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Searched refs:regRLC_CGCG_CGLS_CTRL_3D (Results 1 – 6 of 6) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v12_0.c3916 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); in gfx_v12_0_update_coarse_grain_clock_gating()
3931 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); in gfx_v12_0_update_coarse_grain_clock_gating()
3974 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); in gfx_v12_0_update_coarse_grain_clock_gating()
3982 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); in gfx_v12_0_update_coarse_grain_clock_gating()
4141 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); in gfx_v12_0_get_clockgating_state()
H A Dgfx_v11_0.c5272 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); in gfx_v11_0_update_coarse_grain_clock_gating()
5287 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5330 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); in gfx_v11_0_update_coarse_grain_clock_gating()
5338 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5560 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); in gfx_v11_0_get_clockgating_state()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_5_0_offset.h8705 #define regRLC_CGCG_CGLS_CTRL_3D … macro
H A Dgc_12_0_0_offset.h6530 #define regRLC_CGCG_CGLS_CTRL_3D … macro
H A Dgc_11_0_0_offset.h10040 #define regRLC_CGCG_CGLS_CTRL_3D … macro
H A Dgc_11_0_3_offset.h10642 #define regRLC_CGCG_CGLS_CTRL_3D … macro