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Searched refs:regRLC_CGCG_CGLS_CTRL (Results 1 – 9 of 9) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c1597 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); in gfx_v9_4_3_xcc_rlc_resume()
2637 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); in gfx_v9_4_3_xcc_update_coarse_grain_clock_gating()
2646 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); in gfx_v9_4_3_xcc_update_coarse_grain_clock_gating()
2655 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); in gfx_v9_4_3_xcc_update_coarse_grain_clock_gating()
2660 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); in gfx_v9_4_3_xcc_update_coarse_grain_clock_gating()
2753 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL)); in gfx_v9_4_3_get_clockgating_state()
H A Dgfx_v12_0.c2008 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); in gfx_v12_0_rlc_resume()
3898 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v12_0_update_coarse_grain_clock_gating()
3913 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); in gfx_v12_0_update_coarse_grain_clock_gating()
3962 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v12_0_update_coarse_grain_clock_gating()
3971 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); in gfx_v12_0_update_coarse_grain_clock_gating()
4132 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v12_0_get_clockgating_state()
H A Dgfx_v11_0.c2386 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); in gfx_v11_0_rlc_resume()
5254 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5269 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5318 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5327 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5551 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v11_0_get_clockgating_state()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h4976 #define regRLC_CGCG_CGLS_CTRL … macro
H A Dgc_9_4_3_offset.h6488 #define regRLC_CGCG_CGLS_CTRL … macro
H A Dgc_11_5_0_offset.h8569 #define regRLC_CGCG_CGLS_CTRL … macro
H A Dgc_12_0_0_offset.h6400 #define regRLC_CGCG_CGLS_CTRL … macro
H A Dgc_11_0_0_offset.h9898 #define regRLC_CGCG_CGLS_CTRL … macro
H A Dgc_11_0_3_offset.h10500 #define regRLC_CGCG_CGLS_CTRL … macro