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Searched refs:regPHYESYMCLK_CLOCK_CNTL_BASE_IDX (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h379 #define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h1389 #define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h1368 #define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h233 #define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h1530 #define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h438 #define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h233 #define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h227 #define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h249 #define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h640 #define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX … macro