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Searched refs:regOTG0_OTG_DRR_CONTROL_BASE_IDX (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h8619 #define regOTG0_OTG_DRR_CONTROL_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h6747 #define regOTG0_OTG_DRR_CONTROL_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h6726 #define regOTG0_OTG_DRR_CONTROL_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h8101 #define regOTG0_OTG_DRR_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h8007 #define regOTG0_OTG_DRR_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h8954 #define regOTG0_OTG_DRR_CONTROL_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h8102 #define regOTG0_OTG_DRR_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h8715 #define regOTG0_OTG_DRR_CONTROL_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h8748 #define regOTG0_OTG_DRR_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h9178 #define regOTG0_OTG_DRR_CONTROL_BASE_IDX … macro