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Searched refs:regMPC_OUT1_CSC_C31_C32_A_BASE_IDX (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h7351 #define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h13143 #define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h13122 #define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h6899 #define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h14209 #define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h7470 #define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h6900 #define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h7229 #define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h7679 #define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h7690 #define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX … macro