1 /* SPDX-License-Identifier: MIT */ 2 /* Copyright 2025 Advanced Micro Devices, Inc. */ 3 4 5 #ifndef _dcn_3_6_0_OFFSET_HEADER 6 #define _dcn_3_6_0_OFFSET_HEADER 7 8 9 10 // addressBlock: dce_dc_hda_azcontroller_azdec 11 // base address: 0x1300000 12 #define regGLOBAL_CAPABILITIES 0x4b7000 13 #define regGLOBAL_CAPABILITIES_BASE_IDX 3 14 #define regMINOR_VERSION 0x4b7000 15 #define regMINOR_VERSION_BASE_IDX 3 16 #define regMAJOR_VERSION 0x4b7000 17 #define regMAJOR_VERSION_BASE_IDX 3 18 #define regOUTPUT_PAYLOAD_CAPABILITY 0x4b7001 19 #define regOUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 3 20 #define regINPUT_PAYLOAD_CAPABILITY 0x4b7001 21 #define regINPUT_PAYLOAD_CAPABILITY_BASE_IDX 3 22 #define regGLOBAL_CONTROL 0x4b7002 23 #define regGLOBAL_CONTROL_BASE_IDX 3 24 #define regWAKE_ENABLE 0x4b7003 25 #define regWAKE_ENABLE_BASE_IDX 3 26 #define regSTATE_CHANGE_STATUS 0x4b7003 27 #define regSTATE_CHANGE_STATUS_BASE_IDX 3 28 #define regGLOBAL_STATUS 0x4b7004 29 #define regGLOBAL_STATUS_BASE_IDX 3 30 #define regOUTPUT_STREAM_PAYLOAD_CAPABILITY 0x4b7006 31 #define regOUTPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX 3 32 #define regINPUT_STREAM_PAYLOAD_CAPABILITY 0x4b7006 33 #define regINPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX 3 34 #define regINTERRUPT_CONTROL 0x4b7008 35 #define regINTERRUPT_CONTROL_BASE_IDX 3 36 #define regINTERRUPT_STATUS 0x4b7009 37 #define regINTERRUPT_STATUS_BASE_IDX 3 38 #define regWALL_CLOCK_COUNTER 0x4b700c 39 #define regWALL_CLOCK_COUNTER_BASE_IDX 3 40 #define regSTREAM_SYNCHRONIZATION 0x4b700e 41 #define regSTREAM_SYNCHRONIZATION_BASE_IDX 3 42 #define regCORB_LOWER_BASE_ADDRESS 0x4b7010 43 #define regCORB_LOWER_BASE_ADDRESS_BASE_IDX 3 44 #define regCORB_UPPER_BASE_ADDRESS 0x4b7011 45 #define regCORB_UPPER_BASE_ADDRESS_BASE_IDX 3 46 #define regAZCONTROLLER0_CORB_WRITE_POINTER 0x4b7012 47 #define regAZCONTROLLER0_CORB_WRITE_POINTER_BASE_IDX 3 48 #define regAZCONTROLLER0_CORB_READ_POINTER 0x4b7012 49 #define regAZCONTROLLER0_CORB_READ_POINTER_BASE_IDX 3 50 #define regAZCONTROLLER0_CORB_CONTROL 0x4b7013 51 #define regAZCONTROLLER0_CORB_CONTROL_BASE_IDX 3 52 #define regAZCONTROLLER0_CORB_STATUS 0x4b7013 53 #define regAZCONTROLLER0_CORB_STATUS_BASE_IDX 3 54 #define regAZCONTROLLER0_CORB_SIZE 0x4b7013 55 #define regAZCONTROLLER0_CORB_SIZE_BASE_IDX 3 56 #define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS 0x4b7014 57 #define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS_BASE_IDX 3 58 #define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS 0x4b7015 59 #define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS_BASE_IDX 3 60 #define regAZCONTROLLER0_RIRB_WRITE_POINTER 0x4b7016 61 #define regAZCONTROLLER0_RIRB_WRITE_POINTER_BASE_IDX 3 62 #define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT 0x4b7016 63 #define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_BASE_IDX 3 64 #define regAZCONTROLLER0_RIRB_CONTROL 0x4b7017 65 #define regAZCONTROLLER0_RIRB_CONTROL_BASE_IDX 3 66 #define regAZCONTROLLER0_RIRB_STATUS 0x4b7017 67 #define regAZCONTROLLER0_RIRB_STATUS_BASE_IDX 3 68 #define regAZCONTROLLER0_RIRB_SIZE 0x4b7017 69 #define regAZCONTROLLER0_RIRB_SIZE_BASE_IDX 3 70 #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x4b7018 71 #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 3 72 #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018 73 #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3 74 #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018 75 #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3 76 #define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE 0x4b7019 77 #define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 3 78 #define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS 0x4b701a 79 #define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS_BASE_IDX 3 80 #define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS 0x4b701c 81 #define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 3 82 #define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS 0x4b701d 83 #define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 3 84 #define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS 0x4b780c 85 #define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX 3 86 87 88 // addressBlock: dce_dc_hda_azendpoint_azdec 89 // base address: 0x1300000 90 #define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018 91 #define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3 92 #define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018 93 #define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3 94 95 96 // addressBlock: dce_dc_hda_azinputendpoint_azdec 97 // base address: 0x1300000 98 #define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x4b7018 99 #define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 3 100 #define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x4b7018 101 #define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 3 102 103 104 // addressBlock: dce_dc_hda_azcontroller_azdec 105 // base address: 0x0 106 #define regAZCONTROLLER1_CORB_WRITE_POINTER 0x0000 107 #define regAZCONTROLLER1_CORB_WRITE_POINTER_BASE_IDX 0 108 #define regAZCONTROLLER1_CORB_READ_POINTER 0x0000 109 #define regAZCONTROLLER1_CORB_READ_POINTER_BASE_IDX 0 110 #define regAZCONTROLLER1_CORB_CONTROL 0x0001 111 #define regAZCONTROLLER1_CORB_CONTROL_BASE_IDX 0 112 #define regAZCONTROLLER1_CORB_STATUS 0x0001 113 #define regAZCONTROLLER1_CORB_STATUS_BASE_IDX 0 114 #define regAZCONTROLLER1_CORB_SIZE 0x0001 115 #define regAZCONTROLLER1_CORB_SIZE_BASE_IDX 0 116 #define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS 0x0002 117 #define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS_BASE_IDX 0 118 #define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS 0x0003 119 #define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS_BASE_IDX 0 120 #define regAZCONTROLLER1_RIRB_WRITE_POINTER 0x0004 121 #define regAZCONTROLLER1_RIRB_WRITE_POINTER_BASE_IDX 0 122 #define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT 0x0004 123 #define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT_BASE_IDX 0 124 #define regAZCONTROLLER1_RIRB_CONTROL 0x0005 125 #define regAZCONTROLLER1_RIRB_CONTROL_BASE_IDX 0 126 #define regAZCONTROLLER1_RIRB_STATUS 0x0005 127 #define regAZCONTROLLER1_RIRB_STATUS_BASE_IDX 0 128 #define regAZCONTROLLER1_RIRB_SIZE 0x0005 129 #define regAZCONTROLLER1_RIRB_SIZE_BASE_IDX 0 130 #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006 131 #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0 132 #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 133 #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 134 #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 135 #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 136 #define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007 137 #define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0 138 #define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS 0x0008 139 #define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS_BASE_IDX 0 140 #define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS 0x000a 141 #define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0 142 #define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS 0x000b 143 #define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0 144 #define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS 0x074c 145 #define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1 146 147 148 // addressBlock: dce_dc_hda_azendpoint_azdec 149 // base address: 0x0 150 #define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 151 #define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 152 #define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 153 #define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 154 155 156 // addressBlock: dce_dc_hda_azinputendpoint_azdec 157 // base address: 0x0 158 #define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006 159 #define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0 160 #define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006 161 #define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0 162 163 164 // addressBlock: dce_dc_dccg_dccg_dfs_dispdec 165 // base address: 0x0 166 #define regDENTIST_DISPCLK_CNTL 0x0064 167 #define regDENTIST_DISPCLK_CNTL_BASE_IDX 1 168 169 170 // addressBlock: dce_dc_dccg_dccg_dispdec 171 // base address: 0x0 172 #define regPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040 173 #define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1 174 #define regPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041 175 #define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1 176 #define regPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042 177 #define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1 178 #define regPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043 179 #define regPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1 180 #define regDP_DTO_DBUF_EN 0x0044 181 #define regDP_DTO_DBUF_EN_BASE_IDX 1 182 #define regDSCCLK3_DTO_PARAM 0x0045 183 #define regDSCCLK3_DTO_PARAM_BASE_IDX 1 184 #define regDPREFCLK_CGTT_BLK_CTRL_REG 0x0048 185 #define regDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 186 #define regDCCG_GATE_DISABLE_CNTL4 0x0049 187 #define regDCCG_GATE_DISABLE_CNTL4_BASE_IDX 1 188 #define regDPSTREAMCLK_CNTL 0x004a 189 #define regDPSTREAMCLK_CNTL_BASE_IDX 1 190 #define regREFCLK_CGTT_BLK_CTRL_REG 0x004b 191 #define regREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 192 #define regPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c 193 #define regPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1 194 #define regDCCG_PERFMON_CNTL2 0x004e 195 #define regDCCG_PERFMON_CNTL2_BASE_IDX 1 196 #define regDCCG_GLOBAL_FGCG_REP_CNTL 0x0050 197 #define regDCCG_GLOBAL_FGCG_REP_CNTL_BASE_IDX 1 198 #define regDCCG_DS_DTO_INCR 0x0053 199 #define regDCCG_DS_DTO_INCR_BASE_IDX 1 200 #define regDCCG_DS_DTO_MODULO 0x0054 201 #define regDCCG_DS_DTO_MODULO_BASE_IDX 1 202 #define regDCCG_DS_CNTL 0x0055 203 #define regDCCG_DS_CNTL_BASE_IDX 1 204 #define regDCCG_DS_HW_CAL_INTERVAL 0x0056 205 #define regDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1 206 #define regDPREFCLK_CNTL 0x0058 207 #define regDPREFCLK_CNTL_BASE_IDX 1 208 #define regDCE_VERSION 0x005e 209 #define regDCE_VERSION_BASE_IDX 1 210 #define regDCCG_GTC_CNTL 0x0060 211 #define regDCCG_GTC_CNTL_BASE_IDX 1 212 #define regDCCG_GTC_DTO_INCR 0x0061 213 #define regDCCG_GTC_DTO_INCR_BASE_IDX 1 214 #define regDCCG_GTC_DTO_MODULO 0x0062 215 #define regDCCG_GTC_DTO_MODULO_BASE_IDX 1 216 #define regDCCG_GTC_CURRENT 0x0063 217 #define regDCCG_GTC_CURRENT_BASE_IDX 1 218 #define regSYMCLK32_SE_CNTL 0x0065 219 #define regSYMCLK32_SE_CNTL_BASE_IDX 1 220 #define regSYMCLK32_LE_CNTL 0x0066 221 #define regSYMCLK32_LE_CNTL_BASE_IDX 1 222 #define regDTBCLK_P_CNTL 0x0068 223 #define regDTBCLK_P_CNTL_BASE_IDX 1 224 #define regDCCG_GATE_DISABLE_CNTL5 0x0069 225 #define regDCCG_GATE_DISABLE_CNTL5_BASE_IDX 1 226 #define regDSCCLK0_DTO_PARAM 0x006c 227 #define regDSCCLK0_DTO_PARAM_BASE_IDX 1 228 #define regDSCCLK1_DTO_PARAM 0x006d 229 #define regDSCCLK1_DTO_PARAM_BASE_IDX 1 230 #define regDSCCLK2_DTO_PARAM 0x006e 231 #define regDSCCLK2_DTO_PARAM_BASE_IDX 1 232 #define regOTG_PIXEL_RATE_DIV 0x006f 233 #define regOTG_PIXEL_RATE_DIV_BASE_IDX 1 234 #define regMILLISECOND_TIME_BASE_DIV 0x0070 235 #define regMILLISECOND_TIME_BASE_DIV_BASE_IDX 1 236 #define regDISPCLK_FREQ_CHANGE_CNTL 0x0071 237 #define regDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1 238 #define regDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072 239 #define regDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1 240 #define regDCCG_PERFMON_CNTL 0x0073 241 #define regDCCG_PERFMON_CNTL_BASE_IDX 1 242 #define regDCCG_GATE_DISABLE_CNTL 0x0074 243 #define regDCCG_GATE_DISABLE_CNTL_BASE_IDX 1 244 #define regDISPCLK_CGTT_BLK_CTRL_REG 0x0075 245 #define regDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 246 #define regSOCCLK_CGTT_BLK_CTRL_REG 0x0076 247 #define regSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 248 #define regDCCG_CAC_STATUS 0x0077 249 #define regDCCG_CAC_STATUS_BASE_IDX 1 250 #define regMICROSECOND_TIME_BASE_DIV 0x007b 251 #define regMICROSECOND_TIME_BASE_DIV_BASE_IDX 1 252 #define regDCCG_GATE_DISABLE_CNTL2 0x007c 253 #define regDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1 254 #define regSYMCLK_CGTT_BLK_CTRL_REG 0x007d 255 #define regSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 256 #define regDCCG_DISP_CNTL_REG 0x007f 257 #define regDCCG_DISP_CNTL_REG_BASE_IDX 1 258 #define regOTG0_PIXEL_RATE_CNTL 0x0080 259 #define regOTG0_PIXEL_RATE_CNTL_BASE_IDX 1 260 #define regDP_DTO0_PHASE 0x0081 261 #define regDP_DTO0_PHASE_BASE_IDX 1 262 #define regDP_DTO0_MODULO 0x0082 263 #define regDP_DTO0_MODULO_BASE_IDX 1 264 #define regOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083 265 #define regOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 266 #define regOTG1_PIXEL_RATE_CNTL 0x0084 267 #define regOTG1_PIXEL_RATE_CNTL_BASE_IDX 1 268 #define regDP_DTO1_PHASE 0x0085 269 #define regDP_DTO1_PHASE_BASE_IDX 1 270 #define regDP_DTO1_MODULO 0x0086 271 #define regDP_DTO1_MODULO_BASE_IDX 1 272 #define regOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087 273 #define regOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 274 #define regOTG2_PIXEL_RATE_CNTL 0x0088 275 #define regOTG2_PIXEL_RATE_CNTL_BASE_IDX 1 276 #define regDP_DTO2_PHASE 0x0089 277 #define regDP_DTO2_PHASE_BASE_IDX 1 278 #define regDP_DTO2_MODULO 0x008a 279 #define regDP_DTO2_MODULO_BASE_IDX 1 280 #define regOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b 281 #define regOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 282 #define regOTG3_PIXEL_RATE_CNTL 0x008c 283 #define regOTG3_PIXEL_RATE_CNTL_BASE_IDX 1 284 #define regDP_DTO3_PHASE 0x008d 285 #define regDP_DTO3_PHASE_BASE_IDX 1 286 #define regDP_DTO3_MODULO 0x008e 287 #define regDP_DTO3_MODULO_BASE_IDX 1 288 #define regOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f 289 #define regOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 290 #define regDPPCLK_CGTT_BLK_CTRL_REG 0x0098 291 #define regDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 292 #define regDPPCLK0_DTO_PARAM 0x0099 293 #define regDPPCLK0_DTO_PARAM_BASE_IDX 1 294 #define regDPPCLK1_DTO_PARAM 0x009a 295 #define regDPPCLK1_DTO_PARAM_BASE_IDX 1 296 #define regDPPCLK2_DTO_PARAM 0x009b 297 #define regDPPCLK2_DTO_PARAM_BASE_IDX 1 298 #define regDPPCLK3_DTO_PARAM 0x009c 299 #define regDPPCLK3_DTO_PARAM_BASE_IDX 1 300 #define regDCCG_CAC_STATUS2 0x009f 301 #define regDCCG_CAC_STATUS2_BASE_IDX 1 302 #define regSYMCLKA_CLOCK_ENABLE 0x00a0 303 #define regSYMCLKA_CLOCK_ENABLE_BASE_IDX 1 304 #define regSYMCLKB_CLOCK_ENABLE 0x00a1 305 #define regSYMCLKB_CLOCK_ENABLE_BASE_IDX 1 306 #define regSYMCLKC_CLOCK_ENABLE 0x00a2 307 #define regSYMCLKC_CLOCK_ENABLE_BASE_IDX 1 308 #define regSYMCLKD_CLOCK_ENABLE 0x00a3 309 #define regSYMCLKD_CLOCK_ENABLE_BASE_IDX 1 310 #define regSYMCLKE_CLOCK_ENABLE 0x00a4 311 #define regSYMCLKE_CLOCK_ENABLE_BASE_IDX 1 312 #define regDCCG_SOFT_RESET 0x00a6 313 #define regDCCG_SOFT_RESET_BASE_IDX 1 314 #define regDSCCLK_DTO_CTRL 0x00a7 315 #define regDSCCLK_DTO_CTRL_BASE_IDX 1 316 #define regDPPCLK_CTRL 0x00a8 317 #define regDPPCLK_CTRL_BASE_IDX 1 318 #define regDCCG_GATE_DISABLE_CNTL6 0x00a9 319 #define regDCCG_GATE_DISABLE_CNTL6_BASE_IDX 1 320 #define regSYMCLK_PSP_CNTL 0x00aa 321 #define regSYMCLK_PSP_CNTL_BASE_IDX 1 322 #define regDCCG_AUDIO_DTO_SOURCE 0x00ab 323 #define regDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1 324 #define regDCCG_AUDIO_DTO0_PHASE 0x00ac 325 #define regDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1 326 #define regDCCG_AUDIO_DTO0_MODULE 0x00ad 327 #define regDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1 328 #define regDCCG_AUDIO_DTO1_PHASE 0x00ae 329 #define regDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1 330 #define regDCCG_AUDIO_DTO1_MODULE 0x00af 331 #define regDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1 332 #define regDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0 333 #define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1 334 #define regDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1 335 #define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1 336 #define regDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2 337 #define regDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1 338 #define regDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3 339 #define regDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1 340 #define regDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4 341 #define regDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1 342 #define regDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5 343 #define regDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1 344 #define regDPPCLK_DTO_CTRL 0x00b6 345 #define regDPPCLK_DTO_CTRL_BASE_IDX 1 346 #define regDCCG_VSYNC_CNT_CTRL 0x00b8 347 #define regDCCG_VSYNC_CNT_CTRL_BASE_IDX 1 348 #define regDCCG_VSYNC_CNT_INT_CTRL 0x00b9 349 #define regDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1 350 #define regFORCE_SYMCLK_DISABLE 0x00ba 351 #define regFORCE_SYMCLK_DISABLE_BASE_IDX 1 352 #define regDTBCLK_DTO0_PHASE 0x0018 353 #define regDTBCLK_DTO0_PHASE_BASE_IDX 2 354 #define regDTBCLK_DTO1_PHASE 0x0019 355 #define regDTBCLK_DTO1_PHASE_BASE_IDX 2 356 #define regDTBCLK_DTO2_PHASE 0x001a 357 #define regDTBCLK_DTO2_PHASE_BASE_IDX 2 358 #define regDTBCLK_DTO3_PHASE 0x001b 359 #define regDTBCLK_DTO3_PHASE_BASE_IDX 2 360 #define regDTBCLK_DTO0_MODULO 0x001f 361 #define regDTBCLK_DTO0_MODULO_BASE_IDX 2 362 #define regDTBCLK_DTO1_MODULO 0x0020 363 #define regDTBCLK_DTO1_MODULO_BASE_IDX 2 364 #define regDTBCLK_DTO2_MODULO 0x0021 365 #define regDTBCLK_DTO2_MODULO_BASE_IDX 2 366 #define regDTBCLK_DTO3_MODULO 0x0022 367 #define regDTBCLK_DTO3_MODULO_BASE_IDX 2 368 #define regHDMICHARCLK0_CLOCK_CNTL 0x004a 369 #define regHDMICHARCLK0_CLOCK_CNTL_BASE_IDX 2 370 #define regPHYASYMCLK_CLOCK_CNTL 0x0052 371 #define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX 2 372 #define regPHYBSYMCLK_CLOCK_CNTL 0x0053 373 #define regPHYBSYMCLK_CLOCK_CNTL_BASE_IDX 2 374 #define regPHYCSYMCLK_CLOCK_CNTL 0x0054 375 #define regPHYCSYMCLK_CLOCK_CNTL_BASE_IDX 2 376 #define regPHYDSYMCLK_CLOCK_CNTL 0x0055 377 #define regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX 2 378 #define regPHYESYMCLK_CLOCK_CNTL 0x0056 379 #define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX 2 380 #define regHDMISTREAMCLK_CNTL 0x0059 381 #define regHDMISTREAMCLK_CNTL_BASE_IDX 2 382 #define regDCCG_GATE_DISABLE_CNTL3 0x005a 383 #define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX 2 384 #define regHDMISTREAMCLK0_DTO_PARAM 0x005b 385 #define regHDMISTREAMCLK0_DTO_PARAM_BASE_IDX 2 386 #define regDCCG_AUDIO_DTBCLK_DTO_PHASE 0x0061 387 #define regDCCG_AUDIO_DTBCLK_DTO_PHASE_BASE_IDX 2 388 #define regDCCG_AUDIO_DTBCLK_DTO_MODULO 0x0062 389 #define regDCCG_AUDIO_DTBCLK_DTO_MODULO_BASE_IDX 2 390 #define regDTBCLK_DTO_DBUF_EN 0x0063 391 #define regDTBCLK_DTO_DBUF_EN_BASE_IDX 2 392 393 394 // addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec 395 // base address: 0x0 396 #define regDC_PERFMON0_PERFCOUNTER_CNTL 0x0000 397 #define regDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2 398 #define regDC_PERFMON0_PERFCOUNTER_CNTL2 0x0001 399 #define regDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2 400 #define regDC_PERFMON0_PERFCOUNTER_STATE 0x0002 401 #define regDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2 402 #define regDC_PERFMON0_PERFMON_CNTL 0x0003 403 #define regDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2 404 #define regDC_PERFMON0_PERFMON_CNTL2 0x0004 405 #define regDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2 406 #define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0005 407 #define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 408 #define regDC_PERFMON0_PERFMON_CVALUE_LOW 0x0006 409 #define regDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2 410 #define regDC_PERFMON0_PERFMON_HI 0x0007 411 #define regDC_PERFMON0_PERFMON_HI_BASE_IDX 2 412 #define regDC_PERFMON0_PERFMON_LOW 0x0008 413 #define regDC_PERFMON0_PERFMON_LOW_BASE_IDX 2 414 415 416 // addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec 417 // base address: 0x30 418 #define regDC_PERFMON1_PERFCOUNTER_CNTL 0x000c 419 #define regDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2 420 #define regDC_PERFMON1_PERFCOUNTER_CNTL2 0x000d 421 #define regDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2 422 #define regDC_PERFMON1_PERFCOUNTER_STATE 0x000e 423 #define regDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2 424 #define regDC_PERFMON1_PERFMON_CNTL 0x000f 425 #define regDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2 426 #define regDC_PERFMON1_PERFMON_CNTL2 0x0010 427 #define regDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2 428 #define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x0011 429 #define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 430 #define regDC_PERFMON1_PERFMON_CVALUE_LOW 0x0012 431 #define regDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2 432 #define regDC_PERFMON1_PERFMON_HI 0x0013 433 #define regDC_PERFMON1_PERFMON_HI_BASE_IDX 2 434 #define regDC_PERFMON1_PERFMON_LOW 0x0014 435 #define regDC_PERFMON1_PERFMON_LOW_BASE_IDX 2 436 437 438 // addressBlock: dce_dc_dmu_fgsec_dispdec 439 // base address: 0x0 440 #define regDMCUB_RBBMIF_SEC_CNTL 0x017a 441 #define regDMCUB_RBBMIF_SEC_CNTL_BASE_IDX 2 442 443 444 // addressBlock: dce_dc_dmu_rbbmif_dispdec 445 // base address: 0x0 446 #define regRBBMIF_TIMEOUT 0x017f 447 #define regRBBMIF_TIMEOUT_BASE_IDX 2 448 #define regRBBMIF_STATUS 0x0180 449 #define regRBBMIF_STATUS_BASE_IDX 2 450 #define regRBBMIF_STATUS_2 0x0181 451 #define regRBBMIF_STATUS_2_BASE_IDX 2 452 #define regRBBMIF_INT_STATUS 0x0182 453 #define regRBBMIF_INT_STATUS_BASE_IDX 2 454 #define regRBBMIF_TIMEOUT_DIS 0x0183 455 #define regRBBMIF_TIMEOUT_DIS_BASE_IDX 2 456 #define regRBBMIF_TIMEOUT_DIS_2 0x0184 457 #define regRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2 458 #define regRBBMIF_STATUS_FLAG 0x0185 459 #define regRBBMIF_STATUS_FLAG_BASE_IDX 2 460 461 462 // addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec 463 // base address: 0x2f8 464 #define regDC_PERFMON2_PERFCOUNTER_CNTL 0x00be 465 #define regDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2 466 #define regDC_PERFMON2_PERFCOUNTER_CNTL2 0x00bf 467 #define regDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2 468 #define regDC_PERFMON2_PERFCOUNTER_STATE 0x00c0 469 #define regDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2 470 #define regDC_PERFMON2_PERFMON_CNTL 0x00c1 471 #define regDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2 472 #define regDC_PERFMON2_PERFMON_CNTL2 0x00c2 473 #define regDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2 474 #define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x00c3 475 #define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 476 #define regDC_PERFMON2_PERFMON_CVALUE_LOW 0x00c4 477 #define regDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2 478 #define regDC_PERFMON2_PERFMON_HI 0x00c5 479 #define regDC_PERFMON2_PERFMON_HI_BASE_IDX 2 480 #define regDC_PERFMON2_PERFMON_LOW 0x00c6 481 #define regDC_PERFMON2_PERFMON_LOW_BASE_IDX 2 482 483 484 // addressBlock: dce_dc_dmu_ihc_dispdec 485 // base address: 0x0 486 #define regDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126 487 #define regDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2 488 #define regDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127 489 #define regDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2 490 #define regDC_GPU_TIMER_READ 0x0128 491 #define regDC_GPU_TIMER_READ_BASE_IDX 2 492 #define regDC_GPU_TIMER_READ_CNTL 0x0129 493 #define regDC_GPU_TIMER_READ_CNTL_BASE_IDX 2 494 #define regDISP_INTERRUPT_STATUS 0x012a 495 #define regDISP_INTERRUPT_STATUS_BASE_IDX 2 496 #define regDISP_INTERRUPT_STATUS_CONTINUE 0x012b 497 #define regDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 498 #define regDISP_INTERRUPT_STATUS_CONTINUE2 0x012c 499 #define regDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2 500 #define regDISP_INTERRUPT_STATUS_CONTINUE3 0x012d 501 #define regDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2 502 #define regDISP_INTERRUPT_STATUS_CONTINUE4 0x012e 503 #define regDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2 504 #define regDISP_INTERRUPT_STATUS_CONTINUE5 0x012f 505 #define regDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2 506 #define regDISP_INTERRUPT_STATUS_CONTINUE6 0x0130 507 #define regDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2 508 #define regDISP_INTERRUPT_STATUS_CONTINUE7 0x0131 509 #define regDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2 510 #define regDISP_INTERRUPT_STATUS_CONTINUE8 0x0132 511 #define regDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2 512 #define regDISP_INTERRUPT_STATUS_CONTINUE9 0x0133 513 #define regDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2 514 #define regDISP_INTERRUPT_STATUS_CONTINUE10 0x0134 515 #define regDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2 516 #define regDISP_INTERRUPT_STATUS_CONTINUE11 0x0135 517 #define regDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2 518 #define regDISP_INTERRUPT_STATUS_CONTINUE12 0x0136 519 #define regDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2 520 #define regDISP_INTERRUPT_STATUS_CONTINUE13 0x0137 521 #define regDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2 522 #define regDISP_INTERRUPT_STATUS_CONTINUE14 0x0138 523 #define regDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2 524 #define regDISP_INTERRUPT_STATUS_CONTINUE15 0x0139 525 #define regDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2 526 #define regDISP_INTERRUPT_STATUS_CONTINUE16 0x013a 527 #define regDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2 528 #define regDISP_INTERRUPT_STATUS_CONTINUE17 0x013b 529 #define regDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2 530 #define regDISP_INTERRUPT_STATUS_CONTINUE18 0x013c 531 #define regDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2 532 #define regDISP_INTERRUPT_STATUS_CONTINUE19 0x013d 533 #define regDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2 534 #define regDISP_INTERRUPT_STATUS_CONTINUE20 0x013e 535 #define regDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2 536 #define regDISP_INTERRUPT_STATUS_CONTINUE21 0x013f 537 #define regDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2 538 #define regDISP_INTERRUPT_STATUS_CONTINUE22 0x0140 539 #define regDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2 540 #define regDC_GPU_TIMER_START_POSITION_VREADY 0x0141 541 #define regDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2 542 #define regDC_GPU_TIMER_START_POSITION_FLIP 0x0142 543 #define regDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2 544 #define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143 545 #define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2 546 #define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144 547 #define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2 548 #define regDISP_INTERRUPT_STATUS_CONTINUE23 0x0145 549 #define regDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX 2 550 #define regDISP_INTERRUPT_STATUS_CONTINUE24 0x0146 551 #define regDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX 2 552 #define regDISP_INTERRUPT_STATUS_CONTINUE25 0x0147 553 #define regDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX 2 554 #define regDCCG_INTERRUPT_DEST 0x0148 555 #define regDCCG_INTERRUPT_DEST_BASE_IDX 2 556 #define regDMU_INTERRUPT_DEST 0x0149 557 #define regDMU_INTERRUPT_DEST_BASE_IDX 2 558 #define regDMU_INTERRUPT_DEST2 0x014a 559 #define regDMU_INTERRUPT_DEST2_BASE_IDX 2 560 #define regDCPG_INTERRUPT_DEST 0x014b 561 #define regDCPG_INTERRUPT_DEST_BASE_IDX 2 562 #define regDCPG_INTERRUPT_DEST2 0x014c 563 #define regDCPG_INTERRUPT_DEST2_BASE_IDX 2 564 #define regMMHUBBUB_INTERRUPT_DEST 0x014d 565 #define regMMHUBBUB_INTERRUPT_DEST_BASE_IDX 2 566 #define regWB_INTERRUPT_DEST 0x014e 567 #define regWB_INTERRUPT_DEST_BASE_IDX 2 568 #define regDCHUB_INTERRUPT_DEST 0x014f 569 #define regDCHUB_INTERRUPT_DEST_BASE_IDX 2 570 #define regDCHUB_PERFCOUNTER_INTERRUPT_DEST 0x0150 571 #define regDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 572 #define regDCHUB_INTERRUPT_DEST2 0x0151 573 #define regDCHUB_INTERRUPT_DEST2_BASE_IDX 2 574 #define regDPP_PERFCOUNTER_INTERRUPT_DEST 0x0152 575 #define regDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 576 #define regMPC_INTERRUPT_DEST 0x0153 577 #define regMPC_INTERRUPT_DEST_BASE_IDX 2 578 #define regOPP_INTERRUPT_DEST 0x0154 579 #define regOPP_INTERRUPT_DEST_BASE_IDX 2 580 #define regOPTC_INTERRUPT_DEST 0x0155 581 #define regOPTC_INTERRUPT_DEST_BASE_IDX 2 582 #define regOTG0_INTERRUPT_DEST 0x0156 583 #define regOTG0_INTERRUPT_DEST_BASE_IDX 2 584 #define regOTG1_INTERRUPT_DEST 0x0157 585 #define regOTG1_INTERRUPT_DEST_BASE_IDX 2 586 #define regOTG2_INTERRUPT_DEST 0x0158 587 #define regOTG2_INTERRUPT_DEST_BASE_IDX 2 588 #define regOTG3_INTERRUPT_DEST 0x0159 589 #define regOTG3_INTERRUPT_DEST_BASE_IDX 2 590 #define regOTG4_INTERRUPT_DEST 0x015a 591 #define regOTG4_INTERRUPT_DEST_BASE_IDX 2 592 #define regOTG5_INTERRUPT_DEST 0x015b 593 #define regOTG5_INTERRUPT_DEST_BASE_IDX 2 594 #define regDIG_INTERRUPT_DEST 0x015c 595 #define regDIG_INTERRUPT_DEST_BASE_IDX 2 596 #define regI2C_DDC_HPD_INTERRUPT_DEST 0x015d 597 #define regI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX 2 598 #define regDIO_INTERRUPT_DEST 0x015f 599 #define regDIO_INTERRUPT_DEST_BASE_IDX 2 600 #define regDCIO_INTERRUPT_DEST 0x0160 601 #define regDCIO_INTERRUPT_DEST_BASE_IDX 2 602 #define regHPD_INTERRUPT_DEST 0x0161 603 #define regHPD_INTERRUPT_DEST_BASE_IDX 2 604 #define regAZ_INTERRUPT_DEST 0x0162 605 #define regAZ_INTERRUPT_DEST_BASE_IDX 2 606 #define regAUX_INTERRUPT_DEST 0x0163 607 #define regAUX_INTERRUPT_DEST_BASE_IDX 2 608 #define regDSC_INTERRUPT_DEST 0x0164 609 #define regDSC_INTERRUPT_DEST_BASE_IDX 2 610 #define regHPO_INTERRUPT_DEST 0x0165 611 #define regHPO_INTERRUPT_DEST_BASE_IDX 2 612 613 614 // addressBlock: dce_dc_dmu_dmu_misc_dispdec 615 // base address: 0x0 616 #define regCC_DC_PIPE_DIS 0x00ca 617 #define regCC_DC_PIPE_DIS_BASE_IDX 2 618 #define regDMU_CLK_CNTL 0x00cb 619 #define regDMU_CLK_CNTL_BASE_IDX 2 620 #define regDMCUB_SMU_INTERRUPT_CNTL 0x00cd 621 #define regDMCUB_SMU_INTERRUPT_CNTL_BASE_IDX 2 622 #define regSMU_INTERRUPT_CONTROL 0x00ce 623 #define regSMU_INTERRUPT_CONTROL_BASE_IDX 2 624 #define regZSC_CNTL 0x00cf 625 #define regZSC_CNTL_BASE_IDX 2 626 #define regZSC_CNTL2 0x00d0 627 #define regZSC_CNTL2_BASE_IDX 2 628 #define regDMU_MISC_ALLOW_DS_FORCE 0x00d6 629 #define regDMU_MISC_ALLOW_DS_FORCE_BASE_IDX 2 630 #define regZSC_STATUS 0x00d7 631 #define regZSC_STATUS_BASE_IDX 2 632 #define regDMU_DISPCLK_CGTT_BLK_CTRL_REG 0x00d8 633 #define regDMU_DISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 2 634 #define regDMU_SOCCLK_CGTT_BLK_CTRL_REG 0x00d9 635 #define regDMU_SOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 2 636 #define regZPR_CLK_UNGATE_DELAY 0x00da 637 #define regZPR_CLK_UNGATE_DELAY_BASE_IDX 2 638 639 640 // addressBlock: dce_dc_dmu_dc_pg_dispdec 641 // base address: 0x0 642 #define regDOMAIN0_PG_CONFIG 0x0080 643 #define regDOMAIN0_PG_CONFIG_BASE_IDX 2 644 #define regDOMAIN0_PG_STATUS 0x0081 645 #define regDOMAIN0_PG_STATUS_BASE_IDX 2 646 #define regDOMAIN1_PG_CONFIG 0x0082 647 #define regDOMAIN1_PG_CONFIG_BASE_IDX 2 648 #define regDOMAIN1_PG_STATUS 0x0083 649 #define regDOMAIN1_PG_STATUS_BASE_IDX 2 650 #define regDOMAIN2_PG_CONFIG 0x0084 651 #define regDOMAIN2_PG_CONFIG_BASE_IDX 2 652 #define regDOMAIN2_PG_STATUS 0x0085 653 #define regDOMAIN2_PG_STATUS_BASE_IDX 2 654 #define regDOMAIN3_PG_CONFIG 0x0086 655 #define regDOMAIN3_PG_CONFIG_BASE_IDX 2 656 #define regDOMAIN3_PG_STATUS 0x0087 657 #define regDOMAIN3_PG_STATUS_BASE_IDX 2 658 #define regDOMAIN16_PG_CONFIG 0x0089 659 #define regDOMAIN16_PG_CONFIG_BASE_IDX 2 660 #define regDOMAIN16_PG_STATUS 0x008a 661 #define regDOMAIN16_PG_STATUS_BASE_IDX 2 662 #define regDOMAIN17_PG_CONFIG 0x008b 663 #define regDOMAIN17_PG_CONFIG_BASE_IDX 2 664 #define regDOMAIN17_PG_STATUS 0x008c 665 #define regDOMAIN17_PG_STATUS_BASE_IDX 2 666 #define regDOMAIN18_PG_CONFIG 0x008d 667 #define regDOMAIN18_PG_CONFIG_BASE_IDX 2 668 #define regDOMAIN18_PG_STATUS 0x008e 669 #define regDOMAIN18_PG_STATUS_BASE_IDX 2 670 #define regDOMAIN19_PG_CONFIG 0x008f 671 #define regDOMAIN19_PG_CONFIG_BASE_IDX 2 672 #define regDOMAIN19_PG_STATUS 0x0090 673 #define regDOMAIN19_PG_STATUS_BASE_IDX 2 674 #define regDOMAIN22_PG_CONFIG 0x0092 675 #define regDOMAIN22_PG_CONFIG_BASE_IDX 2 676 #define regDOMAIN22_PG_STATUS 0x0093 677 #define regDOMAIN22_PG_STATUS_BASE_IDX 2 678 #define regDOMAIN23_PG_CONFIG 0x0094 679 #define regDOMAIN23_PG_CONFIG_BASE_IDX 2 680 #define regDOMAIN23_PG_STATUS 0x0095 681 #define regDOMAIN23_PG_STATUS_BASE_IDX 2 682 #define regDOMAIN24_PG_CONFIG 0x0096 683 #define regDOMAIN24_PG_CONFIG_BASE_IDX 2 684 #define regDOMAIN24_PG_STATUS 0x0097 685 #define regDOMAIN24_PG_STATUS_BASE_IDX 2 686 #define regDOMAIN25_PG_CONFIG 0x0098 687 #define regDOMAIN25_PG_CONFIG_BASE_IDX 2 688 #define regDOMAIN25_PG_STATUS 0x0099 689 #define regDOMAIN25_PG_STATUS_BASE_IDX 2 690 #define regDCPG_INTERRUPT_STATUS 0x009a 691 #define regDCPG_INTERRUPT_STATUS_BASE_IDX 2 692 #define regDCPG_INTERRUPT_STATUS_2 0x009b 693 #define regDCPG_INTERRUPT_STATUS_2_BASE_IDX 2 694 #define regDCPG_INTERRUPT_STATUS_3 0x009c 695 #define regDCPG_INTERRUPT_STATUS_3_BASE_IDX 2 696 #define regDCPG_INTERRUPT_CONTROL_1 0x009d 697 #define regDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2 698 #define regDCPG_INTERRUPT_CONTROL_2 0x009e 699 #define regDCPG_INTERRUPT_CONTROL_2_BASE_IDX 2 700 #define regDCPG_INTERRUPT_CONTROL_3 0x009f 701 #define regDCPG_INTERRUPT_CONTROL_3_BASE_IDX 2 702 #define regDC_IP_REQUEST_CNTL 0x00a0 703 #define regDC_IP_REQUEST_CNTL_BASE_IDX 2 704 #define regLONO_MEM_PWR_REQ_CNTL 0x00a4 705 #define regLONO_MEM_PWR_REQ_CNTL_BASE_IDX 2 706 707 708 // addressBlock: dce_dc_dmu_dmcub_dispdec 709 // base address: 0x0 710 #define regDMCUB_REGION0_OFFSET 0x018e 711 #define regDMCUB_REGION0_OFFSET_BASE_IDX 2 712 #define regDMCUB_REGION0_OFFSET_HIGH 0x018f 713 #define regDMCUB_REGION0_OFFSET_HIGH_BASE_IDX 2 714 #define regDMCUB_REGION1_OFFSET 0x0190 715 #define regDMCUB_REGION1_OFFSET_BASE_IDX 2 716 #define regDMCUB_REGION1_OFFSET_HIGH 0x0191 717 #define regDMCUB_REGION1_OFFSET_HIGH_BASE_IDX 2 718 #define regDMCUB_REGION2_OFFSET 0x0192 719 #define regDMCUB_REGION2_OFFSET_BASE_IDX 2 720 #define regDMCUB_REGION2_OFFSET_HIGH 0x0193 721 #define regDMCUB_REGION2_OFFSET_HIGH_BASE_IDX 2 722 #define regDMCUB_REGION4_OFFSET 0x0196 723 #define regDMCUB_REGION4_OFFSET_BASE_IDX 2 724 #define regDMCUB_REGION4_OFFSET_HIGH 0x0197 725 #define regDMCUB_REGION4_OFFSET_HIGH_BASE_IDX 2 726 #define regDMCUB_REGION5_OFFSET 0x0198 727 #define regDMCUB_REGION5_OFFSET_BASE_IDX 2 728 #define regDMCUB_REGION5_OFFSET_HIGH 0x0199 729 #define regDMCUB_REGION5_OFFSET_HIGH_BASE_IDX 2 730 #define regDMCUB_REGION6_OFFSET 0x019a 731 #define regDMCUB_REGION6_OFFSET_BASE_IDX 2 732 #define regDMCUB_REGION6_OFFSET_HIGH 0x019b 733 #define regDMCUB_REGION6_OFFSET_HIGH_BASE_IDX 2 734 #define regDMCUB_REGION7_OFFSET 0x019c 735 #define regDMCUB_REGION7_OFFSET_BASE_IDX 2 736 #define regDMCUB_REGION7_OFFSET_HIGH 0x019d 737 #define regDMCUB_REGION7_OFFSET_HIGH_BASE_IDX 2 738 #define regDMCUB_REGION0_TOP_ADDRESS 0x019e 739 #define regDMCUB_REGION0_TOP_ADDRESS_BASE_IDX 2 740 #define regDMCUB_REGION1_TOP_ADDRESS 0x019f 741 #define regDMCUB_REGION1_TOP_ADDRESS_BASE_IDX 2 742 #define regDMCUB_REGION2_TOP_ADDRESS 0x01a0 743 #define regDMCUB_REGION2_TOP_ADDRESS_BASE_IDX 2 744 #define regDMCUB_REGION4_TOP_ADDRESS 0x01a1 745 #define regDMCUB_REGION4_TOP_ADDRESS_BASE_IDX 2 746 #define regDMCUB_REGION5_TOP_ADDRESS 0x01a2 747 #define regDMCUB_REGION5_TOP_ADDRESS_BASE_IDX 2 748 #define regDMCUB_REGION6_TOP_ADDRESS 0x01a3 749 #define regDMCUB_REGION6_TOP_ADDRESS_BASE_IDX 2 750 #define regDMCUB_REGION7_TOP_ADDRESS 0x01a4 751 #define regDMCUB_REGION7_TOP_ADDRESS_BASE_IDX 2 752 #define regDMCUB_REGION3_CW0_BASE_ADDRESS 0x01a5 753 #define regDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX 2 754 #define regDMCUB_REGION3_CW1_BASE_ADDRESS 0x01a6 755 #define regDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX 2 756 #define regDMCUB_REGION3_CW2_BASE_ADDRESS 0x01a7 757 #define regDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX 2 758 #define regDMCUB_REGION3_CW3_BASE_ADDRESS 0x01a8 759 #define regDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX 2 760 #define regDMCUB_REGION3_CW4_BASE_ADDRESS 0x01a9 761 #define regDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX 2 762 #define regDMCUB_REGION3_CW5_BASE_ADDRESS 0x01aa 763 #define regDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX 2 764 #define regDMCUB_REGION3_CW6_BASE_ADDRESS 0x01ab 765 #define regDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX 2 766 #define regDMCUB_REGION3_CW7_BASE_ADDRESS 0x01ac 767 #define regDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX 2 768 #define regDMCUB_REGION3_CW0_TOP_ADDRESS 0x01ad 769 #define regDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX 2 770 #define regDMCUB_REGION3_CW1_TOP_ADDRESS 0x01ae 771 #define regDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX 2 772 #define regDMCUB_REGION3_CW2_TOP_ADDRESS 0x01af 773 #define regDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX 2 774 #define regDMCUB_REGION3_CW3_TOP_ADDRESS 0x01b0 775 #define regDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX 2 776 #define regDMCUB_REGION3_CW4_TOP_ADDRESS 0x01b1 777 #define regDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX 2 778 #define regDMCUB_REGION3_CW5_TOP_ADDRESS 0x01b2 779 #define regDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX 2 780 #define regDMCUB_REGION3_CW6_TOP_ADDRESS 0x01b3 781 #define regDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX 2 782 #define regDMCUB_REGION3_CW7_TOP_ADDRESS 0x01b4 783 #define regDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX 2 784 #define regDMCUB_REGION3_CW0_OFFSET 0x01b5 785 #define regDMCUB_REGION3_CW0_OFFSET_BASE_IDX 2 786 #define regDMCUB_REGION3_CW0_OFFSET_HIGH 0x01b6 787 #define regDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX 2 788 #define regDMCUB_REGION3_CW1_OFFSET 0x01b7 789 #define regDMCUB_REGION3_CW1_OFFSET_BASE_IDX 2 790 #define regDMCUB_REGION3_CW1_OFFSET_HIGH 0x01b8 791 #define regDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX 2 792 #define regDMCUB_REGION3_CW2_OFFSET 0x01b9 793 #define regDMCUB_REGION3_CW2_OFFSET_BASE_IDX 2 794 #define regDMCUB_REGION3_CW2_OFFSET_HIGH 0x01ba 795 #define regDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX 2 796 #define regDMCUB_REGION3_CW3_OFFSET 0x01bb 797 #define regDMCUB_REGION3_CW3_OFFSET_BASE_IDX 2 798 #define regDMCUB_REGION3_CW3_OFFSET_HIGH 0x01bc 799 #define regDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX 2 800 #define regDMCUB_REGION3_CW4_OFFSET 0x01bd 801 #define regDMCUB_REGION3_CW4_OFFSET_BASE_IDX 2 802 #define regDMCUB_REGION3_CW4_OFFSET_HIGH 0x01be 803 #define regDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX 2 804 #define regDMCUB_REGION3_CW5_OFFSET 0x01bf 805 #define regDMCUB_REGION3_CW5_OFFSET_BASE_IDX 2 806 #define regDMCUB_REGION3_CW5_OFFSET_HIGH 0x01c0 807 #define regDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX 2 808 #define regDMCUB_REGION3_CW6_OFFSET 0x01c1 809 #define regDMCUB_REGION3_CW6_OFFSET_BASE_IDX 2 810 #define regDMCUB_REGION3_CW6_OFFSET_HIGH 0x01c2 811 #define regDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX 2 812 #define regDMCUB_REGION3_CW7_OFFSET 0x01c3 813 #define regDMCUB_REGION3_CW7_OFFSET_BASE_IDX 2 814 #define regDMCUB_REGION3_CW7_OFFSET_HIGH 0x01c4 815 #define regDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX 2 816 #define regDMCUB_INTERRUPT_ENABLE 0x01c5 817 #define regDMCUB_INTERRUPT_ENABLE_BASE_IDX 2 818 #define regDMCUB_INTERRUPT_ACK 0x01c6 819 #define regDMCUB_INTERRUPT_ACK_BASE_IDX 2 820 #define regDMCUB_INTERRUPT_STATUS 0x01c7 821 #define regDMCUB_INTERRUPT_STATUS_BASE_IDX 2 822 #define regDMCUB_INTERRUPT_TYPE 0x01c8 823 #define regDMCUB_INTERRUPT_TYPE_BASE_IDX 2 824 #define regDMCUB_EXT_INTERRUPT_STATUS 0x01c9 825 #define regDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX 2 826 #define regDMCUB_EXT_INTERRUPT_CTXID 0x01ca 827 #define regDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX 2 828 #define regDMCUB_EXT_INTERRUPT_ACK 0x01cb 829 #define regDMCUB_EXT_INTERRUPT_ACK_BASE_IDX 2 830 #define regDMCUB_INST_FETCH_FAULT_ADDR 0x01cc 831 #define regDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX 2 832 #define regDMCUB_DATA_WRITE_FAULT_ADDR 0x01cd 833 #define regDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX 2 834 #define regDMCUB_SEC_CNTL 0x01ce 835 #define regDMCUB_SEC_CNTL_BASE_IDX 2 836 #define regDMCUB_MEM_CNTL 0x01cf 837 #define regDMCUB_MEM_CNTL_BASE_IDX 2 838 #define regDMCUB_INBOX0_BASE_ADDRESS 0x01d0 839 #define regDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX 2 840 #define regDMCUB_INBOX0_SIZE 0x01d1 841 #define regDMCUB_INBOX0_SIZE_BASE_IDX 2 842 #define regDMCUB_INBOX0_WPTR 0x01d2 843 #define regDMCUB_INBOX0_WPTR_BASE_IDX 2 844 #define regDMCUB_INBOX0_RPTR 0x01d3 845 #define regDMCUB_INBOX0_RPTR_BASE_IDX 2 846 #define regDMCUB_INBOX1_BASE_ADDRESS 0x01d4 847 #define regDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX 2 848 #define regDMCUB_INBOX1_SIZE 0x01d5 849 #define regDMCUB_INBOX1_SIZE_BASE_IDX 2 850 #define regDMCUB_INBOX1_WPTR 0x01d6 851 #define regDMCUB_INBOX1_WPTR_BASE_IDX 2 852 #define regDMCUB_INBOX1_RPTR 0x01d7 853 #define regDMCUB_INBOX1_RPTR_BASE_IDX 2 854 #define regDMCUB_OUTBOX0_BASE_ADDRESS 0x01d8 855 #define regDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX 2 856 #define regDMCUB_OUTBOX0_SIZE 0x01d9 857 #define regDMCUB_OUTBOX0_SIZE_BASE_IDX 2 858 #define regDMCUB_OUTBOX0_WPTR 0x01da 859 #define regDMCUB_OUTBOX0_WPTR_BASE_IDX 2 860 #define regDMCUB_OUTBOX0_RPTR 0x01db 861 #define regDMCUB_OUTBOX0_RPTR_BASE_IDX 2 862 #define regDMCUB_OUTBOX1_BASE_ADDRESS 0x01dc 863 #define regDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX 2 864 #define regDMCUB_OUTBOX1_SIZE 0x01dd 865 #define regDMCUB_OUTBOX1_SIZE_BASE_IDX 2 866 #define regDMCUB_OUTBOX1_WPTR 0x01de 867 #define regDMCUB_OUTBOX1_WPTR_BASE_IDX 2 868 #define regDMCUB_OUTBOX1_RPTR 0x01df 869 #define regDMCUB_OUTBOX1_RPTR_BASE_IDX 2 870 #define regDMCUB_TIMER_TRIGGER0 0x01e0 871 #define regDMCUB_TIMER_TRIGGER0_BASE_IDX 2 872 #define regDMCUB_TIMER_TRIGGER1 0x01e1 873 #define regDMCUB_TIMER_TRIGGER1_BASE_IDX 2 874 #define regDMCUB_TIMER_WINDOW 0x01e2 875 #define regDMCUB_TIMER_WINDOW_BASE_IDX 2 876 #define regDMCUB_SCRATCH0 0x01e3 877 #define regDMCUB_SCRATCH0_BASE_IDX 2 878 #define regDMCUB_SCRATCH1 0x01e4 879 #define regDMCUB_SCRATCH1_BASE_IDX 2 880 #define regDMCUB_SCRATCH2 0x01e5 881 #define regDMCUB_SCRATCH2_BASE_IDX 2 882 #define regDMCUB_SCRATCH3 0x01e6 883 #define regDMCUB_SCRATCH3_BASE_IDX 2 884 #define regDMCUB_SCRATCH4 0x01e7 885 #define regDMCUB_SCRATCH4_BASE_IDX 2 886 #define regDMCUB_SCRATCH5 0x01e8 887 #define regDMCUB_SCRATCH5_BASE_IDX 2 888 #define regDMCUB_SCRATCH6 0x01e9 889 #define regDMCUB_SCRATCH6_BASE_IDX 2 890 #define regDMCUB_SCRATCH7 0x01ea 891 #define regDMCUB_SCRATCH7_BASE_IDX 2 892 #define regDMCUB_SCRATCH8 0x01eb 893 #define regDMCUB_SCRATCH8_BASE_IDX 2 894 #define regDMCUB_SCRATCH9 0x01ec 895 #define regDMCUB_SCRATCH9_BASE_IDX 2 896 #define regDMCUB_SCRATCH10 0x01ed 897 #define regDMCUB_SCRATCH10_BASE_IDX 2 898 #define regDMCUB_SCRATCH11 0x01ee 899 #define regDMCUB_SCRATCH11_BASE_IDX 2 900 #define regDMCUB_SCRATCH12 0x01ef 901 #define regDMCUB_SCRATCH12_BASE_IDX 2 902 #define regDMCUB_SCRATCH13 0x01f0 903 #define regDMCUB_SCRATCH13_BASE_IDX 2 904 #define regDMCUB_SCRATCH14 0x01f1 905 #define regDMCUB_SCRATCH14_BASE_IDX 2 906 #define regDMCUB_SCRATCH15 0x01f2 907 #define regDMCUB_SCRATCH15_BASE_IDX 2 908 #define regDMCUB_SCRATCH16 0x01f3 909 #define regDMCUB_SCRATCH16_BASE_IDX 2 910 #define regDMCUB_SCRATCH17 0x01f4 911 #define regDMCUB_SCRATCH17_BASE_IDX 2 912 #define regDMCUB_SCRATCH18 0x01f5 913 #define regDMCUB_SCRATCH18_BASE_IDX 2 914 #define regDMCUB_CNTL 0x01f6 915 #define regDMCUB_CNTL_BASE_IDX 2 916 #define regDMCUB_GPINT_DATAIN0 0x01f7 917 #define regDMCUB_GPINT_DATAIN0_BASE_IDX 2 918 #define regDMCUB_GPINT_DATAIN1 0x01f8 919 #define regDMCUB_GPINT_DATAIN1_BASE_IDX 2 920 #define regDMCUB_GPINT_DATAOUT 0x01f9 921 #define regDMCUB_GPINT_DATAOUT_BASE_IDX 2 922 #define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR 0x01fa 923 #define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX 2 924 #define regDMCUB_LS_WAKE_INT_ENABLE 0x01fb 925 #define regDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX 2 926 #define regDMCUB_MEM_PWR_CNTL 0x01fc 927 #define regDMCUB_MEM_PWR_CNTL_BASE_IDX 2 928 #define regDMCUB_TIMER_CURRENT 0x01fd 929 #define regDMCUB_TIMER_CURRENT_BASE_IDX 2 930 #define regDMCUB_PROC_ID 0x01ff 931 #define regDMCUB_PROC_ID_BASE_IDX 2 932 #define regDMCUB_CNTL2 0x0200 933 #define regDMCUB_CNTL2_BASE_IDX 2 934 #define regDMCUB_GPINT_DATAIN2 0x0215 935 #define regDMCUB_GPINT_DATAIN2_BASE_IDX 2 936 #define regDMCUB_GPINT_DATAIN3 0x0216 937 #define regDMCUB_GPINT_DATAIN3_BASE_IDX 2 938 #define regDMCUB_GPINT_DATAIN4 0x0217 939 #define regDMCUB_GPINT_DATAIN4_BASE_IDX 2 940 #define regDMCUB_GPINT_DATAIN5 0x0218 941 #define regDMCUB_GPINT_DATAIN5_BASE_IDX 2 942 #define regDMCUB_GPINT_DATAIN6 0x0219 943 #define regDMCUB_GPINT_DATAIN6_BASE_IDX 2 944 #define regDMCUB_REGION3_TMR_AXI_SPACE 0x021a 945 #define regDMCUB_REGION3_TMR_AXI_SPACE_BASE_IDX 2 946 #define regDMCUB_SCRATCH19 0x022e 947 #define regDMCUB_SCRATCH19_BASE_IDX 2 948 #define regDMCUB_SCRATCH20 0x022f 949 #define regDMCUB_SCRATCH20_BASE_IDX 2 950 #define regDMCUB_SCRATCH21 0x0230 951 #define regDMCUB_SCRATCH21_BASE_IDX 2 952 #define regDMCUB_SCRATCH22 0x0231 953 #define regDMCUB_SCRATCH22_BASE_IDX 2 954 #define regDMCUB_SCRATCH23 0x0232 955 #define regDMCUB_SCRATCH23_BASE_IDX 2 956 957 958 // addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec 959 // base address: 0x0 960 #define regDWB_ENABLE_CLK_CTRL 0x3228 961 #define regDWB_ENABLE_CLK_CTRL_BASE_IDX 2 962 #define regDWB_MEM_PWR_CTRL 0x3229 963 #define regDWB_MEM_PWR_CTRL_BASE_IDX 2 964 #define regFC_MODE_CTRL 0x322a 965 #define regFC_MODE_CTRL_BASE_IDX 2 966 #define regFC_FLOW_CTRL 0x322b 967 #define regFC_FLOW_CTRL_BASE_IDX 2 968 #define regFC_WINDOW_START 0x322c 969 #define regFC_WINDOW_START_BASE_IDX 2 970 #define regFC_WINDOW_SIZE 0x322d 971 #define regFC_WINDOW_SIZE_BASE_IDX 2 972 #define regFC_SOURCE_SIZE 0x322e 973 #define regFC_SOURCE_SIZE_BASE_IDX 2 974 #define regDWB_UPDATE_CTRL 0x322f 975 #define regDWB_UPDATE_CTRL_BASE_IDX 2 976 #define regDWB_CRC_CTRL 0x3230 977 #define regDWB_CRC_CTRL_BASE_IDX 2 978 #define regDWB_CRC_MASK_R_G 0x3231 979 #define regDWB_CRC_MASK_R_G_BASE_IDX 2 980 #define regDWB_CRC_MASK_B_A 0x3232 981 #define regDWB_CRC_MASK_B_A_BASE_IDX 2 982 #define regDWB_CRC_VAL_R_G 0x3233 983 #define regDWB_CRC_VAL_R_G_BASE_IDX 2 984 #define regDWB_CRC_VAL_B_A 0x3234 985 #define regDWB_CRC_VAL_B_A_BASE_IDX 2 986 #define regDWB_OUT_CTRL 0x3235 987 #define regDWB_OUT_CTRL_BASE_IDX 2 988 #define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN 0x3236 989 #define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX 2 990 #define regDWB_MMHUBBUB_BACKPRESSURE_CNT 0x3237 991 #define regDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX 2 992 #define regDWB_HOST_READ_CONTROL 0x3238 993 #define regDWB_HOST_READ_CONTROL_BASE_IDX 2 994 #define regDWB_OVERFLOW_STATUS 0x3239 995 #define regDWB_OVERFLOW_STATUS_BASE_IDX 2 996 #define regDWB_OVERFLOW_COUNTER 0x323a 997 #define regDWB_OVERFLOW_COUNTER_BASE_IDX 2 998 #define regDWB_SOFT_RESET 0x323b 999 #define regDWB_SOFT_RESET_BASE_IDX 2 1000 1001 1002 // addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec 1003 // base address: 0x0 1004 #define regDWB_HDR_MULT_COEF 0x3294 1005 #define regDWB_HDR_MULT_COEF_BASE_IDX 2 1006 #define regDWB_GAMUT_REMAP_MODE 0x3295 1007 #define regDWB_GAMUT_REMAP_MODE_BASE_IDX 2 1008 #define regDWB_GAMUT_REMAP_COEF_FORMAT 0x3296 1009 #define regDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 2 1010 #define regDWB_GAMUT_REMAPA_C11_C12 0x3297 1011 #define regDWB_GAMUT_REMAPA_C11_C12_BASE_IDX 2 1012 #define regDWB_GAMUT_REMAPA_C13_C14 0x3298 1013 #define regDWB_GAMUT_REMAPA_C13_C14_BASE_IDX 2 1014 #define regDWB_GAMUT_REMAPA_C21_C22 0x3299 1015 #define regDWB_GAMUT_REMAPA_C21_C22_BASE_IDX 2 1016 #define regDWB_GAMUT_REMAPA_C23_C24 0x329a 1017 #define regDWB_GAMUT_REMAPA_C23_C24_BASE_IDX 2 1018 #define regDWB_GAMUT_REMAPA_C31_C32 0x329b 1019 #define regDWB_GAMUT_REMAPA_C31_C32_BASE_IDX 2 1020 #define regDWB_GAMUT_REMAPA_C33_C34 0x329c 1021 #define regDWB_GAMUT_REMAPA_C33_C34_BASE_IDX 2 1022 #define regDWB_GAMUT_REMAPB_C11_C12 0x329d 1023 #define regDWB_GAMUT_REMAPB_C11_C12_BASE_IDX 2 1024 #define regDWB_GAMUT_REMAPB_C13_C14 0x329e 1025 #define regDWB_GAMUT_REMAPB_C13_C14_BASE_IDX 2 1026 #define regDWB_GAMUT_REMAPB_C21_C22 0x329f 1027 #define regDWB_GAMUT_REMAPB_C21_C22_BASE_IDX 2 1028 #define regDWB_GAMUT_REMAPB_C23_C24 0x32a0 1029 #define regDWB_GAMUT_REMAPB_C23_C24_BASE_IDX 2 1030 #define regDWB_GAMUT_REMAPB_C31_C32 0x32a1 1031 #define regDWB_GAMUT_REMAPB_C31_C32_BASE_IDX 2 1032 #define regDWB_GAMUT_REMAPB_C33_C34 0x32a2 1033 #define regDWB_GAMUT_REMAPB_C33_C34_BASE_IDX 2 1034 #define regDWB_OGAM_CONTROL 0x32a3 1035 #define regDWB_OGAM_CONTROL_BASE_IDX 2 1036 #define regDWB_OGAM_LUT_INDEX 0x32a4 1037 #define regDWB_OGAM_LUT_INDEX_BASE_IDX 2 1038 #define regDWB_OGAM_LUT_DATA 0x32a5 1039 #define regDWB_OGAM_LUT_DATA_BASE_IDX 2 1040 #define regDWB_OGAM_LUT_CONTROL 0x32a6 1041 #define regDWB_OGAM_LUT_CONTROL_BASE_IDX 2 1042 #define regDWB_OGAM_RAMA_START_CNTL_B 0x32a7 1043 #define regDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 1044 #define regDWB_OGAM_RAMA_START_CNTL_G 0x32a8 1045 #define regDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 1046 #define regDWB_OGAM_RAMA_START_CNTL_R 0x32a9 1047 #define regDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 1048 #define regDWB_OGAM_RAMA_START_BASE_CNTL_B 0x32aa 1049 #define regDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 1050 #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B 0x32ab 1051 #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 1052 #define regDWB_OGAM_RAMA_START_BASE_CNTL_G 0x32ac 1053 #define regDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 1054 #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G 0x32ad 1055 #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 1056 #define regDWB_OGAM_RAMA_START_BASE_CNTL_R 0x32ae 1057 #define regDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 1058 #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R 0x32af 1059 #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 1060 #define regDWB_OGAM_RAMA_END_CNTL1_B 0x32b0 1061 #define regDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 1062 #define regDWB_OGAM_RAMA_END_CNTL2_B 0x32b1 1063 #define regDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 1064 #define regDWB_OGAM_RAMA_END_CNTL1_G 0x32b2 1065 #define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 1066 #define regDWB_OGAM_RAMA_END_CNTL2_G 0x32b3 1067 #define regDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 1068 #define regDWB_OGAM_RAMA_END_CNTL1_R 0x32b4 1069 #define regDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 1070 #define regDWB_OGAM_RAMA_END_CNTL2_R 0x32b5 1071 #define regDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 1072 #define regDWB_OGAM_RAMA_OFFSET_B 0x32b6 1073 #define regDWB_OGAM_RAMA_OFFSET_B_BASE_IDX 2 1074 #define regDWB_OGAM_RAMA_OFFSET_G 0x32b7 1075 #define regDWB_OGAM_RAMA_OFFSET_G_BASE_IDX 2 1076 #define regDWB_OGAM_RAMA_OFFSET_R 0x32b8 1077 #define regDWB_OGAM_RAMA_OFFSET_R_BASE_IDX 2 1078 #define regDWB_OGAM_RAMA_REGION_0_1 0x32b9 1079 #define regDWB_OGAM_RAMA_REGION_0_1_BASE_IDX 2 1080 #define regDWB_OGAM_RAMA_REGION_2_3 0x32ba 1081 #define regDWB_OGAM_RAMA_REGION_2_3_BASE_IDX 2 1082 #define regDWB_OGAM_RAMA_REGION_4_5 0x32bb 1083 #define regDWB_OGAM_RAMA_REGION_4_5_BASE_IDX 2 1084 #define regDWB_OGAM_RAMA_REGION_6_7 0x32bc 1085 #define regDWB_OGAM_RAMA_REGION_6_7_BASE_IDX 2 1086 #define regDWB_OGAM_RAMA_REGION_8_9 0x32bd 1087 #define regDWB_OGAM_RAMA_REGION_8_9_BASE_IDX 2 1088 #define regDWB_OGAM_RAMA_REGION_10_11 0x32be 1089 #define regDWB_OGAM_RAMA_REGION_10_11_BASE_IDX 2 1090 #define regDWB_OGAM_RAMA_REGION_12_13 0x32bf 1091 #define regDWB_OGAM_RAMA_REGION_12_13_BASE_IDX 2 1092 #define regDWB_OGAM_RAMA_REGION_14_15 0x32c0 1093 #define regDWB_OGAM_RAMA_REGION_14_15_BASE_IDX 2 1094 #define regDWB_OGAM_RAMA_REGION_16_17 0x32c1 1095 #define regDWB_OGAM_RAMA_REGION_16_17_BASE_IDX 2 1096 #define regDWB_OGAM_RAMA_REGION_18_19 0x32c2 1097 #define regDWB_OGAM_RAMA_REGION_18_19_BASE_IDX 2 1098 #define regDWB_OGAM_RAMA_REGION_20_21 0x32c3 1099 #define regDWB_OGAM_RAMA_REGION_20_21_BASE_IDX 2 1100 #define regDWB_OGAM_RAMA_REGION_22_23 0x32c4 1101 #define regDWB_OGAM_RAMA_REGION_22_23_BASE_IDX 2 1102 #define regDWB_OGAM_RAMA_REGION_24_25 0x32c5 1103 #define regDWB_OGAM_RAMA_REGION_24_25_BASE_IDX 2 1104 #define regDWB_OGAM_RAMA_REGION_26_27 0x32c6 1105 #define regDWB_OGAM_RAMA_REGION_26_27_BASE_IDX 2 1106 #define regDWB_OGAM_RAMA_REGION_28_29 0x32c7 1107 #define regDWB_OGAM_RAMA_REGION_28_29_BASE_IDX 2 1108 #define regDWB_OGAM_RAMA_REGION_30_31 0x32c8 1109 #define regDWB_OGAM_RAMA_REGION_30_31_BASE_IDX 2 1110 #define regDWB_OGAM_RAMA_REGION_32_33 0x32c9 1111 #define regDWB_OGAM_RAMA_REGION_32_33_BASE_IDX 2 1112 #define regDWB_OGAM_RAMB_START_CNTL_B 0x32ca 1113 #define regDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 1114 #define regDWB_OGAM_RAMB_START_CNTL_G 0x32cb 1115 #define regDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 1116 #define regDWB_OGAM_RAMB_START_CNTL_R 0x32cc 1117 #define regDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 1118 #define regDWB_OGAM_RAMB_START_BASE_CNTL_B 0x32cd 1119 #define regDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 1120 #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B 0x32ce 1121 #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 1122 #define regDWB_OGAM_RAMB_START_BASE_CNTL_G 0x32cf 1123 #define regDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 1124 #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G 0x32d0 1125 #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 1126 #define regDWB_OGAM_RAMB_START_BASE_CNTL_R 0x32d1 1127 #define regDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 1128 #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R 0x32d2 1129 #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 1130 #define regDWB_OGAM_RAMB_END_CNTL1_B 0x32d3 1131 #define regDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 1132 #define regDWB_OGAM_RAMB_END_CNTL2_B 0x32d4 1133 #define regDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 1134 #define regDWB_OGAM_RAMB_END_CNTL1_G 0x32d5 1135 #define regDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 1136 #define regDWB_OGAM_RAMB_END_CNTL2_G 0x32d6 1137 #define regDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 1138 #define regDWB_OGAM_RAMB_END_CNTL1_R 0x32d7 1139 #define regDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 1140 #define regDWB_OGAM_RAMB_END_CNTL2_R 0x32d8 1141 #define regDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 1142 #define regDWB_OGAM_RAMB_OFFSET_B 0x32d9 1143 #define regDWB_OGAM_RAMB_OFFSET_B_BASE_IDX 2 1144 #define regDWB_OGAM_RAMB_OFFSET_G 0x32da 1145 #define regDWB_OGAM_RAMB_OFFSET_G_BASE_IDX 2 1146 #define regDWB_OGAM_RAMB_OFFSET_R 0x32db 1147 #define regDWB_OGAM_RAMB_OFFSET_R_BASE_IDX 2 1148 #define regDWB_OGAM_RAMB_REGION_0_1 0x32dc 1149 #define regDWB_OGAM_RAMB_REGION_0_1_BASE_IDX 2 1150 #define regDWB_OGAM_RAMB_REGION_2_3 0x32dd 1151 #define regDWB_OGAM_RAMB_REGION_2_3_BASE_IDX 2 1152 #define regDWB_OGAM_RAMB_REGION_4_5 0x32de 1153 #define regDWB_OGAM_RAMB_REGION_4_5_BASE_IDX 2 1154 #define regDWB_OGAM_RAMB_REGION_6_7 0x32df 1155 #define regDWB_OGAM_RAMB_REGION_6_7_BASE_IDX 2 1156 #define regDWB_OGAM_RAMB_REGION_8_9 0x32e0 1157 #define regDWB_OGAM_RAMB_REGION_8_9_BASE_IDX 2 1158 #define regDWB_OGAM_RAMB_REGION_10_11 0x32e1 1159 #define regDWB_OGAM_RAMB_REGION_10_11_BASE_IDX 2 1160 #define regDWB_OGAM_RAMB_REGION_12_13 0x32e2 1161 #define regDWB_OGAM_RAMB_REGION_12_13_BASE_IDX 2 1162 #define regDWB_OGAM_RAMB_REGION_14_15 0x32e3 1163 #define regDWB_OGAM_RAMB_REGION_14_15_BASE_IDX 2 1164 #define regDWB_OGAM_RAMB_REGION_16_17 0x32e4 1165 #define regDWB_OGAM_RAMB_REGION_16_17_BASE_IDX 2 1166 #define regDWB_OGAM_RAMB_REGION_18_19 0x32e5 1167 #define regDWB_OGAM_RAMB_REGION_18_19_BASE_IDX 2 1168 #define regDWB_OGAM_RAMB_REGION_20_21 0x32e6 1169 #define regDWB_OGAM_RAMB_REGION_20_21_BASE_IDX 2 1170 #define regDWB_OGAM_RAMB_REGION_22_23 0x32e7 1171 #define regDWB_OGAM_RAMB_REGION_22_23_BASE_IDX 2 1172 #define regDWB_OGAM_RAMB_REGION_24_25 0x32e8 1173 #define regDWB_OGAM_RAMB_REGION_24_25_BASE_IDX 2 1174 #define regDWB_OGAM_RAMB_REGION_26_27 0x32e9 1175 #define regDWB_OGAM_RAMB_REGION_26_27_BASE_IDX 2 1176 #define regDWB_OGAM_RAMB_REGION_28_29 0x32ea 1177 #define regDWB_OGAM_RAMB_REGION_28_29_BASE_IDX 2 1178 #define regDWB_OGAM_RAMB_REGION_30_31 0x32eb 1179 #define regDWB_OGAM_RAMB_REGION_30_31_BASE_IDX 2 1180 #define regDWB_OGAM_RAMB_REGION_32_33 0x32ec 1181 #define regDWB_OGAM_RAMB_REGION_32_33_BASE_IDX 2 1182 1183 1184 // addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec 1185 // base address: 0xca20 1186 #define regDC_PERFMON3_PERFCOUNTER_CNTL 0x3288 1187 #define regDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2 1188 #define regDC_PERFMON3_PERFCOUNTER_CNTL2 0x3289 1189 #define regDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2 1190 #define regDC_PERFMON3_PERFCOUNTER_STATE 0x328a 1191 #define regDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2 1192 #define regDC_PERFMON3_PERFMON_CNTL 0x328b 1193 #define regDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2 1194 #define regDC_PERFMON3_PERFMON_CNTL2 0x328c 1195 #define regDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2 1196 #define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x328d 1197 #define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1198 #define regDC_PERFMON3_PERFMON_CVALUE_LOW 0x328e 1199 #define regDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2 1200 #define regDC_PERFMON3_PERFMON_HI 0x328f 1201 #define regDC_PERFMON3_PERFMON_HI_BASE_IDX 2 1202 #define regDC_PERFMON3_PERFMON_LOW 0x3290 1203 #define regDC_PERFMON3_PERFMON_LOW_BASE_IDX 2 1204 1205 1206 // addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec 1207 // base address: 0x0 1208 #define regMCIF_WB_BUFMGR_SW_CONTROL 0x0272 1209 #define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 1210 #define regMCIF_WB_BUFMGR_STATUS 0x0274 1211 #define regMCIF_WB_BUFMGR_STATUS_BASE_IDX 2 1212 #define regMCIF_WB_BUF_PITCH 0x0275 1213 #define regMCIF_WB_BUF_PITCH_BASE_IDX 2 1214 #define regMCIF_WB_BUF_1_STATUS 0x0276 1215 #define regMCIF_WB_BUF_1_STATUS_BASE_IDX 2 1216 #define regMCIF_WB_BUF_1_STATUS2 0x0277 1217 #define regMCIF_WB_BUF_1_STATUS2_BASE_IDX 2 1218 #define regMCIF_WB_BUF_2_STATUS 0x0278 1219 #define regMCIF_WB_BUF_2_STATUS_BASE_IDX 2 1220 #define regMCIF_WB_BUF_2_STATUS2 0x0279 1221 #define regMCIF_WB_BUF_2_STATUS2_BASE_IDX 2 1222 #define regMCIF_WB_BUF_3_STATUS 0x027a 1223 #define regMCIF_WB_BUF_3_STATUS_BASE_IDX 2 1224 #define regMCIF_WB_BUF_3_STATUS2 0x027b 1225 #define regMCIF_WB_BUF_3_STATUS2_BASE_IDX 2 1226 #define regMCIF_WB_BUF_4_STATUS 0x027c 1227 #define regMCIF_WB_BUF_4_STATUS_BASE_IDX 2 1228 #define regMCIF_WB_BUF_4_STATUS2 0x027d 1229 #define regMCIF_WB_BUF_4_STATUS2_BASE_IDX 2 1230 #define regMCIF_WB_ARBITRATION_CONTROL 0x027e 1231 #define regMCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 1232 #define regMCIF_WB_SCLK_CHANGE 0x027f 1233 #define regMCIF_WB_SCLK_CHANGE_BASE_IDX 2 1234 #define regMCIF_WB_BUF_1_ADDR_Y 0x0282 1235 #define regMCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 1236 #define regMCIF_WB_BUF_1_ADDR_C 0x0284 1237 #define regMCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 1238 #define regMCIF_WB_BUF_2_ADDR_Y 0x0286 1239 #define regMCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 1240 #define regMCIF_WB_BUF_2_ADDR_C 0x0288 1241 #define regMCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 1242 #define regMCIF_WB_BUF_3_ADDR_Y 0x028a 1243 #define regMCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 1244 #define regMCIF_WB_BUF_3_ADDR_C 0x028c 1245 #define regMCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 1246 #define regMCIF_WB_BUF_4_ADDR_Y 0x028e 1247 #define regMCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 1248 #define regMCIF_WB_BUF_4_ADDR_C 0x0290 1249 #define regMCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 1250 #define regMCIF_WB_BUFMGR_VCE_CONTROL 0x0292 1251 #define regMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 1252 #define regMCIF_WB_NB_PSTATE_CONTROL 0x0293 1253 #define regMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 1254 #define regMCIF_WB_CLOCK_GATER_CONTROL 0x0294 1255 #define regMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 1256 #define regMCIF_WB_SELF_REFRESH_CONTROL 0x0296 1257 #define regMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 1258 #define regMULTI_LEVEL_QOS_CTRL 0x0297 1259 #define regMULTI_LEVEL_QOS_CTRL_BASE_IDX 2 1260 #define regMCIF_WB_SECURITY_LEVEL 0x0298 1261 #define regMCIF_WB_SECURITY_LEVEL_BASE_IDX 2 1262 #define regMCIF_WB_BUF_LUMA_SIZE 0x0299 1263 #define regMCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 1264 #define regMCIF_WB_BUF_CHROMA_SIZE 0x029a 1265 #define regMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 1266 #define regMCIF_WB_BUF_1_ADDR_Y_HIGH 0x029b 1267 #define regMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2 1268 #define regMCIF_WB_BUF_1_ADDR_C_HIGH 0x029c 1269 #define regMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2 1270 #define regMCIF_WB_BUF_2_ADDR_Y_HIGH 0x029d 1271 #define regMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2 1272 #define regMCIF_WB_BUF_2_ADDR_C_HIGH 0x029e 1273 #define regMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2 1274 #define regMCIF_WB_BUF_3_ADDR_Y_HIGH 0x029f 1275 #define regMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2 1276 #define regMCIF_WB_BUF_3_ADDR_C_HIGH 0x02a0 1277 #define regMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2 1278 #define regMCIF_WB_BUF_4_ADDR_Y_HIGH 0x02a1 1279 #define regMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2 1280 #define regMCIF_WB_BUF_4_ADDR_C_HIGH 0x02a2 1281 #define regMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2 1282 #define regMCIF_WB_BUF_1_RESOLUTION 0x02a3 1283 #define regMCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2 1284 #define regMCIF_WB_BUF_2_RESOLUTION 0x02a4 1285 #define regMCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2 1286 #define regMCIF_WB_BUF_3_RESOLUTION 0x02a5 1287 #define regMCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2 1288 #define regMCIF_WB_BUF_4_RESOLUTION 0x02a6 1289 #define regMCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2 1290 #define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI 0x02a7 1291 #define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI_BASE_IDX 2 1292 #define regMCIF_WB_VMID_CONTROL 0x02a8 1293 #define regMCIF_WB_VMID_CONTROL_BASE_IDX 2 1294 #define regMCIF_WB_MIN_TTO 0x02a9 1295 #define regMCIF_WB_MIN_TTO_BASE_IDX 2 1296 1297 1298 // addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec 1299 // base address: 0xd48 1300 #define regDC_PERFMON4_PERFCOUNTER_CNTL 0x0352 1301 #define regDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2 1302 #define regDC_PERFMON4_PERFCOUNTER_CNTL2 0x0353 1303 #define regDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2 1304 #define regDC_PERFMON4_PERFCOUNTER_STATE 0x0354 1305 #define regDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2 1306 #define regDC_PERFMON4_PERFMON_CNTL 0x0355 1307 #define regDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2 1308 #define regDC_PERFMON4_PERFMON_CNTL2 0x0356 1309 #define regDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2 1310 #define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x0357 1311 #define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1312 #define regDC_PERFMON4_PERFMON_CVALUE_LOW 0x0358 1313 #define regDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2 1314 #define regDC_PERFMON4_PERFMON_HI 0x0359 1315 #define regDC_PERFMON4_PERFMON_HI_BASE_IDX 2 1316 #define regDC_PERFMON4_PERFMON_LOW 0x035a 1317 #define regDC_PERFMON4_PERFMON_LOW_BASE_IDX 2 1318 1319 1320 // addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec 1321 // base address: 0x0 1322 #define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02aa 1323 #define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 1324 #define regMCIF_WB_WATERMARK 0x02ab 1325 #define regMCIF_WB_WATERMARK_BASE_IDX 2 1326 #define regMMHUBBUB_WARMUP_CONFIG 0x02ac 1327 #define regMMHUBBUB_WARMUP_CONFIG_BASE_IDX 2 1328 #define regMMHUBBUB_WARMUP_CONTROL_STATUS 0x02ad 1329 #define regMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX 2 1330 #define regMMHUBBUB_WARMUP_BASE_ADDR_LOW 0x02ae 1331 #define regMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX 2 1332 #define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH 0x02af 1333 #define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX 2 1334 #define regMMHUBBUB_WARMUP_ADDR_REGION 0x02b0 1335 #define regMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX 2 1336 #define regMMHUBBUB_MIN_TTO 0x02b1 1337 #define regMMHUBBUB_MIN_TTO_BASE_IDX 2 1338 #define regMMHUBBUB_CTRL 0x0333 1339 #define regMMHUBBUB_CTRL_BASE_IDX 2 1340 #define regWBIF_SMU_WM_CONTROL 0x0334 1341 #define regWBIF_SMU_WM_CONTROL_BASE_IDX 2 1342 #define regWBIF0_MISC_CTRL 0x0335 1343 #define regWBIF0_MISC_CTRL_BASE_IDX 2 1344 #define regWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0336 1345 #define regWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 1346 #define regWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0337 1347 #define regWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 1348 #define regMMHUBBUB_MEM_PWR_STATUS 0x033e 1349 #define regMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 1350 #define regMMHUBBUB_MEM_PWR_CNTL 0x033f 1351 #define regMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2 1352 #define regMMHUBBUB_CLOCK_CNTL 0x0340 1353 #define regMMHUBBUB_CLOCK_CNTL_BASE_IDX 2 1354 #define regMMHUBBUB_SOFT_RESET 0x0341 1355 #define regMMHUBBUB_SOFT_RESET_BASE_IDX 2 1356 #define regDMU_IF_ERR_STATUS 0x0345 1357 #define regDMU_IF_ERR_STATUS_BASE_IDX 2 1358 #define regMMHUBBUB_CLIENT_UNIT_ID 0x0346 1359 #define regMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX 2 1360 #define regMMHUBBUB_WARMUP_VMID_CONTROL 0x0348 1361 #define regMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX 2 1362 1363 1364 // addressBlock: dce_dc_hda_azf0controller_dispdec 1365 // base address: 0x0 1366 #define regAZALIA_CONTROLLER_CLOCK_GATING 0x03c2 1367 #define regAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2 1368 #define regAZALIA_AUDIO_DTO 0x03c3 1369 #define regAZALIA_AUDIO_DTO_BASE_IDX 2 1370 #define regAZALIA_AUDIO_DTO_CONTROL 0x03c4 1371 #define regAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2 1372 #define regAZALIA_SOCCLK_CONTROL 0x03c5 1373 #define regAZALIA_SOCCLK_CONTROL_BASE_IDX 2 1374 #define regAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6 1375 #define regAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2 1376 #define regAZALIA_DATA_DMA_CONTROL 0x03c7 1377 #define regAZALIA_DATA_DMA_CONTROL_BASE_IDX 2 1378 #define regAZALIA_BDL_DMA_CONTROL 0x03c8 1379 #define regAZALIA_BDL_DMA_CONTROL_BASE_IDX 2 1380 #define regAZALIA_RIRB_AND_DP_CONTROL 0x03c9 1381 #define regAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2 1382 #define regAZALIA_CORB_DMA_CONTROL 0x03ca 1383 #define regAZALIA_CORB_DMA_CONTROL_BASE_IDX 2 1384 #define regAZALIA_GLOBAL_CAPABILITIES 0x03d3 1385 #define regAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2 1386 #define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4 1387 #define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 1388 #define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5 1389 #define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2 1390 #define regAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6 1391 #define regAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 1392 #define regAZALIA_INPUT_CRC0_CONTROL0 0x03d9 1393 #define regAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2 1394 #define regAZALIA_INPUT_CRC0_CONTROL1 0x03da 1395 #define regAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2 1396 #define regAZALIA_INPUT_CRC0_CONTROL2 0x03db 1397 #define regAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2 1398 #define regAZALIA_INPUT_CRC0_CONTROL3 0x03dc 1399 #define regAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2 1400 #define regAZALIA_INPUT_CRC0_RESULT 0x03dd 1401 #define regAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2 1402 #define regAZALIA_INPUT_CRC1_CONTROL0 0x03de 1403 #define regAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2 1404 #define regAZALIA_INPUT_CRC1_CONTROL1 0x03df 1405 #define regAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2 1406 #define regAZALIA_INPUT_CRC1_CONTROL2 0x03e0 1407 #define regAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2 1408 #define regAZALIA_INPUT_CRC1_CONTROL3 0x03e1 1409 #define regAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2 1410 #define regAZALIA_INPUT_CRC1_RESULT 0x03e2 1411 #define regAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2 1412 #define regAZALIA_CRC0_CONTROL0 0x03e3 1413 #define regAZALIA_CRC0_CONTROL0_BASE_IDX 2 1414 #define regAZALIA_CRC0_CONTROL1 0x03e4 1415 #define regAZALIA_CRC0_CONTROL1_BASE_IDX 2 1416 #define regAZALIA_CRC0_CONTROL2 0x03e5 1417 #define regAZALIA_CRC0_CONTROL2_BASE_IDX 2 1418 #define regAZALIA_CRC0_CONTROL3 0x03e6 1419 #define regAZALIA_CRC0_CONTROL3_BASE_IDX 2 1420 #define regAZALIA_CRC0_RESULT 0x03e7 1421 #define regAZALIA_CRC0_RESULT_BASE_IDX 2 1422 #define regAZALIA_CRC1_CONTROL0 0x03e8 1423 #define regAZALIA_CRC1_CONTROL0_BASE_IDX 2 1424 #define regAZALIA_CRC1_CONTROL1 0x03e9 1425 #define regAZALIA_CRC1_CONTROL1_BASE_IDX 2 1426 #define regAZALIA_CRC1_CONTROL2 0x03ea 1427 #define regAZALIA_CRC1_CONTROL2_BASE_IDX 2 1428 #define regAZALIA_CRC1_CONTROL3 0x03eb 1429 #define regAZALIA_CRC1_CONTROL3_BASE_IDX 2 1430 #define regAZALIA_CRC1_RESULT 0x03ec 1431 #define regAZALIA_CRC1_RESULT_BASE_IDX 2 1432 #define regAZALIA_MEM_PWR_CTRL 0x03ee 1433 #define regAZALIA_MEM_PWR_CTRL_BASE_IDX 2 1434 #define regAZALIA_MEM_PWR_STATUS 0x03ef 1435 #define regAZALIA_MEM_PWR_STATUS_BASE_IDX 2 1436 1437 1438 // addressBlock: dce_dc_hda_azf0root_dispdec 1439 // base address: 0x0 1440 #define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406 1441 #define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2 1442 #define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407 1443 #define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2 1444 #define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408 1445 #define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2 1446 #define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409 1447 #define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2 1448 #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a 1449 #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2 1450 #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b 1451 #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2 1452 #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c 1453 #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2 1454 #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d 1455 #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2 1456 #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e 1457 #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2 1458 #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f 1459 #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2 1460 #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410 1461 #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2 1462 #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411 1463 #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2 1464 #define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412 1465 #define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 1466 #define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413 1467 #define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 1468 #define regAZALIA_F0_GTC_GROUP_OFFSET0 0x0415 1469 #define regAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2 1470 #define regAZALIA_F0_GTC_GROUP_OFFSET1 0x0416 1471 #define regAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2 1472 #define regAZALIA_F0_GTC_GROUP_OFFSET2 0x0417 1473 #define regAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2 1474 #define regAZALIA_F0_GTC_GROUP_OFFSET3 0x0418 1475 #define regAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2 1476 #define regAZALIA_F0_GTC_GROUP_OFFSET4 0x0419 1477 #define regAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2 1478 #define regAZALIA_F0_GTC_GROUP_OFFSET5 0x041a 1479 #define regAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2 1480 #define regAZALIA_F0_GTC_GROUP_OFFSET6 0x041b 1481 #define regAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2 1482 #define regREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c 1483 #define regREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 1484 #define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d 1485 #define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 1486 1487 1488 // addressBlock: dce_dc_hda_az_misc_dispdec 1489 // base address: 0x0 1490 #define regAZ_CLOCK_CNTL 0x0372 1491 #define regAZ_CLOCK_CNTL_BASE_IDX 2 1492 #define regAZ_MEM_GLOBAL_PWR_REQ_CNTL 0x0373 1493 #define regAZ_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 2 1494 1495 1496 // addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec 1497 // base address: 0xde8 1498 #define regDC_PERFMON5_PERFCOUNTER_CNTL 0x037a 1499 #define regDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2 1500 #define regDC_PERFMON5_PERFCOUNTER_CNTL2 0x037b 1501 #define regDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2 1502 #define regDC_PERFMON5_PERFCOUNTER_STATE 0x037c 1503 #define regDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2 1504 #define regDC_PERFMON5_PERFMON_CNTL 0x037d 1505 #define regDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2 1506 #define regDC_PERFMON5_PERFMON_CNTL2 0x037e 1507 #define regDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2 1508 #define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x037f 1509 #define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1510 #define regDC_PERFMON5_PERFMON_CVALUE_LOW 0x0380 1511 #define regDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2 1512 #define regDC_PERFMON5_PERFMON_HI 0x0381 1513 #define regDC_PERFMON5_PERFMON_HI_BASE_IDX 2 1514 #define regDC_PERFMON5_PERFMON_LOW 0x0382 1515 #define regDC_PERFMON5_PERFMON_LOW_BASE_IDX 2 1516 1517 1518 // addressBlock: dce_dc_hda_azf0stream0_dispdec 1519 // base address: 0x0 1520 #define regAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e 1521 #define regAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2 1522 #define regAZF0STREAM0_AZALIA_STREAM_DATA 0x035f 1523 #define regAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2 1524 1525 1526 // addressBlock: dce_dc_hda_azf0stream1_dispdec 1527 // base address: 0x8 1528 #define regAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360 1529 #define regAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2 1530 #define regAZF0STREAM1_AZALIA_STREAM_DATA 0x0361 1531 #define regAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2 1532 1533 1534 // addressBlock: dce_dc_hda_azf0stream2_dispdec 1535 // base address: 0x10 1536 #define regAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362 1537 #define regAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2 1538 #define regAZF0STREAM2_AZALIA_STREAM_DATA 0x0363 1539 #define regAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2 1540 1541 1542 // addressBlock: dce_dc_hda_azf0stream3_dispdec 1543 // base address: 0x18 1544 #define regAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364 1545 #define regAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2 1546 #define regAZF0STREAM3_AZALIA_STREAM_DATA 0x0365 1547 #define regAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2 1548 1549 1550 // addressBlock: dce_dc_hda_azf0stream4_dispdec 1551 // base address: 0x20 1552 #define regAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366 1553 #define regAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2 1554 #define regAZF0STREAM4_AZALIA_STREAM_DATA 0x0367 1555 #define regAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2 1556 1557 1558 // addressBlock: dce_dc_hda_azf0stream5_dispdec 1559 // base address: 0x28 1560 #define regAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368 1561 #define regAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2 1562 #define regAZF0STREAM5_AZALIA_STREAM_DATA 0x0369 1563 #define regAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2 1564 1565 1566 // addressBlock: dce_dc_hda_azf0stream6_dispdec 1567 // base address: 0x30 1568 #define regAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a 1569 #define regAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2 1570 #define regAZF0STREAM6_AZALIA_STREAM_DATA 0x036b 1571 #define regAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2 1572 1573 1574 // addressBlock: dce_dc_hda_azf0stream7_dispdec 1575 // base address: 0x38 1576 #define regAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c 1577 #define regAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2 1578 #define regAZF0STREAM7_AZALIA_STREAM_DATA 0x036d 1579 #define regAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2 1580 1581 1582 // addressBlock: dce_dc_hda_azf0stream8_dispdec 1583 // base address: 0x320 1584 #define regAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426 1585 #define regAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2 1586 #define regAZF0STREAM8_AZALIA_STREAM_DATA 0x0427 1587 #define regAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2 1588 1589 1590 // addressBlock: dce_dc_hda_azf0stream9_dispdec 1591 // base address: 0x328 1592 #define regAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428 1593 #define regAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2 1594 #define regAZF0STREAM9_AZALIA_STREAM_DATA 0x0429 1595 #define regAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2 1596 1597 1598 // addressBlock: dce_dc_hda_azf0stream10_dispdec 1599 // base address: 0x330 1600 #define regAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a 1601 #define regAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2 1602 #define regAZF0STREAM10_AZALIA_STREAM_DATA 0x042b 1603 #define regAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2 1604 1605 1606 // addressBlock: dce_dc_hda_azf0stream11_dispdec 1607 // base address: 0x338 1608 #define regAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c 1609 #define regAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2 1610 #define regAZF0STREAM11_AZALIA_STREAM_DATA 0x042d 1611 #define regAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2 1612 1613 1614 // addressBlock: dce_dc_hda_azf0stream12_dispdec 1615 // base address: 0x340 1616 #define regAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e 1617 #define regAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2 1618 #define regAZF0STREAM12_AZALIA_STREAM_DATA 0x042f 1619 #define regAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2 1620 1621 1622 // addressBlock: dce_dc_hda_azf0stream13_dispdec 1623 // base address: 0x348 1624 #define regAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430 1625 #define regAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2 1626 #define regAZF0STREAM13_AZALIA_STREAM_DATA 0x0431 1627 #define regAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2 1628 1629 1630 // addressBlock: dce_dc_hda_azf0stream14_dispdec 1631 // base address: 0x350 1632 #define regAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432 1633 #define regAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2 1634 #define regAZF0STREAM14_AZALIA_STREAM_DATA 0x0433 1635 #define regAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2 1636 1637 1638 // addressBlock: dce_dc_hda_azf0stream15_dispdec 1639 // base address: 0x358 1640 #define regAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434 1641 #define regAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2 1642 #define regAZF0STREAM15_AZALIA_STREAM_DATA 0x0435 1643 #define regAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2 1644 1645 1646 // addressBlock: dce_dc_hda_azf0endpoint0_dispdec 1647 // base address: 0x0 1648 #define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386 1649 #define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1650 #define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387 1651 #define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1652 1653 1654 // addressBlock: dce_dc_hda_azf0endpoint1_dispdec 1655 // base address: 0x18 1656 #define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c 1657 #define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1658 #define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d 1659 #define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1660 1661 1662 // addressBlock: dce_dc_hda_azf0endpoint2_dispdec 1663 // base address: 0x30 1664 #define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392 1665 #define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1666 #define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393 1667 #define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1668 1669 1670 // addressBlock: dce_dc_hda_azf0endpoint3_dispdec 1671 // base address: 0x48 1672 #define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398 1673 #define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1674 #define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399 1675 #define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1676 1677 1678 // addressBlock: dce_dc_hda_azf0endpoint4_dispdec 1679 // base address: 0x60 1680 #define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e 1681 #define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1682 #define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f 1683 #define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1684 1685 1686 // addressBlock: dce_dc_hda_azf0endpoint5_dispdec 1687 // base address: 0x78 1688 #define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4 1689 #define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1690 #define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5 1691 #define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1692 1693 1694 // addressBlock: dce_dc_hda_azf0endpoint6_dispdec 1695 // base address: 0x90 1696 #define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa 1697 #define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1698 #define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab 1699 #define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1700 1701 1702 // addressBlock: dce_dc_hda_azf0endpoint7_dispdec 1703 // base address: 0xa8 1704 #define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0 1705 #define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1706 #define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1 1707 #define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1708 1709 1710 // addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec 1711 // base address: 0x0 1712 #define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a 1713 #define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1714 #define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b 1715 #define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1716 1717 1718 // addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec 1719 // base address: 0x10 1720 #define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e 1721 #define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1722 #define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f 1723 #define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1724 1725 1726 // addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec 1727 // base address: 0x20 1728 #define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442 1729 #define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1730 #define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443 1731 #define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1732 1733 1734 // addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec 1735 // base address: 0x30 1736 #define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446 1737 #define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1738 #define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447 1739 #define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1740 1741 1742 // addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec 1743 // base address: 0x40 1744 #define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a 1745 #define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1746 #define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b 1747 #define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1748 1749 1750 // addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec 1751 // base address: 0x50 1752 #define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e 1753 #define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1754 #define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f 1755 #define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1756 1757 1758 // addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec 1759 // base address: 0x60 1760 #define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452 1761 #define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1762 #define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453 1763 #define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1764 1765 1766 // addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec 1767 // base address: 0x70 1768 #define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456 1769 #define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1770 #define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457 1771 #define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1772 1773 1774 // addressBlock: dce_dc_dchubbubl_hubbub_dispdec 1775 // base address: 0x0 1776 #define regDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x04f9 1777 #define regDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2 1778 #define regDCHUBBUB_ARB_SAT_LEVEL 0x04fa 1779 #define regDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2 1780 #define regDCHUBBUB_ARB_QOS_FORCE 0x04fb 1781 #define regDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2 1782 #define regDCHUBBUB_ARB_DRAM_STATE_CNTL 0x04fc 1783 #define regDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2 1784 #define regDCHUBBUB_ARB_USR_RETRAINING_CNTL 0x04fd 1785 #define regDCHUBBUB_ARB_USR_RETRAINING_CNTL_BASE_IDX 2 1786 #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x04fe 1787 #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2 1788 #define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A 0x04ff 1789 #define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A_BASE_IDX 2 1790 #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A 0x0500 1791 #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX 2 1792 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x0501 1793 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2 1794 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A 0x0502 1795 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A_BASE_IDX 2 1796 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x0503 1797 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2 1798 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A 0x0504 1799 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A_BASE_IDX 2 1800 #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A 0x0505 1801 #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX 2 1802 #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A 0x0506 1803 #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX 2 1804 #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A 0x0507 1805 #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX 2 1806 #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A 0x0508 1807 #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX 2 1808 #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x0509 1809 #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2 1810 #define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B 0x050a 1811 #define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B_BASE_IDX 2 1812 #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B 0x050b 1813 #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX 2 1814 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x050c 1815 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2 1816 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B 0x050d 1817 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B_BASE_IDX 2 1818 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x050e 1819 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2 1820 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B 0x050f 1821 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B_BASE_IDX 2 1822 #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B 0x0510 1823 #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX 2 1824 #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B 0x0511 1825 #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX 2 1826 #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B 0x0512 1827 #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX 2 1828 #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B 0x0513 1829 #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX 2 1830 #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x0514 1831 #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2 1832 #define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C 0x0515 1833 #define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C_BASE_IDX 2 1834 #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C 0x0516 1835 #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX 2 1836 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x0517 1837 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2 1838 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C 0x0518 1839 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C_BASE_IDX 2 1840 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0519 1841 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2 1842 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C 0x051a 1843 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C_BASE_IDX 2 1844 #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C 0x051b 1845 #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX 2 1846 #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C 0x051c 1847 #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX 2 1848 #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C 0x051d 1849 #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX 2 1850 #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C 0x051e 1851 #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX 2 1852 #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x051f 1853 #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2 1854 #define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D 0x0520 1855 #define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D_BASE_IDX 2 1856 #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D 0x0521 1857 #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX 2 1858 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x0522 1859 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2 1860 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D 0x0523 1861 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D_BASE_IDX 2 1862 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x0524 1863 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2 1864 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D 0x0525 1865 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D_BASE_IDX 2 1866 #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D 0x0526 1867 #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX 2 1868 #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D 0x0527 1869 #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX 2 1870 #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D 0x0528 1871 #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX 2 1872 #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D 0x0529 1873 #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX 2 1874 #define regDCHUBBUB_ARB_HOSTVM_CNTL 0x052a 1875 #define regDCHUBBUB_ARB_HOSTVM_CNTL_BASE_IDX 2 1876 #define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x052b 1877 #define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2 1878 #define regDCHUBBUB_ARB_MALL_CNTL 0x052c 1879 #define regDCHUBBUB_ARB_MALL_CNTL_BASE_IDX 2 1880 #define regDCHUBBUB_ARB_TIMEOUT_ENABLE 0x052d 1881 #define regDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2 1882 #define regDCHUBBUB_GLOBAL_TIMER_CNTL 0x052e 1883 #define regDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2 1884 #define regSURFACE_CHECK0_ADDRESS_LSB 0x052f 1885 #define regSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2 1886 #define regSURFACE_CHECK0_ADDRESS_MSB 0x0530 1887 #define regSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2 1888 #define regSURFACE_CHECK1_ADDRESS_LSB 0x0531 1889 #define regSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2 1890 #define regSURFACE_CHECK1_ADDRESS_MSB 0x0532 1891 #define regSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2 1892 #define regSURFACE_CHECK2_ADDRESS_LSB 0x0533 1893 #define regSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2 1894 #define regSURFACE_CHECK2_ADDRESS_MSB 0x0534 1895 #define regSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2 1896 #define regSURFACE_CHECK3_ADDRESS_LSB 0x0535 1897 #define regSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2 1898 #define regSURFACE_CHECK3_ADDRESS_MSB 0x0536 1899 #define regSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2 1900 #define regVTG0_CONTROL 0x0537 1901 #define regVTG0_CONTROL_BASE_IDX 2 1902 #define regVTG1_CONTROL 0x0538 1903 #define regVTG1_CONTROL_BASE_IDX 2 1904 #define regVTG2_CONTROL 0x0539 1905 #define regVTG2_CONTROL_BASE_IDX 2 1906 #define regVTG3_CONTROL 0x053a 1907 #define regVTG3_CONTROL_BASE_IDX 2 1908 #define regDCHUBBUB_SOFT_RESET 0x053b 1909 #define regDCHUBBUB_SOFT_RESET_BASE_IDX 2 1910 #define regDCHUBBUB_CLOCK_CNTL 0x053c 1911 #define regDCHUBBUB_CLOCK_CNTL_BASE_IDX 2 1912 #define regDCFCLK_CNTL 0x053d 1913 #define regDCFCLK_CNTL_BASE_IDX 2 1914 #define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x053e 1915 #define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2 1916 #define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x053f 1917 #define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2 1918 #define regDCHUBBUB_VLINE_SNAPSHOT 0x0540 1919 #define regDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2 1920 #define regDCHUBBUB_CTRL_STATUS 0x0541 1921 #define regDCHUBBUB_CTRL_STATUS_BASE_IDX 2 1922 #define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0x0547 1923 #define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX 2 1924 #define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0x0548 1925 #define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX 2 1926 #define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS 0x0549 1927 #define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX 2 1928 #define regFMON_CTRL 0x054a 1929 #define regFMON_CTRL_BASE_IDX 2 1930 1931 1932 // addressBlock: dce_dc_dchubbubl_hubbub_sdpif_dispdec 1933 // base address: 0x0 1934 #define regDCHUBBUB_SDPIF_CFG0 0x046f 1935 #define regDCHUBBUB_SDPIF_CFG0_BASE_IDX 2 1936 #define regDCHUBBUB_SDPIF_CFG1 0x0470 1937 #define regDCHUBBUB_SDPIF_CFG1_BASE_IDX 2 1938 #define regDCHUBBUB_SDPIF_CFG2 0x0471 1939 #define regDCHUBBUB_SDPIF_CFG2_BASE_IDX 2 1940 #define regVM_REQUEST_PHYSICAL 0x0472 1941 #define regVM_REQUEST_PHYSICAL_BASE_IDX 2 1942 #define regDCHUBBUB_FORCE_IO_STATUS_0 0x0473 1943 #define regDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2 1944 #define regDCHUBBUB_FORCE_IO_STATUS_1 0x0474 1945 #define regDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2 1946 #define regDCN_VM_FB_LOCATION_BASE 0x0475 1947 #define regDCN_VM_FB_LOCATION_BASE_BASE_IDX 2 1948 #define regDCN_VM_FB_LOCATION_TOP 0x0476 1949 #define regDCN_VM_FB_LOCATION_TOP_BASE_IDX 2 1950 #define regDCN_VM_FB_OFFSET 0x0477 1951 #define regDCN_VM_FB_OFFSET_BASE_IDX 2 1952 #define regDCN_VM_AGP_BOT 0x0478 1953 #define regDCN_VM_AGP_BOT_BASE_IDX 2 1954 #define regDCN_VM_AGP_TOP 0x0479 1955 #define regDCN_VM_AGP_TOP_BASE_IDX 2 1956 #define regDCN_VM_AGP_BASE 0x047a 1957 #define regDCN_VM_AGP_BASE_BASE_IDX 2 1958 #define regDCN_VM_LOCAL_HBM_ADDRESS_START 0x047b 1959 #define regDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 2 1960 #define regDCN_VM_LOCAL_HBM_ADDRESS_END 0x047c 1961 #define regDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 2 1962 #define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x047d 1963 #define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 2 1964 #define regDCHUBBUB_SDPIF_PIPE_SEC_LVL 0x047e 1965 #define regDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX 2 1966 #define regDCHUBBUB_SDPIF_PIPE_NOALLOC 0x047f 1967 #define regDCHUBBUB_SDPIF_PIPE_NOALLOC_BASE_IDX 2 1968 #define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL 0x0480 1969 #define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL_BASE_IDX 2 1970 #define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL 0x0481 1971 #define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL_BASE_IDX 2 1972 #define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL 0x0482 1973 #define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL_BASE_IDX 2 1974 #define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL 0x0483 1975 #define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL_BASE_IDX 2 1976 #define regSDPIF_REQUEST_RATE_LIMIT 0x0484 1977 #define regSDPIF_REQUEST_RATE_LIMIT_BASE_IDX 2 1978 #define regDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x0485 1979 #define regDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2 1980 #define regDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x0486 1981 #define regDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2 1982 1983 1984 // addressBlock: dce_dc_dchubbubl_hubbub_ret_path_dispdec 1985 // base address: 0x0 1986 #define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04af 1987 #define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2 1988 #define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04b0 1989 #define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2 1990 #define regDCHUBBUB_CRC_CTRL 0x04b1 1991 #define regDCHUBBUB_CRC_CTRL_BASE_IDX 2 1992 #define regDCHUBBUB_CRC0_VAL_R 0x04b2 1993 #define regDCHUBBUB_CRC0_VAL_R_BASE_IDX 2 1994 #define regDCHUBBUB_CRC0_VAL_G 0x04b3 1995 #define regDCHUBBUB_CRC0_VAL_G_BASE_IDX 2 1996 #define regDCHUBBUB_CRC0_VAL_B 0x04b4 1997 #define regDCHUBBUB_CRC0_VAL_B_BASE_IDX 2 1998 #define regDCHUBBUB_CRC0_VAL_A 0x04b5 1999 #define regDCHUBBUB_CRC0_VAL_A_BASE_IDX 2 2000 #define regDCHUBBUB_DCC_STAT_CNTL 0x04b6 2001 #define regDCHUBBUB_DCC_STAT_CNTL_BASE_IDX 2 2002 #define regDCHUBBUB_DCC_STAT0 0x04b7 2003 #define regDCHUBBUB_DCC_STAT0_BASE_IDX 2 2004 #define regDCHUBBUB_DCC_STAT1 0x04b8 2005 #define regDCHUBBUB_DCC_STAT1_BASE_IDX 2 2006 #define regDCHUBBUB_DCC_STAT2 0x04b9 2007 #define regDCHUBBUB_DCC_STAT2_BASE_IDX 2 2008 #define regDCHUBBUB_COMPBUF_CTRL 0x04ba 2009 #define regDCHUBBUB_COMPBUF_CTRL_BASE_IDX 2 2010 #define regDCHUBBUB_DET0_CTRL 0x04bb 2011 #define regDCHUBBUB_DET0_CTRL_BASE_IDX 2 2012 #define regDCHUBBUB_DET1_CTRL 0x04bc 2013 #define regDCHUBBUB_DET1_CTRL_BASE_IDX 2 2014 #define regDCHUBBUB_DET2_CTRL 0x04bd 2015 #define regDCHUBBUB_DET2_CTRL_BASE_IDX 2 2016 #define regDCHUBBUB_DET3_CTRL 0x04be 2017 #define regDCHUBBUB_DET3_CTRL_BASE_IDX 2 2018 #define regDCHUBBUB_MEM_PWR_MODE_CTRL 0x04c0 2019 #define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX 2 2020 #define regCOMPBUF_MEM_PWR_CTRL_1 0x04c1 2021 #define regCOMPBUF_MEM_PWR_CTRL_1_BASE_IDX 2 2022 #define regCOMPBUF_MEM_PWR_CTRL_2 0x04c2 2023 #define regCOMPBUF_MEM_PWR_CTRL_2_BASE_IDX 2 2024 #define regDCHUBBUB_MEM_PWR_STATUS 0x04c3 2025 #define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 2026 #define regCOMPBUF_RESERVED_SPACE 0x04c4 2027 #define regCOMPBUF_RESERVED_SPACE_BASE_IDX 2 2028 #define regDCHUBBUB_DEBUG_CTRL_0 0x04c5 2029 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2 2030 #define regDCHUBBUB_CRC1_VAL_R 0x04ca 2031 #define regDCHUBBUB_CRC1_VAL_R_BASE_IDX 2 2032 #define regDCHUBBUB_CRC1_VAL_G 0x04cb 2033 #define regDCHUBBUB_CRC1_VAL_G_BASE_IDX 2 2034 #define regDCHUBBUB_CRC1_VAL_B 0x04cc 2035 #define regDCHUBBUB_CRC1_VAL_B_BASE_IDX 2 2036 #define regDCHUBBUB_CRC1_VAL_A 0x04cd 2037 #define regDCHUBBUB_CRC1_VAL_A_BASE_IDX 2 2038 2039 2040 // addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec 2041 // base address: 0x0 2042 #define regDCN_VM_CONTEXT0_CNTL 0x0559 2043 #define regDCN_VM_CONTEXT0_CNTL_BASE_IDX 2 2044 #define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x055a 2045 #define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2046 #define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x055b 2047 #define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2048 #define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x055c 2049 #define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2050 #define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x055d 2051 #define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2052 #define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x055e 2053 #define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2054 #define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x055f 2055 #define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2056 #define regDCN_VM_CONTEXT1_CNTL 0x0560 2057 #define regDCN_VM_CONTEXT1_CNTL_BASE_IDX 2 2058 #define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0561 2059 #define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2060 #define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0562 2061 #define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2062 #define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0563 2063 #define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2064 #define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0564 2065 #define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2066 #define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0565 2067 #define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2068 #define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0566 2069 #define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2070 #define regDCN_VM_CONTEXT2_CNTL 0x0567 2071 #define regDCN_VM_CONTEXT2_CNTL_BASE_IDX 2 2072 #define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0568 2073 #define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2074 #define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0569 2075 #define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2076 #define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x056a 2077 #define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2078 #define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x056b 2079 #define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2080 #define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x056c 2081 #define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2082 #define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x056d 2083 #define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2084 #define regDCN_VM_CONTEXT3_CNTL 0x056e 2085 #define regDCN_VM_CONTEXT3_CNTL_BASE_IDX 2 2086 #define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x056f 2087 #define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2088 #define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0570 2089 #define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2090 #define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0571 2091 #define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2092 #define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0572 2093 #define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2094 #define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0573 2095 #define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2096 #define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0574 2097 #define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2098 #define regDCN_VM_CONTEXT4_CNTL 0x0575 2099 #define regDCN_VM_CONTEXT4_CNTL_BASE_IDX 2 2100 #define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0576 2101 #define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2102 #define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0577 2103 #define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2104 #define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0578 2105 #define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2106 #define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0579 2107 #define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2108 #define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x057a 2109 #define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2110 #define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x057b 2111 #define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2112 #define regDCN_VM_CONTEXT5_CNTL 0x057c 2113 #define regDCN_VM_CONTEXT5_CNTL_BASE_IDX 2 2114 #define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x057d 2115 #define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2116 #define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x057e 2117 #define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2118 #define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x057f 2119 #define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2120 #define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0580 2121 #define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2122 #define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0581 2123 #define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2124 #define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0582 2125 #define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2126 #define regDCN_VM_CONTEXT6_CNTL 0x0583 2127 #define regDCN_VM_CONTEXT6_CNTL_BASE_IDX 2 2128 #define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0584 2129 #define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2130 #define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0585 2131 #define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2132 #define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0586 2133 #define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2134 #define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0587 2135 #define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2136 #define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0588 2137 #define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2138 #define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0589 2139 #define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2140 #define regDCN_VM_CONTEXT7_CNTL 0x058a 2141 #define regDCN_VM_CONTEXT7_CNTL_BASE_IDX 2 2142 #define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x058b 2143 #define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2144 #define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x058c 2145 #define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2146 #define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x058d 2147 #define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2148 #define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x058e 2149 #define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2150 #define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x058f 2151 #define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2152 #define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0590 2153 #define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2154 #define regDCN_VM_CONTEXT8_CNTL 0x0591 2155 #define regDCN_VM_CONTEXT8_CNTL_BASE_IDX 2 2156 #define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0592 2157 #define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2158 #define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0593 2159 #define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2160 #define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0594 2161 #define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2162 #define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0595 2163 #define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2164 #define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0596 2165 #define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2166 #define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0597 2167 #define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2168 #define regDCN_VM_CONTEXT9_CNTL 0x0598 2169 #define regDCN_VM_CONTEXT9_CNTL_BASE_IDX 2 2170 #define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0599 2171 #define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2172 #define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x059a 2173 #define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2174 #define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x059b 2175 #define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2176 #define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x059c 2177 #define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2178 #define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x059d 2179 #define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2180 #define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x059e 2181 #define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2182 #define regDCN_VM_CONTEXT10_CNTL 0x059f 2183 #define regDCN_VM_CONTEXT10_CNTL_BASE_IDX 2 2184 #define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x05a0 2185 #define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2186 #define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x05a1 2187 #define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2188 #define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x05a2 2189 #define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2190 #define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x05a3 2191 #define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2192 #define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x05a4 2193 #define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2194 #define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x05a5 2195 #define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2196 #define regDCN_VM_CONTEXT11_CNTL 0x05a6 2197 #define regDCN_VM_CONTEXT11_CNTL_BASE_IDX 2 2198 #define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x05a7 2199 #define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2200 #define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x05a8 2201 #define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2202 #define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x05a9 2203 #define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2204 #define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x05aa 2205 #define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2206 #define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x05ab 2207 #define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2208 #define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x05ac 2209 #define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2210 #define regDCN_VM_CONTEXT12_CNTL 0x05ad 2211 #define regDCN_VM_CONTEXT12_CNTL_BASE_IDX 2 2212 #define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x05ae 2213 #define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2214 #define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x05af 2215 #define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2216 #define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x05b0 2217 #define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2218 #define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x05b1 2219 #define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2220 #define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x05b2 2221 #define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2222 #define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x05b3 2223 #define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2224 #define regDCN_VM_CONTEXT13_CNTL 0x05b4 2225 #define regDCN_VM_CONTEXT13_CNTL_BASE_IDX 2 2226 #define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x05b5 2227 #define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2228 #define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x05b6 2229 #define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2230 #define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x05b7 2231 #define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2232 #define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x05b8 2233 #define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2234 #define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x05b9 2235 #define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2236 #define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x05ba 2237 #define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2238 #define regDCN_VM_CONTEXT14_CNTL 0x05bb 2239 #define regDCN_VM_CONTEXT14_CNTL_BASE_IDX 2 2240 #define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x05bc 2241 #define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2242 #define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x05bd 2243 #define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2244 #define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x05be 2245 #define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2246 #define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x05bf 2247 #define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2248 #define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x05c0 2249 #define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2250 #define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x05c1 2251 #define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2252 #define regDCN_VM_CONTEXT15_CNTL 0x05c2 2253 #define regDCN_VM_CONTEXT15_CNTL_BASE_IDX 2 2254 #define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x05c3 2255 #define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2256 #define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x05c4 2257 #define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2258 #define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x05c5 2259 #define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2260 #define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x05c6 2261 #define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2262 #define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x05c7 2263 #define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2264 #define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x05c8 2265 #define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2266 #define regDCN_VM_DEFAULT_ADDR_MSB 0x05c9 2267 #define regDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX 2 2268 #define regDCN_VM_DEFAULT_ADDR_LSB 0x05ca 2269 #define regDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX 2 2270 #define regDCN_VM_FAULT_CNTL 0x05cb 2271 #define regDCN_VM_FAULT_CNTL_BASE_IDX 2 2272 #define regDCN_VM_FAULT_STATUS 0x05cc 2273 #define regDCN_VM_FAULT_STATUS_BASE_IDX 2 2274 #define regDCN_VM_FAULT_ADDR_MSB 0x05cd 2275 #define regDCN_VM_FAULT_ADDR_MSB_BASE_IDX 2 2276 #define regDCN_VM_FAULT_ADDR_LSB 0x05ce 2277 #define regDCN_VM_FAULT_ADDR_LSB_BASE_IDX 2 2278 2279 2280 // addressBlock: dce_dc_dchubbubl_dchubbub_dcperfmon_dc_perfmon_dispdec 2281 // base address: 0x1534 2282 #define regDC_PERFMON6_PERFCOUNTER_CNTL 0x054d 2283 #define regDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2 2284 #define regDC_PERFMON6_PERFCOUNTER_CNTL2 0x054e 2285 #define regDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2 2286 #define regDC_PERFMON6_PERFCOUNTER_STATE 0x054f 2287 #define regDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2 2288 #define regDC_PERFMON6_PERFMON_CNTL 0x0550 2289 #define regDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2 2290 #define regDC_PERFMON6_PERFMON_CNTL2 0x0551 2291 #define regDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2 2292 #define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x0552 2293 #define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 2294 #define regDC_PERFMON6_PERFMON_CVALUE_LOW 0x0553 2295 #define regDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2 2296 #define regDC_PERFMON6_PERFMON_HI 0x0554 2297 #define regDC_PERFMON6_PERFMON_HI_BASE_IDX 2 2298 #define regDC_PERFMON6_PERFMON_LOW 0x0555 2299 #define regDC_PERFMON6_PERFMON_LOW_BASE_IDX 2 2300 2301 2302 // addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec 2303 // base address: 0x0 2304 #define regHUBP0_DCSURF_SURFACE_CONFIG 0x05e5 2305 #define regHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2 2306 #define regHUBP0_DCSURF_ADDR_CONFIG 0x05e6 2307 #define regHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2 2308 #define regHUBP0_DCSURF_TILING_CONFIG 0x05e7 2309 #define regHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2 2310 #define regHUBP0_DCSURF_PRI_VIEWPORT_START 0x05e9 2311 #define regHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 2312 #define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x05ea 2313 #define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 2314 #define regHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x05eb 2315 #define regHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 2316 #define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x05ec 2317 #define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 2318 #define regHUBP0_DCSURF_SEC_VIEWPORT_START 0x05ed 2319 #define regHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 2320 #define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x05ee 2321 #define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 2322 #define regHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x05ef 2323 #define regHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 2324 #define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x05f0 2325 #define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 2326 #define regHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x05f1 2327 #define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 2328 #define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x05f2 2329 #define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 2330 #define regHUBP0_DCHUBP_CNTL 0x05f3 2331 #define regHUBP0_DCHUBP_CNTL_BASE_IDX 2 2332 #define regHUBP0_HUBP_CLK_CNTL 0x05f4 2333 #define regHUBP0_HUBP_CLK_CNTL_BASE_IDX 2 2334 #define regHUBP0_DCHUBP_VMPG_CONFIG 0x05f5 2335 #define regHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2 2336 #define regHUBP0_DCHUBP_MALL_CONFIG 0x05f6 2337 #define regHUBP0_DCHUBP_MALL_CONFIG_BASE_IDX 2 2338 #define regHUBP0_DCHUBP_MALL_SUB_VP 0x05f7 2339 #define regHUBP0_DCHUBP_MALL_SUB_VP_BASE_IDX 2 2340 #define regHUBP0_HUBPREQ_DEBUG_DB 0x05f8 2341 #define regHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2 2342 #define regHUBP0_HUBPREQ_DEBUG 0x05f9 2343 #define regHUBP0_HUBPREQ_DEBUG_BASE_IDX 2 2344 #define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x05fd 2345 #define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 2346 #define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x05fe 2347 #define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 2348 #define regHUBP0_HUBP_MALL_STATUS 0x05ff 2349 #define regHUBP0_HUBP_MALL_STATUS_BASE_IDX 2 2350 2351 2352 // addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec 2353 // base address: 0x0 2354 #define regHUBPREQ0_DCSURF_SURFACE_PITCH 0x0607 2355 #define regHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2 2356 #define regHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x0608 2357 #define regHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 2358 #define regHUBPREQ0_VMID_SETTINGS_0 0x0609 2359 #define regHUBPREQ0_VMID_SETTINGS_0_BASE_IDX 2 2360 #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x060a 2361 #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 2362 #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x060b 2363 #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2364 #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x060c 2365 #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 2366 #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x060d 2367 #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2368 #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x060e 2369 #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 2370 #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x060f 2371 #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2372 #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0610 2373 #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 2374 #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0611 2375 #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2376 #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0612 2377 #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 2378 #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0613 2379 #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2380 #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0614 2381 #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2382 #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0615 2383 #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2384 #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0616 2385 #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 2386 #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0617 2387 #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2388 #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0618 2389 #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2390 #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0619 2391 #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2392 #define regHUBPREQ0_DCSURF_SURFACE_CONTROL 0x061a 2393 #define regHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2 2394 #define regHUBPREQ0_DCSURF_FLIP_CONTROL 0x061b 2395 #define regHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2 2396 #define regHUBPREQ0_DCSURF_FLIP_CONTROL2 0x061c 2397 #define regHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2 2398 #define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x061f 2399 #define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 2400 #define regHUBPREQ0_DCSURF_SURFACE_INUSE 0x0620 2401 #define regHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2 2402 #define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0621 2403 #define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 2404 #define regHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0622 2405 #define regHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 2406 #define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0623 2407 #define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 2408 #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0624 2409 #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 2410 #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0625 2411 #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 2412 #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0626 2413 #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 2414 #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0627 2415 #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 2416 #define regHUBPREQ0_DCN_EXPANSION_MODE 0x0628 2417 #define regHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2 2418 #define regHUBPREQ0_DCN_TTU_QOS_WM 0x0629 2419 #define regHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2 2420 #define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x062a 2421 #define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 2422 #define regHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x062b 2423 #define regHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 2424 #define regHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x062c 2425 #define regHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 2426 #define regHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x062d 2427 #define regHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 2428 #define regHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x062e 2429 #define regHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 2430 #define regHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x062f 2431 #define regHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 2432 #define regHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x0630 2433 #define regHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 2434 #define regHUBPREQ0_DCN_CUR1_TTU_CNTL0 0x0631 2435 #define regHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 2436 #define regHUBPREQ0_DCN_CUR1_TTU_CNTL1 0x0632 2437 #define regHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 2438 #define regHUBPREQ0_DCN_DMDATA_VM_CNTL 0x0633 2439 #define regHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX 2 2440 #define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0634 2441 #define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 2442 #define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0635 2443 #define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 2444 #define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x0642 2445 #define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 2446 #define regHUBPREQ0_BLANK_OFFSET_0 0x0643 2447 #define regHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2 2448 #define regHUBPREQ0_BLANK_OFFSET_1 0x0644 2449 #define regHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2 2450 #define regHUBPREQ0_DST_DIMENSIONS 0x0645 2451 #define regHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2 2452 #define regHUBPREQ0_DST_AFTER_SCALER 0x0646 2453 #define regHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2 2454 #define regHUBPREQ0_PREFETCH_SETTINGS 0x0647 2455 #define regHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX 2 2456 #define regHUBPREQ0_PREFETCH_SETTINGS_C 0x0648 2457 #define regHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX 2 2458 #define regHUBPREQ0_VBLANK_PARAMETERS_0 0x0649 2459 #define regHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2 2460 #define regHUBPREQ0_VBLANK_PARAMETERS_1 0x064a 2461 #define regHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2 2462 #define regHUBPREQ0_VBLANK_PARAMETERS_2 0x064b 2463 #define regHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2 2464 #define regHUBPREQ0_VBLANK_PARAMETERS_3 0x064c 2465 #define regHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2 2466 #define regHUBPREQ0_VBLANK_PARAMETERS_4 0x064d 2467 #define regHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2 2468 #define regHUBPREQ0_FLIP_PARAMETERS_0 0x064e 2469 #define regHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX 2 2470 #define regHUBPREQ0_FLIP_PARAMETERS_1 0x064f 2471 #define regHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX 2 2472 #define regHUBPREQ0_FLIP_PARAMETERS_2 0x0650 2473 #define regHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX 2 2474 #define regHUBPREQ0_NOM_PARAMETERS_0 0x0651 2475 #define regHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2 2476 #define regHUBPREQ0_NOM_PARAMETERS_1 0x0652 2477 #define regHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2 2478 #define regHUBPREQ0_NOM_PARAMETERS_2 0x0653 2479 #define regHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2 2480 #define regHUBPREQ0_NOM_PARAMETERS_3 0x0654 2481 #define regHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2 2482 #define regHUBPREQ0_NOM_PARAMETERS_4 0x0655 2483 #define regHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2 2484 #define regHUBPREQ0_NOM_PARAMETERS_5 0x0656 2485 #define regHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2 2486 #define regHUBPREQ0_NOM_PARAMETERS_6 0x0657 2487 #define regHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2 2488 #define regHUBPREQ0_NOM_PARAMETERS_7 0x0658 2489 #define regHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2 2490 #define regHUBPREQ0_PER_LINE_DELIVERY_PRE 0x0659 2491 #define regHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2 2492 #define regHUBPREQ0_PER_LINE_DELIVERY 0x065a 2493 #define regHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2 2494 #define regHUBPREQ0_CURSOR_SETTINGS 0x065b 2495 #define regHUBPREQ0_CURSOR_SETTINGS_BASE_IDX 2 2496 #define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x065c 2497 #define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 2498 #define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0x065d 2499 #define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 2500 #define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x065e 2501 #define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 2502 #define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x065f 2503 #define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 2504 #define regHUBPREQ0_VBLANK_PARAMETERS_5 0x0662 2505 #define regHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX 2 2506 #define regHUBPREQ0_VBLANK_PARAMETERS_6 0x0663 2507 #define regHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX 2 2508 #define regHUBPREQ0_FLIP_PARAMETERS_3 0x0664 2509 #define regHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX 2 2510 #define regHUBPREQ0_FLIP_PARAMETERS_4 0x0665 2511 #define regHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX 2 2512 #define regHUBPREQ0_FLIP_PARAMETERS_5 0x0666 2513 #define regHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX 2 2514 #define regHUBPREQ0_FLIP_PARAMETERS_6 0x0667 2515 #define regHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX 2 2516 #define regHUBPREQ0_UCLK_PSTATE_FORCE 0x0668 2517 #define regHUBPREQ0_UCLK_PSTATE_FORCE_BASE_IDX 2 2518 #define regHUBPREQ0_HUBPREQ_STATUS_REG0 0x0669 2519 #define regHUBPREQ0_HUBPREQ_STATUS_REG0_BASE_IDX 2 2520 #define regHUBPREQ0_HUBPREQ_STATUS_REG1 0x066a 2521 #define regHUBPREQ0_HUBPREQ_STATUS_REG1_BASE_IDX 2 2522 #define regHUBPREQ0_HUBPREQ_STATUS_REG2 0x066b 2523 #define regHUBPREQ0_HUBPREQ_STATUS_REG2_BASE_IDX 2 2524 2525 2526 // addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec 2527 // base address: 0x0 2528 #define regHUBPRET0_HUBPRET_CONTROL 0x066c 2529 #define regHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2 2530 #define regHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x066d 2531 #define regHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 2532 #define regHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x066e 2533 #define regHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 2534 #define regHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x066f 2535 #define regHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 2536 #define regHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x0670 2537 #define regHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 2538 #define regHUBPRET0_HUBPRET_READ_LINE0 0x0671 2539 #define regHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2 2540 #define regHUBPRET0_HUBPRET_READ_LINE1 0x0672 2541 #define regHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2 2542 #define regHUBPRET0_HUBPRET_INTERRUPT 0x0673 2543 #define regHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2 2544 #define regHUBPRET0_HUBPRET_READ_LINE_VALUE 0x0674 2545 #define regHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 2546 #define regHUBPRET0_HUBPRET_READ_LINE_STATUS 0x0675 2547 #define regHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 2548 2549 2550 // addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec 2551 // base address: 0x0 2552 #define regCURSOR0_0_CURSOR_CONTROL 0x0678 2553 #define regCURSOR0_0_CURSOR_CONTROL_BASE_IDX 2 2554 #define regCURSOR0_0_CURSOR_SURFACE_ADDRESS 0x0679 2555 #define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 2556 #define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0x067a 2557 #define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2558 #define regCURSOR0_0_CURSOR_SIZE 0x067b 2559 #define regCURSOR0_0_CURSOR_SIZE_BASE_IDX 2 2560 #define regCURSOR0_0_CURSOR_POSITION 0x067c 2561 #define regCURSOR0_0_CURSOR_POSITION_BASE_IDX 2 2562 #define regCURSOR0_0_CURSOR_HOT_SPOT 0x067d 2563 #define regCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX 2 2564 #define regCURSOR0_0_CURSOR_STEREO_CONTROL 0x067e 2565 #define regCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX 2 2566 #define regCURSOR0_0_CURSOR_DST_OFFSET 0x067f 2567 #define regCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX 2 2568 #define regCURSOR0_0_CURSOR_MEM_PWR_CTRL 0x0680 2569 #define regCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 2570 #define regCURSOR0_0_CURSOR_MEM_PWR_STATUS 0x0681 2571 #define regCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 2572 #define regCURSOR0_0_DMDATA_ADDRESS_HIGH 0x0682 2573 #define regCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX 2 2574 #define regCURSOR0_0_DMDATA_ADDRESS_LOW 0x0683 2575 #define regCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX 2 2576 #define regCURSOR0_0_DMDATA_CNTL 0x0684 2577 #define regCURSOR0_0_DMDATA_CNTL_BASE_IDX 2 2578 #define regCURSOR0_0_DMDATA_QOS_CNTL 0x0685 2579 #define regCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX 2 2580 #define regCURSOR0_0_DMDATA_STATUS 0x0686 2581 #define regCURSOR0_0_DMDATA_STATUS_BASE_IDX 2 2582 #define regCURSOR0_0_DMDATA_SW_CNTL 0x0687 2583 #define regCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX 2 2584 #define regCURSOR0_0_DMDATA_SW_DATA 0x0688 2585 #define regCURSOR0_0_DMDATA_SW_DATA_BASE_IDX 2 2586 2587 2588 // addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 2589 // base address: 0x1a74 2590 #define regDC_PERFMON7_PERFCOUNTER_CNTL 0x069d 2591 #define regDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2 2592 #define regDC_PERFMON7_PERFCOUNTER_CNTL2 0x069e 2593 #define regDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2 2594 #define regDC_PERFMON7_PERFCOUNTER_STATE 0x069f 2595 #define regDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2 2596 #define regDC_PERFMON7_PERFMON_CNTL 0x06a0 2597 #define regDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2 2598 #define regDC_PERFMON7_PERFMON_CNTL2 0x06a1 2599 #define regDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2 2600 #define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x06a2 2601 #define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 2602 #define regDC_PERFMON7_PERFMON_CVALUE_LOW 0x06a3 2603 #define regDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2 2604 #define regDC_PERFMON7_PERFMON_HI 0x06a4 2605 #define regDC_PERFMON7_PERFMON_HI_BASE_IDX 2 2606 #define regDC_PERFMON7_PERFMON_LOW 0x06a5 2607 #define regDC_PERFMON7_PERFMON_LOW_BASE_IDX 2 2608 2609 2610 // addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec 2611 // base address: 0x370 2612 #define regHUBP1_DCSURF_SURFACE_CONFIG 0x06c1 2613 #define regHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2 2614 #define regHUBP1_DCSURF_ADDR_CONFIG 0x06c2 2615 #define regHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2 2616 #define regHUBP1_DCSURF_TILING_CONFIG 0x06c3 2617 #define regHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2 2618 #define regHUBP1_DCSURF_PRI_VIEWPORT_START 0x06c5 2619 #define regHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 2620 #define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x06c6 2621 #define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 2622 #define regHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x06c7 2623 #define regHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 2624 #define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06c8 2625 #define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 2626 #define regHUBP1_DCSURF_SEC_VIEWPORT_START 0x06c9 2627 #define regHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 2628 #define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x06ca 2629 #define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 2630 #define regHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x06cb 2631 #define regHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 2632 #define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06cc 2633 #define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 2634 #define regHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x06cd 2635 #define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 2636 #define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x06ce 2637 #define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 2638 #define regHUBP1_DCHUBP_CNTL 0x06cf 2639 #define regHUBP1_DCHUBP_CNTL_BASE_IDX 2 2640 #define regHUBP1_HUBP_CLK_CNTL 0x06d0 2641 #define regHUBP1_HUBP_CLK_CNTL_BASE_IDX 2 2642 #define regHUBP1_DCHUBP_VMPG_CONFIG 0x06d1 2643 #define regHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2 2644 #define regHUBP1_DCHUBP_MALL_CONFIG 0x06d2 2645 #define regHUBP1_DCHUBP_MALL_CONFIG_BASE_IDX 2 2646 #define regHUBP1_DCHUBP_MALL_SUB_VP 0x06d3 2647 #define regHUBP1_DCHUBP_MALL_SUB_VP_BASE_IDX 2 2648 #define regHUBP1_HUBPREQ_DEBUG_DB 0x06d4 2649 #define regHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2 2650 #define regHUBP1_HUBPREQ_DEBUG 0x06d5 2651 #define regHUBP1_HUBPREQ_DEBUG_BASE_IDX 2 2652 #define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06d9 2653 #define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 2654 #define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06da 2655 #define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 2656 #define regHUBP1_HUBP_MALL_STATUS 0x06db 2657 #define regHUBP1_HUBP_MALL_STATUS_BASE_IDX 2 2658 2659 2660 // addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec 2661 // base address: 0x370 2662 #define regHUBPREQ1_DCSURF_SURFACE_PITCH 0x06e3 2663 #define regHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2 2664 #define regHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x06e4 2665 #define regHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 2666 #define regHUBPREQ1_VMID_SETTINGS_0 0x06e5 2667 #define regHUBPREQ1_VMID_SETTINGS_0_BASE_IDX 2 2668 #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x06e6 2669 #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 2670 #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x06e7 2671 #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2672 #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x06e8 2673 #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 2674 #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x06e9 2675 #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2676 #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x06ea 2677 #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 2678 #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x06eb 2679 #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2680 #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x06ec 2681 #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 2682 #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x06ed 2683 #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2684 #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x06ee 2685 #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 2686 #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x06ef 2687 #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2688 #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x06f0 2689 #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2690 #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x06f1 2691 #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2692 #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x06f2 2693 #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 2694 #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x06f3 2695 #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2696 #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x06f4 2697 #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2698 #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x06f5 2699 #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2700 #define regHUBPREQ1_DCSURF_SURFACE_CONTROL 0x06f6 2701 #define regHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2 2702 #define regHUBPREQ1_DCSURF_FLIP_CONTROL 0x06f7 2703 #define regHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2 2704 #define regHUBPREQ1_DCSURF_FLIP_CONTROL2 0x06f8 2705 #define regHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2 2706 #define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x06fb 2707 #define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 2708 #define regHUBPREQ1_DCSURF_SURFACE_INUSE 0x06fc 2709 #define regHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2 2710 #define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x06fd 2711 #define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 2712 #define regHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x06fe 2713 #define regHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 2714 #define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x06ff 2715 #define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 2716 #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x0700 2717 #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 2718 #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0701 2719 #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 2720 #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0702 2721 #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 2722 #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0703 2723 #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 2724 #define regHUBPREQ1_DCN_EXPANSION_MODE 0x0704 2725 #define regHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2 2726 #define regHUBPREQ1_DCN_TTU_QOS_WM 0x0705 2727 #define regHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2 2728 #define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x0706 2729 #define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 2730 #define regHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x0707 2731 #define regHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 2732 #define regHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x0708 2733 #define regHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 2734 #define regHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x0709 2735 #define regHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 2736 #define regHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x070a 2737 #define regHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 2738 #define regHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x070b 2739 #define regHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 2740 #define regHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x070c 2741 #define regHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 2742 #define regHUBPREQ1_DCN_CUR1_TTU_CNTL0 0x070d 2743 #define regHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 2744 #define regHUBPREQ1_DCN_CUR1_TTU_CNTL1 0x070e 2745 #define regHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 2746 #define regHUBPREQ1_DCN_DMDATA_VM_CNTL 0x070f 2747 #define regHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX 2 2748 #define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0710 2749 #define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 2750 #define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0711 2751 #define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 2752 #define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x071e 2753 #define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 2754 #define regHUBPREQ1_BLANK_OFFSET_0 0x071f 2755 #define regHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2 2756 #define regHUBPREQ1_BLANK_OFFSET_1 0x0720 2757 #define regHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2 2758 #define regHUBPREQ1_DST_DIMENSIONS 0x0721 2759 #define regHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2 2760 #define regHUBPREQ1_DST_AFTER_SCALER 0x0722 2761 #define regHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2 2762 #define regHUBPREQ1_PREFETCH_SETTINGS 0x0723 2763 #define regHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX 2 2764 #define regHUBPREQ1_PREFETCH_SETTINGS_C 0x0724 2765 #define regHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX 2 2766 #define regHUBPREQ1_VBLANK_PARAMETERS_0 0x0725 2767 #define regHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2 2768 #define regHUBPREQ1_VBLANK_PARAMETERS_1 0x0726 2769 #define regHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2 2770 #define regHUBPREQ1_VBLANK_PARAMETERS_2 0x0727 2771 #define regHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2 2772 #define regHUBPREQ1_VBLANK_PARAMETERS_3 0x0728 2773 #define regHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2 2774 #define regHUBPREQ1_VBLANK_PARAMETERS_4 0x0729 2775 #define regHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2 2776 #define regHUBPREQ1_FLIP_PARAMETERS_0 0x072a 2777 #define regHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX 2 2778 #define regHUBPREQ1_FLIP_PARAMETERS_1 0x072b 2779 #define regHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX 2 2780 #define regHUBPREQ1_FLIP_PARAMETERS_2 0x072c 2781 #define regHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX 2 2782 #define regHUBPREQ1_NOM_PARAMETERS_0 0x072d 2783 #define regHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2 2784 #define regHUBPREQ1_NOM_PARAMETERS_1 0x072e 2785 #define regHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2 2786 #define regHUBPREQ1_NOM_PARAMETERS_2 0x072f 2787 #define regHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2 2788 #define regHUBPREQ1_NOM_PARAMETERS_3 0x0730 2789 #define regHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2 2790 #define regHUBPREQ1_NOM_PARAMETERS_4 0x0731 2791 #define regHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2 2792 #define regHUBPREQ1_NOM_PARAMETERS_5 0x0732 2793 #define regHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2 2794 #define regHUBPREQ1_NOM_PARAMETERS_6 0x0733 2795 #define regHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2 2796 #define regHUBPREQ1_NOM_PARAMETERS_7 0x0734 2797 #define regHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2 2798 #define regHUBPREQ1_PER_LINE_DELIVERY_PRE 0x0735 2799 #define regHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2 2800 #define regHUBPREQ1_PER_LINE_DELIVERY 0x0736 2801 #define regHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2 2802 #define regHUBPREQ1_CURSOR_SETTINGS 0x0737 2803 #define regHUBPREQ1_CURSOR_SETTINGS_BASE_IDX 2 2804 #define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x0738 2805 #define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 2806 #define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0x0739 2807 #define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 2808 #define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x073a 2809 #define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 2810 #define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x073b 2811 #define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 2812 #define regHUBPREQ1_VBLANK_PARAMETERS_5 0x073e 2813 #define regHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX 2 2814 #define regHUBPREQ1_VBLANK_PARAMETERS_6 0x073f 2815 #define regHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX 2 2816 #define regHUBPREQ1_FLIP_PARAMETERS_3 0x0740 2817 #define regHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX 2 2818 #define regHUBPREQ1_FLIP_PARAMETERS_4 0x0741 2819 #define regHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX 2 2820 #define regHUBPREQ1_FLIP_PARAMETERS_5 0x0742 2821 #define regHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX 2 2822 #define regHUBPREQ1_FLIP_PARAMETERS_6 0x0743 2823 #define regHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX 2 2824 #define regHUBPREQ1_UCLK_PSTATE_FORCE 0x0744 2825 #define regHUBPREQ1_UCLK_PSTATE_FORCE_BASE_IDX 2 2826 #define regHUBPREQ1_HUBPREQ_STATUS_REG0 0x0745 2827 #define regHUBPREQ1_HUBPREQ_STATUS_REG0_BASE_IDX 2 2828 #define regHUBPREQ1_HUBPREQ_STATUS_REG1 0x0746 2829 #define regHUBPREQ1_HUBPREQ_STATUS_REG1_BASE_IDX 2 2830 #define regHUBPREQ1_HUBPREQ_STATUS_REG2 0x0747 2831 #define regHUBPREQ1_HUBPREQ_STATUS_REG2_BASE_IDX 2 2832 2833 2834 // addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec 2835 // base address: 0x370 2836 #define regHUBPRET1_HUBPRET_CONTROL 0x0748 2837 #define regHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2 2838 #define regHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x0749 2839 #define regHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 2840 #define regHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x074a 2841 #define regHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 2842 #define regHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x074b 2843 #define regHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 2844 #define regHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x074c 2845 #define regHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 2846 #define regHUBPRET1_HUBPRET_READ_LINE0 0x074d 2847 #define regHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2 2848 #define regHUBPRET1_HUBPRET_READ_LINE1 0x074e 2849 #define regHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2 2850 #define regHUBPRET1_HUBPRET_INTERRUPT 0x074f 2851 #define regHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2 2852 #define regHUBPRET1_HUBPRET_READ_LINE_VALUE 0x0750 2853 #define regHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 2854 #define regHUBPRET1_HUBPRET_READ_LINE_STATUS 0x0751 2855 #define regHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 2856 2857 2858 // addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec 2859 // base address: 0x370 2860 #define regCURSOR0_1_CURSOR_CONTROL 0x0754 2861 #define regCURSOR0_1_CURSOR_CONTROL_BASE_IDX 2 2862 #define regCURSOR0_1_CURSOR_SURFACE_ADDRESS 0x0755 2863 #define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 2864 #define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0x0756 2865 #define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2866 #define regCURSOR0_1_CURSOR_SIZE 0x0757 2867 #define regCURSOR0_1_CURSOR_SIZE_BASE_IDX 2 2868 #define regCURSOR0_1_CURSOR_POSITION 0x0758 2869 #define regCURSOR0_1_CURSOR_POSITION_BASE_IDX 2 2870 #define regCURSOR0_1_CURSOR_HOT_SPOT 0x0759 2871 #define regCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX 2 2872 #define regCURSOR0_1_CURSOR_STEREO_CONTROL 0x075a 2873 #define regCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX 2 2874 #define regCURSOR0_1_CURSOR_DST_OFFSET 0x075b 2875 #define regCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX 2 2876 #define regCURSOR0_1_CURSOR_MEM_PWR_CTRL 0x075c 2877 #define regCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 2878 #define regCURSOR0_1_CURSOR_MEM_PWR_STATUS 0x075d 2879 #define regCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 2880 #define regCURSOR0_1_DMDATA_ADDRESS_HIGH 0x075e 2881 #define regCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX 2 2882 #define regCURSOR0_1_DMDATA_ADDRESS_LOW 0x075f 2883 #define regCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX 2 2884 #define regCURSOR0_1_DMDATA_CNTL 0x0760 2885 #define regCURSOR0_1_DMDATA_CNTL_BASE_IDX 2 2886 #define regCURSOR0_1_DMDATA_QOS_CNTL 0x0761 2887 #define regCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX 2 2888 #define regCURSOR0_1_DMDATA_STATUS 0x0762 2889 #define regCURSOR0_1_DMDATA_STATUS_BASE_IDX 2 2890 #define regCURSOR0_1_DMDATA_SW_CNTL 0x0763 2891 #define regCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX 2 2892 #define regCURSOR0_1_DMDATA_SW_DATA 0x0764 2893 #define regCURSOR0_1_DMDATA_SW_DATA_BASE_IDX 2 2894 2895 2896 // addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 2897 // base address: 0x1de4 2898 #define regDC_PERFMON8_PERFCOUNTER_CNTL 0x0779 2899 #define regDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2 2900 #define regDC_PERFMON8_PERFCOUNTER_CNTL2 0x077a 2901 #define regDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2 2902 #define regDC_PERFMON8_PERFCOUNTER_STATE 0x077b 2903 #define regDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2 2904 #define regDC_PERFMON8_PERFMON_CNTL 0x077c 2905 #define regDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2 2906 #define regDC_PERFMON8_PERFMON_CNTL2 0x077d 2907 #define regDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2 2908 #define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x077e 2909 #define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 2910 #define regDC_PERFMON8_PERFMON_CVALUE_LOW 0x077f 2911 #define regDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2 2912 #define regDC_PERFMON8_PERFMON_HI 0x0780 2913 #define regDC_PERFMON8_PERFMON_HI_BASE_IDX 2 2914 #define regDC_PERFMON8_PERFMON_LOW 0x0781 2915 #define regDC_PERFMON8_PERFMON_LOW_BASE_IDX 2 2916 2917 2918 // addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec 2919 // base address: 0x6e0 2920 #define regHUBP2_DCSURF_SURFACE_CONFIG 0x079d 2921 #define regHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2 2922 #define regHUBP2_DCSURF_ADDR_CONFIG 0x079e 2923 #define regHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2 2924 #define regHUBP2_DCSURF_TILING_CONFIG 0x079f 2925 #define regHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2 2926 #define regHUBP2_DCSURF_PRI_VIEWPORT_START 0x07a1 2927 #define regHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 2928 #define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a2 2929 #define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 2930 #define regHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x07a3 2931 #define regHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 2932 #define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07a4 2933 #define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 2934 #define regHUBP2_DCSURF_SEC_VIEWPORT_START 0x07a5 2935 #define regHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 2936 #define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x07a6 2937 #define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 2938 #define regHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x07a7 2939 #define regHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 2940 #define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07a8 2941 #define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 2942 #define regHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x07a9 2943 #define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 2944 #define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x07aa 2945 #define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 2946 #define regHUBP2_DCHUBP_CNTL 0x07ab 2947 #define regHUBP2_DCHUBP_CNTL_BASE_IDX 2 2948 #define regHUBP2_HUBP_CLK_CNTL 0x07ac 2949 #define regHUBP2_HUBP_CLK_CNTL_BASE_IDX 2 2950 #define regHUBP2_DCHUBP_VMPG_CONFIG 0x07ad 2951 #define regHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2 2952 #define regHUBP2_DCHUBP_MALL_CONFIG 0x07ae 2953 #define regHUBP2_DCHUBP_MALL_CONFIG_BASE_IDX 2 2954 #define regHUBP2_DCHUBP_MALL_SUB_VP 0x07af 2955 #define regHUBP2_DCHUBP_MALL_SUB_VP_BASE_IDX 2 2956 #define regHUBP2_HUBPREQ_DEBUG_DB 0x07b0 2957 #define regHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2 2958 #define regHUBP2_HUBPREQ_DEBUG 0x07b1 2959 #define regHUBP2_HUBPREQ_DEBUG_BASE_IDX 2 2960 #define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07b5 2961 #define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 2962 #define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07b6 2963 #define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 2964 #define regHUBP2_HUBP_MALL_STATUS 0x07b7 2965 #define regHUBP2_HUBP_MALL_STATUS_BASE_IDX 2 2966 2967 2968 // addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec 2969 // base address: 0x6e0 2970 #define regHUBPREQ2_DCSURF_SURFACE_PITCH 0x07bf 2971 #define regHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2 2972 #define regHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x07c0 2973 #define regHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 2974 #define regHUBPREQ2_VMID_SETTINGS_0 0x07c1 2975 #define regHUBPREQ2_VMID_SETTINGS_0_BASE_IDX 2 2976 #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c2 2977 #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 2978 #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07c3 2979 #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2980 #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07c4 2981 #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 2982 #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07c5 2983 #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2984 #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07c6 2985 #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 2986 #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07c7 2987 #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2988 #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07c8 2989 #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 2990 #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07c9 2991 #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2992 #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07ca 2993 #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 2994 #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07cb 2995 #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2996 #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07cc 2997 #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2998 #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07cd 2999 #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3000 #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07ce 3001 #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 3002 #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07cf 3003 #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3004 #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d0 3005 #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3006 #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d1 3007 #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3008 #define regHUBPREQ2_DCSURF_SURFACE_CONTROL 0x07d2 3009 #define regHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2 3010 #define regHUBPREQ2_DCSURF_FLIP_CONTROL 0x07d3 3011 #define regHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2 3012 #define regHUBPREQ2_DCSURF_FLIP_CONTROL2 0x07d4 3013 #define regHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2 3014 #define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x07d7 3015 #define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 3016 #define regHUBPREQ2_DCSURF_SURFACE_INUSE 0x07d8 3017 #define regHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2 3018 #define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x07d9 3019 #define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 3020 #define regHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x07da 3021 #define regHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 3022 #define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x07db 3023 #define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 3024 #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x07dc 3025 #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 3026 #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07dd 3027 #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 3028 #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07de 3029 #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 3030 #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07df 3031 #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 3032 #define regHUBPREQ2_DCN_EXPANSION_MODE 0x07e0 3033 #define regHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2 3034 #define regHUBPREQ2_DCN_TTU_QOS_WM 0x07e1 3035 #define regHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2 3036 #define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x07e2 3037 #define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 3038 #define regHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x07e3 3039 #define regHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 3040 #define regHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x07e4 3041 #define regHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 3042 #define regHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x07e5 3043 #define regHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 3044 #define regHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x07e6 3045 #define regHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 3046 #define regHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x07e7 3047 #define regHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 3048 #define regHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x07e8 3049 #define regHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 3050 #define regHUBPREQ2_DCN_CUR1_TTU_CNTL0 0x07e9 3051 #define regHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 3052 #define regHUBPREQ2_DCN_CUR1_TTU_CNTL1 0x07ea 3053 #define regHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 3054 #define regHUBPREQ2_DCN_DMDATA_VM_CNTL 0x07eb 3055 #define regHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX 2 3056 #define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x07ec 3057 #define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 3058 #define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x07ed 3059 #define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 3060 #define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x07fa 3061 #define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 3062 #define regHUBPREQ2_BLANK_OFFSET_0 0x07fb 3063 #define regHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2 3064 #define regHUBPREQ2_BLANK_OFFSET_1 0x07fc 3065 #define regHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2 3066 #define regHUBPREQ2_DST_DIMENSIONS 0x07fd 3067 #define regHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2 3068 #define regHUBPREQ2_DST_AFTER_SCALER 0x07fe 3069 #define regHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2 3070 #define regHUBPREQ2_PREFETCH_SETTINGS 0x07ff 3071 #define regHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX 2 3072 #define regHUBPREQ2_PREFETCH_SETTINGS_C 0x0800 3073 #define regHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX 2 3074 #define regHUBPREQ2_VBLANK_PARAMETERS_0 0x0801 3075 #define regHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2 3076 #define regHUBPREQ2_VBLANK_PARAMETERS_1 0x0802 3077 #define regHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2 3078 #define regHUBPREQ2_VBLANK_PARAMETERS_2 0x0803 3079 #define regHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2 3080 #define regHUBPREQ2_VBLANK_PARAMETERS_3 0x0804 3081 #define regHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2 3082 #define regHUBPREQ2_VBLANK_PARAMETERS_4 0x0805 3083 #define regHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2 3084 #define regHUBPREQ2_FLIP_PARAMETERS_0 0x0806 3085 #define regHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX 2 3086 #define regHUBPREQ2_FLIP_PARAMETERS_1 0x0807 3087 #define regHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX 2 3088 #define regHUBPREQ2_FLIP_PARAMETERS_2 0x0808 3089 #define regHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX 2 3090 #define regHUBPREQ2_NOM_PARAMETERS_0 0x0809 3091 #define regHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2 3092 #define regHUBPREQ2_NOM_PARAMETERS_1 0x080a 3093 #define regHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2 3094 #define regHUBPREQ2_NOM_PARAMETERS_2 0x080b 3095 #define regHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2 3096 #define regHUBPREQ2_NOM_PARAMETERS_3 0x080c 3097 #define regHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2 3098 #define regHUBPREQ2_NOM_PARAMETERS_4 0x080d 3099 #define regHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2 3100 #define regHUBPREQ2_NOM_PARAMETERS_5 0x080e 3101 #define regHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2 3102 #define regHUBPREQ2_NOM_PARAMETERS_6 0x080f 3103 #define regHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2 3104 #define regHUBPREQ2_NOM_PARAMETERS_7 0x0810 3105 #define regHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2 3106 #define regHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0811 3107 #define regHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2 3108 #define regHUBPREQ2_PER_LINE_DELIVERY 0x0812 3109 #define regHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2 3110 #define regHUBPREQ2_CURSOR_SETTINGS 0x0813 3111 #define regHUBPREQ2_CURSOR_SETTINGS_BASE_IDX 2 3112 #define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0814 3113 #define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 3114 #define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT 0x0815 3115 #define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 3116 #define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0816 3117 #define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 3118 #define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x0817 3119 #define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 3120 #define regHUBPREQ2_VBLANK_PARAMETERS_5 0x081a 3121 #define regHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX 2 3122 #define regHUBPREQ2_VBLANK_PARAMETERS_6 0x081b 3123 #define regHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX 2 3124 #define regHUBPREQ2_FLIP_PARAMETERS_3 0x081c 3125 #define regHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX 2 3126 #define regHUBPREQ2_FLIP_PARAMETERS_4 0x081d 3127 #define regHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX 2 3128 #define regHUBPREQ2_FLIP_PARAMETERS_5 0x081e 3129 #define regHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX 2 3130 #define regHUBPREQ2_FLIP_PARAMETERS_6 0x081f 3131 #define regHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX 2 3132 #define regHUBPREQ2_UCLK_PSTATE_FORCE 0x0820 3133 #define regHUBPREQ2_UCLK_PSTATE_FORCE_BASE_IDX 2 3134 #define regHUBPREQ2_HUBPREQ_STATUS_REG0 0x0821 3135 #define regHUBPREQ2_HUBPREQ_STATUS_REG0_BASE_IDX 2 3136 #define regHUBPREQ2_HUBPREQ_STATUS_REG1 0x0822 3137 #define regHUBPREQ2_HUBPREQ_STATUS_REG1_BASE_IDX 2 3138 #define regHUBPREQ2_HUBPREQ_STATUS_REG2 0x0823 3139 #define regHUBPREQ2_HUBPREQ_STATUS_REG2_BASE_IDX 2 3140 3141 3142 // addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec 3143 // base address: 0x6e0 3144 #define regHUBPRET2_HUBPRET_CONTROL 0x0824 3145 #define regHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2 3146 #define regHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0825 3147 #define regHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 3148 #define regHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x0826 3149 #define regHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 3150 #define regHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x0827 3151 #define regHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 3152 #define regHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x0828 3153 #define regHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 3154 #define regHUBPRET2_HUBPRET_READ_LINE0 0x0829 3155 #define regHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2 3156 #define regHUBPRET2_HUBPRET_READ_LINE1 0x082a 3157 #define regHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2 3158 #define regHUBPRET2_HUBPRET_INTERRUPT 0x082b 3159 #define regHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2 3160 #define regHUBPRET2_HUBPRET_READ_LINE_VALUE 0x082c 3161 #define regHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 3162 #define regHUBPRET2_HUBPRET_READ_LINE_STATUS 0x082d 3163 #define regHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 3164 3165 3166 // addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec 3167 // base address: 0x6e0 3168 #define regCURSOR0_2_CURSOR_CONTROL 0x0830 3169 #define regCURSOR0_2_CURSOR_CONTROL_BASE_IDX 2 3170 #define regCURSOR0_2_CURSOR_SURFACE_ADDRESS 0x0831 3171 #define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 3172 #define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH 0x0832 3173 #define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3174 #define regCURSOR0_2_CURSOR_SIZE 0x0833 3175 #define regCURSOR0_2_CURSOR_SIZE_BASE_IDX 2 3176 #define regCURSOR0_2_CURSOR_POSITION 0x0834 3177 #define regCURSOR0_2_CURSOR_POSITION_BASE_IDX 2 3178 #define regCURSOR0_2_CURSOR_HOT_SPOT 0x0835 3179 #define regCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX 2 3180 #define regCURSOR0_2_CURSOR_STEREO_CONTROL 0x0836 3181 #define regCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX 2 3182 #define regCURSOR0_2_CURSOR_DST_OFFSET 0x0837 3183 #define regCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX 2 3184 #define regCURSOR0_2_CURSOR_MEM_PWR_CTRL 0x0838 3185 #define regCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 3186 #define regCURSOR0_2_CURSOR_MEM_PWR_STATUS 0x0839 3187 #define regCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 3188 #define regCURSOR0_2_DMDATA_ADDRESS_HIGH 0x083a 3189 #define regCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX 2 3190 #define regCURSOR0_2_DMDATA_ADDRESS_LOW 0x083b 3191 #define regCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX 2 3192 #define regCURSOR0_2_DMDATA_CNTL 0x083c 3193 #define regCURSOR0_2_DMDATA_CNTL_BASE_IDX 2 3194 #define regCURSOR0_2_DMDATA_QOS_CNTL 0x083d 3195 #define regCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX 2 3196 #define regCURSOR0_2_DMDATA_STATUS 0x083e 3197 #define regCURSOR0_2_DMDATA_STATUS_BASE_IDX 2 3198 #define regCURSOR0_2_DMDATA_SW_CNTL 0x083f 3199 #define regCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX 2 3200 #define regCURSOR0_2_DMDATA_SW_DATA 0x0840 3201 #define regCURSOR0_2_DMDATA_SW_DATA_BASE_IDX 2 3202 3203 3204 // addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 3205 // base address: 0x2154 3206 #define regDC_PERFMON9_PERFCOUNTER_CNTL 0x0855 3207 #define regDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2 3208 #define regDC_PERFMON9_PERFCOUNTER_CNTL2 0x0856 3209 #define regDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2 3210 #define regDC_PERFMON9_PERFCOUNTER_STATE 0x0857 3211 #define regDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2 3212 #define regDC_PERFMON9_PERFMON_CNTL 0x0858 3213 #define regDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2 3214 #define regDC_PERFMON9_PERFMON_CNTL2 0x0859 3215 #define regDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2 3216 #define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x085a 3217 #define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 3218 #define regDC_PERFMON9_PERFMON_CVALUE_LOW 0x085b 3219 #define regDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2 3220 #define regDC_PERFMON9_PERFMON_HI 0x085c 3221 #define regDC_PERFMON9_PERFMON_HI_BASE_IDX 2 3222 #define regDC_PERFMON9_PERFMON_LOW 0x085d 3223 #define regDC_PERFMON9_PERFMON_LOW_BASE_IDX 2 3224 3225 3226 // addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec 3227 // base address: 0xa50 3228 #define regHUBP3_DCSURF_SURFACE_CONFIG 0x0879 3229 #define regHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2 3230 #define regHUBP3_DCSURF_ADDR_CONFIG 0x087a 3231 #define regHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2 3232 #define regHUBP3_DCSURF_TILING_CONFIG 0x087b 3233 #define regHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2 3234 #define regHUBP3_DCSURF_PRI_VIEWPORT_START 0x087d 3235 #define regHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 3236 #define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x087e 3237 #define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 3238 #define regHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x087f 3239 #define regHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 3240 #define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0880 3241 #define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 3242 #define regHUBP3_DCSURF_SEC_VIEWPORT_START 0x0881 3243 #define regHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 3244 #define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x0882 3245 #define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 3246 #define regHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x0883 3247 #define regHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 3248 #define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0884 3249 #define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 3250 #define regHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x0885 3251 #define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 3252 #define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x0886 3253 #define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 3254 #define regHUBP3_DCHUBP_CNTL 0x0887 3255 #define regHUBP3_DCHUBP_CNTL_BASE_IDX 2 3256 #define regHUBP3_HUBP_CLK_CNTL 0x0888 3257 #define regHUBP3_HUBP_CLK_CNTL_BASE_IDX 2 3258 #define regHUBP3_DCHUBP_VMPG_CONFIG 0x0889 3259 #define regHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2 3260 #define regHUBP3_DCHUBP_MALL_CONFIG 0x088a 3261 #define regHUBP3_DCHUBP_MALL_CONFIG_BASE_IDX 2 3262 #define regHUBP3_DCHUBP_MALL_SUB_VP 0x088b 3263 #define regHUBP3_DCHUBP_MALL_SUB_VP_BASE_IDX 2 3264 #define regHUBP3_HUBPREQ_DEBUG_DB 0x088c 3265 #define regHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2 3266 #define regHUBP3_HUBPREQ_DEBUG 0x088d 3267 #define regHUBP3_HUBPREQ_DEBUG_BASE_IDX 2 3268 #define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x0891 3269 #define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 3270 #define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0892 3271 #define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 3272 #define regHUBP3_HUBP_MALL_STATUS 0x0893 3273 #define regHUBP3_HUBP_MALL_STATUS_BASE_IDX 2 3274 3275 3276 // addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec 3277 // base address: 0xa50 3278 #define regHUBPREQ3_DCSURF_SURFACE_PITCH 0x089b 3279 #define regHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2 3280 #define regHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x089c 3281 #define regHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 3282 #define regHUBPREQ3_VMID_SETTINGS_0 0x089d 3283 #define regHUBPREQ3_VMID_SETTINGS_0_BASE_IDX 2 3284 #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x089e 3285 #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 3286 #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x089f 3287 #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3288 #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x08a0 3289 #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 3290 #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x08a1 3291 #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3292 #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x08a2 3293 #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 3294 #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x08a3 3295 #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3296 #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x08a4 3297 #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 3298 #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x08a5 3299 #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3300 #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x08a6 3301 #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 3302 #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x08a7 3303 #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3304 #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x08a8 3305 #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3306 #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x08a9 3307 #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3308 #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x08aa 3309 #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 3310 #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x08ab 3311 #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3312 #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x08ac 3313 #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3314 #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x08ad 3315 #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3316 #define regHUBPREQ3_DCSURF_SURFACE_CONTROL 0x08ae 3317 #define regHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2 3318 #define regHUBPREQ3_DCSURF_FLIP_CONTROL 0x08af 3319 #define regHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2 3320 #define regHUBPREQ3_DCSURF_FLIP_CONTROL2 0x08b0 3321 #define regHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2 3322 #define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x08b3 3323 #define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 3324 #define regHUBPREQ3_DCSURF_SURFACE_INUSE 0x08b4 3325 #define regHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2 3326 #define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x08b5 3327 #define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 3328 #define regHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x08b6 3329 #define regHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 3330 #define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x08b7 3331 #define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 3332 #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x08b8 3333 #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 3334 #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x08b9 3335 #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 3336 #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x08ba 3337 #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 3338 #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x08bb 3339 #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 3340 #define regHUBPREQ3_DCN_EXPANSION_MODE 0x08bc 3341 #define regHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2 3342 #define regHUBPREQ3_DCN_TTU_QOS_WM 0x08bd 3343 #define regHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2 3344 #define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x08be 3345 #define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 3346 #define regHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x08bf 3347 #define regHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 3348 #define regHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x08c0 3349 #define regHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 3350 #define regHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x08c1 3351 #define regHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 3352 #define regHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x08c2 3353 #define regHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 3354 #define regHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x08c3 3355 #define regHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 3356 #define regHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x08c4 3357 #define regHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 3358 #define regHUBPREQ3_DCN_CUR1_TTU_CNTL0 0x08c5 3359 #define regHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 3360 #define regHUBPREQ3_DCN_CUR1_TTU_CNTL1 0x08c6 3361 #define regHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 3362 #define regHUBPREQ3_DCN_DMDATA_VM_CNTL 0x08c7 3363 #define regHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX 2 3364 #define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x08c8 3365 #define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 3366 #define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08c9 3367 #define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 3368 #define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x08d6 3369 #define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 3370 #define regHUBPREQ3_BLANK_OFFSET_0 0x08d7 3371 #define regHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2 3372 #define regHUBPREQ3_BLANK_OFFSET_1 0x08d8 3373 #define regHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2 3374 #define regHUBPREQ3_DST_DIMENSIONS 0x08d9 3375 #define regHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2 3376 #define regHUBPREQ3_DST_AFTER_SCALER 0x08da 3377 #define regHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2 3378 #define regHUBPREQ3_PREFETCH_SETTINGS 0x08db 3379 #define regHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX 2 3380 #define regHUBPREQ3_PREFETCH_SETTINGS_C 0x08dc 3381 #define regHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX 2 3382 #define regHUBPREQ3_VBLANK_PARAMETERS_0 0x08dd 3383 #define regHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2 3384 #define regHUBPREQ3_VBLANK_PARAMETERS_1 0x08de 3385 #define regHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2 3386 #define regHUBPREQ3_VBLANK_PARAMETERS_2 0x08df 3387 #define regHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2 3388 #define regHUBPREQ3_VBLANK_PARAMETERS_3 0x08e0 3389 #define regHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2 3390 #define regHUBPREQ3_VBLANK_PARAMETERS_4 0x08e1 3391 #define regHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2 3392 #define regHUBPREQ3_FLIP_PARAMETERS_0 0x08e2 3393 #define regHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX 2 3394 #define regHUBPREQ3_FLIP_PARAMETERS_1 0x08e3 3395 #define regHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX 2 3396 #define regHUBPREQ3_FLIP_PARAMETERS_2 0x08e4 3397 #define regHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX 2 3398 #define regHUBPREQ3_NOM_PARAMETERS_0 0x08e5 3399 #define regHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2 3400 #define regHUBPREQ3_NOM_PARAMETERS_1 0x08e6 3401 #define regHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2 3402 #define regHUBPREQ3_NOM_PARAMETERS_2 0x08e7 3403 #define regHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2 3404 #define regHUBPREQ3_NOM_PARAMETERS_3 0x08e8 3405 #define regHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2 3406 #define regHUBPREQ3_NOM_PARAMETERS_4 0x08e9 3407 #define regHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2 3408 #define regHUBPREQ3_NOM_PARAMETERS_5 0x08ea 3409 #define regHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2 3410 #define regHUBPREQ3_NOM_PARAMETERS_6 0x08eb 3411 #define regHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2 3412 #define regHUBPREQ3_NOM_PARAMETERS_7 0x08ec 3413 #define regHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2 3414 #define regHUBPREQ3_PER_LINE_DELIVERY_PRE 0x08ed 3415 #define regHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2 3416 #define regHUBPREQ3_PER_LINE_DELIVERY 0x08ee 3417 #define regHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2 3418 #define regHUBPREQ3_CURSOR_SETTINGS 0x08ef 3419 #define regHUBPREQ3_CURSOR_SETTINGS_BASE_IDX 2 3420 #define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x08f0 3421 #define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 3422 #define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT 0x08f1 3423 #define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 3424 #define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x08f2 3425 #define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 3426 #define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x08f3 3427 #define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 3428 #define regHUBPREQ3_VBLANK_PARAMETERS_5 0x08f6 3429 #define regHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX 2 3430 #define regHUBPREQ3_VBLANK_PARAMETERS_6 0x08f7 3431 #define regHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX 2 3432 #define regHUBPREQ3_FLIP_PARAMETERS_3 0x08f8 3433 #define regHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX 2 3434 #define regHUBPREQ3_FLIP_PARAMETERS_4 0x08f9 3435 #define regHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX 2 3436 #define regHUBPREQ3_FLIP_PARAMETERS_5 0x08fa 3437 #define regHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX 2 3438 #define regHUBPREQ3_FLIP_PARAMETERS_6 0x08fb 3439 #define regHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX 2 3440 #define regHUBPREQ3_UCLK_PSTATE_FORCE 0x08fc 3441 #define regHUBPREQ3_UCLK_PSTATE_FORCE_BASE_IDX 2 3442 #define regHUBPREQ3_HUBPREQ_STATUS_REG0 0x08fd 3443 #define regHUBPREQ3_HUBPREQ_STATUS_REG0_BASE_IDX 2 3444 #define regHUBPREQ3_HUBPREQ_STATUS_REG1 0x08fe 3445 #define regHUBPREQ3_HUBPREQ_STATUS_REG1_BASE_IDX 2 3446 #define regHUBPREQ3_HUBPREQ_STATUS_REG2 0x08ff 3447 #define regHUBPREQ3_HUBPREQ_STATUS_REG2_BASE_IDX 2 3448 3449 3450 // addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec 3451 // base address: 0xa50 3452 #define regHUBPRET3_HUBPRET_CONTROL 0x0900 3453 #define regHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2 3454 #define regHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x0901 3455 #define regHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 3456 #define regHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x0902 3457 #define regHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 3458 #define regHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x0903 3459 #define regHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 3460 #define regHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0904 3461 #define regHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 3462 #define regHUBPRET3_HUBPRET_READ_LINE0 0x0905 3463 #define regHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2 3464 #define regHUBPRET3_HUBPRET_READ_LINE1 0x0906 3465 #define regHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2 3466 #define regHUBPRET3_HUBPRET_INTERRUPT 0x0907 3467 #define regHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2 3468 #define regHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0908 3469 #define regHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 3470 #define regHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0909 3471 #define regHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 3472 3473 3474 // addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec 3475 // base address: 0xa50 3476 #define regCURSOR0_3_CURSOR_CONTROL 0x090c 3477 #define regCURSOR0_3_CURSOR_CONTROL_BASE_IDX 2 3478 #define regCURSOR0_3_CURSOR_SURFACE_ADDRESS 0x090d 3479 #define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 3480 #define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH 0x090e 3481 #define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3482 #define regCURSOR0_3_CURSOR_SIZE 0x090f 3483 #define regCURSOR0_3_CURSOR_SIZE_BASE_IDX 2 3484 #define regCURSOR0_3_CURSOR_POSITION 0x0910 3485 #define regCURSOR0_3_CURSOR_POSITION_BASE_IDX 2 3486 #define regCURSOR0_3_CURSOR_HOT_SPOT 0x0911 3487 #define regCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX 2 3488 #define regCURSOR0_3_CURSOR_STEREO_CONTROL 0x0912 3489 #define regCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX 2 3490 #define regCURSOR0_3_CURSOR_DST_OFFSET 0x0913 3491 #define regCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX 2 3492 #define regCURSOR0_3_CURSOR_MEM_PWR_CTRL 0x0914 3493 #define regCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 3494 #define regCURSOR0_3_CURSOR_MEM_PWR_STATUS 0x0915 3495 #define regCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 3496 #define regCURSOR0_3_DMDATA_ADDRESS_HIGH 0x0916 3497 #define regCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX 2 3498 #define regCURSOR0_3_DMDATA_ADDRESS_LOW 0x0917 3499 #define regCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX 2 3500 #define regCURSOR0_3_DMDATA_CNTL 0x0918 3501 #define regCURSOR0_3_DMDATA_CNTL_BASE_IDX 2 3502 #define regCURSOR0_3_DMDATA_QOS_CNTL 0x0919 3503 #define regCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX 2 3504 #define regCURSOR0_3_DMDATA_STATUS 0x091a 3505 #define regCURSOR0_3_DMDATA_STATUS_BASE_IDX 2 3506 #define regCURSOR0_3_DMDATA_SW_CNTL 0x091b 3507 #define regCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX 2 3508 #define regCURSOR0_3_DMDATA_SW_DATA 0x091c 3509 #define regCURSOR0_3_DMDATA_SW_DATA_BASE_IDX 2 3510 3511 3512 // addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 3513 // base address: 0x24c4 3514 #define regDC_PERFMON10_PERFCOUNTER_CNTL 0x0931 3515 #define regDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2 3516 #define regDC_PERFMON10_PERFCOUNTER_CNTL2 0x0932 3517 #define regDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2 3518 #define regDC_PERFMON10_PERFCOUNTER_STATE 0x0933 3519 #define regDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2 3520 #define regDC_PERFMON10_PERFMON_CNTL 0x0934 3521 #define regDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2 3522 #define regDC_PERFMON10_PERFMON_CNTL2 0x0935 3523 #define regDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2 3524 #define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x0936 3525 #define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 3526 #define regDC_PERFMON10_PERFMON_CVALUE_LOW 0x0937 3527 #define regDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2 3528 #define regDC_PERFMON10_PERFMON_HI 0x0938 3529 #define regDC_PERFMON10_PERFMON_HI_BASE_IDX 2 3530 #define regDC_PERFMON10_PERFMON_LOW 0x0939 3531 #define regDC_PERFMON10_PERFMON_LOW_BASE_IDX 2 3532 3533 3534 // addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec 3535 // base address: 0x0 3536 #define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0ccf 3537 #define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 3538 #define regCNVC_CFG0_FORMAT_CONTROL 0x0cd0 3539 #define regCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2 3540 #define regCNVC_CFG0_FCNV_FP_BIAS_R 0x0cd1 3541 #define regCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX 2 3542 #define regCNVC_CFG0_FCNV_FP_BIAS_G 0x0cd2 3543 #define regCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX 2 3544 #define regCNVC_CFG0_FCNV_FP_BIAS_B 0x0cd3 3545 #define regCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX 2 3546 #define regCNVC_CFG0_FCNV_FP_SCALE_R 0x0cd4 3547 #define regCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX 2 3548 #define regCNVC_CFG0_FCNV_FP_SCALE_G 0x0cd5 3549 #define regCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX 2 3550 #define regCNVC_CFG0_FCNV_FP_SCALE_B 0x0cd6 3551 #define regCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX 2 3552 #define regCNVC_CFG0_COLOR_KEYER_CONTROL 0x0cd7 3553 #define regCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2 3554 #define regCNVC_CFG0_COLOR_KEYER_ALPHA 0x0cd8 3555 #define regCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2 3556 #define regCNVC_CFG0_COLOR_KEYER_RED 0x0cd9 3557 #define regCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2 3558 #define regCNVC_CFG0_COLOR_KEYER_GREEN 0x0cda 3559 #define regCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2 3560 #define regCNVC_CFG0_COLOR_KEYER_BLUE 0x0cdb 3561 #define regCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2 3562 #define regCNVC_CFG0_ALPHA_2BIT_LUT 0x0cdd 3563 #define regCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX 2 3564 #define regCNVC_CFG0_PRE_DEALPHA 0x0cde 3565 #define regCNVC_CFG0_PRE_DEALPHA_BASE_IDX 2 3566 #define regCNVC_CFG0_PRE_CSC_MODE 0x0cdf 3567 #define regCNVC_CFG0_PRE_CSC_MODE_BASE_IDX 2 3568 #define regCNVC_CFG0_PRE_CSC_C11_C12 0x0ce0 3569 #define regCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX 2 3570 #define regCNVC_CFG0_PRE_CSC_C13_C14 0x0ce1 3571 #define regCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX 2 3572 #define regCNVC_CFG0_PRE_CSC_C21_C22 0x0ce2 3573 #define regCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX 2 3574 #define regCNVC_CFG0_PRE_CSC_C23_C24 0x0ce3 3575 #define regCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX 2 3576 #define regCNVC_CFG0_PRE_CSC_C31_C32 0x0ce4 3577 #define regCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX 2 3578 #define regCNVC_CFG0_PRE_CSC_C33_C34 0x0ce5 3579 #define regCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX 2 3580 #define regCNVC_CFG0_PRE_CSC_B_C11_C12 0x0ce6 3581 #define regCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX 2 3582 #define regCNVC_CFG0_PRE_CSC_B_C13_C14 0x0ce7 3583 #define regCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX 2 3584 #define regCNVC_CFG0_PRE_CSC_B_C21_C22 0x0ce8 3585 #define regCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX 2 3586 #define regCNVC_CFG0_PRE_CSC_B_C23_C24 0x0ce9 3587 #define regCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX 2 3588 #define regCNVC_CFG0_PRE_CSC_B_C31_C32 0x0cea 3589 #define regCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX 2 3590 #define regCNVC_CFG0_PRE_CSC_B_C33_C34 0x0ceb 3591 #define regCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX 2 3592 #define regCNVC_CFG0_CNVC_COEF_FORMAT 0x0cec 3593 #define regCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX 2 3594 #define regCNVC_CFG0_PRE_DEGAM 0x0ced 3595 #define regCNVC_CFG0_PRE_DEGAM_BASE_IDX 2 3596 #define regCNVC_CFG0_PRE_REALPHA 0x0cee 3597 #define regCNVC_CFG0_PRE_REALPHA_BASE_IDX 2 3598 3599 3600 // addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec 3601 // base address: 0x0 3602 #define regCNVC_CUR0_CURSOR0_CONTROL 0x0cf1 3603 #define regCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2 3604 #define regCNVC_CUR0_CURSOR0_COLOR0 0x0cf2 3605 #define regCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2 3606 #define regCNVC_CUR0_CURSOR0_COLOR1 0x0cf3 3607 #define regCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2 3608 #define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0cf4 3609 #define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 3610 3611 3612 // addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec 3613 // base address: 0x0 3614 #define regDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0cf9 3615 #define regDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 3616 #define regDSCL0_SCL_COEF_RAM_TAP_DATA 0x0cfa 3617 #define regDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 3618 #define regDSCL0_SCL_MODE 0x0cfb 3619 #define regDSCL0_SCL_MODE_BASE_IDX 2 3620 #define regDSCL0_SCL_TAP_CONTROL 0x0cfc 3621 #define regDSCL0_SCL_TAP_CONTROL_BASE_IDX 2 3622 #define regDSCL0_DSCL_CONTROL 0x0cfd 3623 #define regDSCL0_DSCL_CONTROL_BASE_IDX 2 3624 #define regDSCL0_DSCL_2TAP_CONTROL 0x0cfe 3625 #define regDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2 3626 #define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0cff 3627 #define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 3628 #define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0d00 3629 #define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 3630 #define regDSCL0_SCL_HORZ_FILTER_INIT 0x0d01 3631 #define regDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2 3632 #define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0d02 3633 #define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 3634 #define regDSCL0_SCL_HORZ_FILTER_INIT_C 0x0d03 3635 #define regDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 3636 #define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0d04 3637 #define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 3638 #define regDSCL0_SCL_VERT_FILTER_INIT 0x0d05 3639 #define regDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2 3640 #define regDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0d06 3641 #define regDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 3642 #define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0d07 3643 #define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 3644 #define regDSCL0_SCL_VERT_FILTER_INIT_C 0x0d08 3645 #define regDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 3646 #define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0d09 3647 #define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 3648 #define regDSCL0_SCL_BLACK_COLOR 0x0d0a 3649 #define regDSCL0_SCL_BLACK_COLOR_BASE_IDX 2 3650 #define regDSCL0_DSCL_UPDATE 0x0d0b 3651 #define regDSCL0_DSCL_UPDATE_BASE_IDX 2 3652 #define regDSCL0_DSCL_AUTOCAL 0x0d0c 3653 #define regDSCL0_DSCL_AUTOCAL_BASE_IDX 2 3654 #define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0d0d 3655 #define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 3656 #define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0d0e 3657 #define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 3658 #define regDSCL0_OTG_H_BLANK 0x0d0f 3659 #define regDSCL0_OTG_H_BLANK_BASE_IDX 2 3660 #define regDSCL0_OTG_V_BLANK 0x0d10 3661 #define regDSCL0_OTG_V_BLANK_BASE_IDX 2 3662 #define regDSCL0_RECOUT_START 0x0d11 3663 #define regDSCL0_RECOUT_START_BASE_IDX 2 3664 #define regDSCL0_RECOUT_SIZE 0x0d12 3665 #define regDSCL0_RECOUT_SIZE_BASE_IDX 2 3666 #define regDSCL0_MPC_SIZE 0x0d13 3667 #define regDSCL0_MPC_SIZE_BASE_IDX 2 3668 #define regDSCL0_LB_DATA_FORMAT 0x0d14 3669 #define regDSCL0_LB_DATA_FORMAT_BASE_IDX 2 3670 #define regDSCL0_LB_MEMORY_CTRL 0x0d15 3671 #define regDSCL0_LB_MEMORY_CTRL_BASE_IDX 2 3672 #define regDSCL0_LB_V_COUNTER 0x0d16 3673 #define regDSCL0_LB_V_COUNTER_BASE_IDX 2 3674 #define regDSCL0_DSCL_MEM_PWR_CTRL 0x0d17 3675 #define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2 3676 #define regDSCL0_DSCL_MEM_PWR_STATUS 0x0d18 3677 #define regDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2 3678 #define regDSCL0_OBUF_CONTROL 0x0d19 3679 #define regDSCL0_OBUF_CONTROL_BASE_IDX 2 3680 #define regDSCL0_OBUF_MEM_PWR_CTRL 0x0d1a 3681 #define regDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2 3682 3683 3684 // addressBlock: dce_dc_dpp0_dispdec_cm_dispdec 3685 // base address: 0x0 3686 #define regCM0_CM_CONTROL 0x0d20 3687 #define regCM0_CM_CONTROL_BASE_IDX 2 3688 #define regCM0_CM_POST_CSC_CONTROL 0x0d21 3689 #define regCM0_CM_POST_CSC_CONTROL_BASE_IDX 2 3690 #define regCM0_CM_POST_CSC_C11_C12 0x0d22 3691 #define regCM0_CM_POST_CSC_C11_C12_BASE_IDX 2 3692 #define regCM0_CM_POST_CSC_C13_C14 0x0d23 3693 #define regCM0_CM_POST_CSC_C13_C14_BASE_IDX 2 3694 #define regCM0_CM_POST_CSC_C21_C22 0x0d24 3695 #define regCM0_CM_POST_CSC_C21_C22_BASE_IDX 2 3696 #define regCM0_CM_POST_CSC_C23_C24 0x0d25 3697 #define regCM0_CM_POST_CSC_C23_C24_BASE_IDX 2 3698 #define regCM0_CM_POST_CSC_C31_C32 0x0d26 3699 #define regCM0_CM_POST_CSC_C31_C32_BASE_IDX 2 3700 #define regCM0_CM_POST_CSC_C33_C34 0x0d27 3701 #define regCM0_CM_POST_CSC_C33_C34_BASE_IDX 2 3702 #define regCM0_CM_POST_CSC_B_C11_C12 0x0d28 3703 #define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX 2 3704 #define regCM0_CM_POST_CSC_B_C13_C14 0x0d29 3705 #define regCM0_CM_POST_CSC_B_C13_C14_BASE_IDX 2 3706 #define regCM0_CM_POST_CSC_B_C21_C22 0x0d2a 3707 #define regCM0_CM_POST_CSC_B_C21_C22_BASE_IDX 2 3708 #define regCM0_CM_POST_CSC_B_C23_C24 0x0d2b 3709 #define regCM0_CM_POST_CSC_B_C23_C24_BASE_IDX 2 3710 #define regCM0_CM_POST_CSC_B_C31_C32 0x0d2c 3711 #define regCM0_CM_POST_CSC_B_C31_C32_BASE_IDX 2 3712 #define regCM0_CM_POST_CSC_B_C33_C34 0x0d2d 3713 #define regCM0_CM_POST_CSC_B_C33_C34_BASE_IDX 2 3714 #define regCM0_CM_GAMUT_REMAP_CONTROL 0x0d2e 3715 #define regCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 3716 #define regCM0_CM_GAMUT_REMAP_C11_C12 0x0d2f 3717 #define regCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 3718 #define regCM0_CM_GAMUT_REMAP_C13_C14 0x0d30 3719 #define regCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 3720 #define regCM0_CM_GAMUT_REMAP_C21_C22 0x0d31 3721 #define regCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 3722 #define regCM0_CM_GAMUT_REMAP_C23_C24 0x0d32 3723 #define regCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 3724 #define regCM0_CM_GAMUT_REMAP_C31_C32 0x0d33 3725 #define regCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 3726 #define regCM0_CM_GAMUT_REMAP_C33_C34 0x0d34 3727 #define regCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 3728 #define regCM0_CM_GAMUT_REMAP_B_C11_C12 0x0d35 3729 #define regCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 3730 #define regCM0_CM_GAMUT_REMAP_B_C13_C14 0x0d36 3731 #define regCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 3732 #define regCM0_CM_GAMUT_REMAP_B_C21_C22 0x0d37 3733 #define regCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 3734 #define regCM0_CM_GAMUT_REMAP_B_C23_C24 0x0d38 3735 #define regCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 3736 #define regCM0_CM_GAMUT_REMAP_B_C31_C32 0x0d39 3737 #define regCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 3738 #define regCM0_CM_GAMUT_REMAP_B_C33_C34 0x0d3a 3739 #define regCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 3740 #define regCM0_CM_BIAS_CR_R 0x0d3b 3741 #define regCM0_CM_BIAS_CR_R_BASE_IDX 2 3742 #define regCM0_CM_BIAS_Y_G_CB_B 0x0d3c 3743 #define regCM0_CM_BIAS_Y_G_CB_B_BASE_IDX 2 3744 #define regCM0_CM_GAMCOR_CONTROL 0x0d3d 3745 #define regCM0_CM_GAMCOR_CONTROL_BASE_IDX 2 3746 #define regCM0_CM_GAMCOR_LUT_INDEX 0x0d3e 3747 #define regCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 3748 #define regCM0_CM_GAMCOR_LUT_DATA 0x0d3f 3749 #define regCM0_CM_GAMCOR_LUT_DATA_BASE_IDX 2 3750 #define regCM0_CM_GAMCOR_LUT_CONTROL 0x0d40 3751 #define regCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 3752 #define regCM0_CM_GAMCOR_RAMA_START_CNTL_B 0x0d41 3753 #define regCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 3754 #define regCM0_CM_GAMCOR_RAMA_START_CNTL_G 0x0d42 3755 #define regCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 3756 #define regCM0_CM_GAMCOR_RAMA_START_CNTL_R 0x0d43 3757 #define regCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 3758 #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0d44 3759 #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 3760 #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0d45 3761 #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 3762 #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0d46 3763 #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 3764 #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0d47 3765 #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 3766 #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0d48 3767 #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 3768 #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0d49 3769 #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 3770 #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B 0x0d4a 3771 #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 3772 #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B 0x0d4b 3773 #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 3774 #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G 0x0d4c 3775 #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 3776 #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G 0x0d4d 3777 #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 3778 #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R 0x0d4e 3779 #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 3780 #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R 0x0d4f 3781 #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 3782 #define regCM0_CM_GAMCOR_RAMA_OFFSET_B 0x0d50 3783 #define regCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 3784 #define regCM0_CM_GAMCOR_RAMA_OFFSET_G 0x0d51 3785 #define regCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 3786 #define regCM0_CM_GAMCOR_RAMA_OFFSET_R 0x0d52 3787 #define regCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 3788 #define regCM0_CM_GAMCOR_RAMA_REGION_0_1 0x0d53 3789 #define regCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 3790 #define regCM0_CM_GAMCOR_RAMA_REGION_2_3 0x0d54 3791 #define regCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 3792 #define regCM0_CM_GAMCOR_RAMA_REGION_4_5 0x0d55 3793 #define regCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 3794 #define regCM0_CM_GAMCOR_RAMA_REGION_6_7 0x0d56 3795 #define regCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 3796 #define regCM0_CM_GAMCOR_RAMA_REGION_8_9 0x0d57 3797 #define regCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 3798 #define regCM0_CM_GAMCOR_RAMA_REGION_10_11 0x0d58 3799 #define regCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 3800 #define regCM0_CM_GAMCOR_RAMA_REGION_12_13 0x0d59 3801 #define regCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 3802 #define regCM0_CM_GAMCOR_RAMA_REGION_14_15 0x0d5a 3803 #define regCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 3804 #define regCM0_CM_GAMCOR_RAMA_REGION_16_17 0x0d5b 3805 #define regCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 3806 #define regCM0_CM_GAMCOR_RAMA_REGION_18_19 0x0d5c 3807 #define regCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 3808 #define regCM0_CM_GAMCOR_RAMA_REGION_20_21 0x0d5d 3809 #define regCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 3810 #define regCM0_CM_GAMCOR_RAMA_REGION_22_23 0x0d5e 3811 #define regCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 3812 #define regCM0_CM_GAMCOR_RAMA_REGION_24_25 0x0d5f 3813 #define regCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 3814 #define regCM0_CM_GAMCOR_RAMA_REGION_26_27 0x0d60 3815 #define regCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 3816 #define regCM0_CM_GAMCOR_RAMA_REGION_28_29 0x0d61 3817 #define regCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 3818 #define regCM0_CM_GAMCOR_RAMA_REGION_30_31 0x0d62 3819 #define regCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 3820 #define regCM0_CM_GAMCOR_RAMA_REGION_32_33 0x0d63 3821 #define regCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 3822 #define regCM0_CM_GAMCOR_RAMB_START_CNTL_B 0x0d64 3823 #define regCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 3824 #define regCM0_CM_GAMCOR_RAMB_START_CNTL_G 0x0d65 3825 #define regCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 3826 #define regCM0_CM_GAMCOR_RAMB_START_CNTL_R 0x0d66 3827 #define regCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 3828 #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0d67 3829 #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 3830 #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0d68 3831 #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 3832 #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0d69 3833 #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 3834 #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0d6a 3835 #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 3836 #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0d6b 3837 #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 3838 #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0d6c 3839 #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 3840 #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B 0x0d6d 3841 #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 3842 #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B 0x0d6e 3843 #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 3844 #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G 0x0d6f 3845 #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 3846 #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G 0x0d70 3847 #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 3848 #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R 0x0d71 3849 #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 3850 #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R 0x0d72 3851 #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 3852 #define regCM0_CM_GAMCOR_RAMB_OFFSET_B 0x0d73 3853 #define regCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 3854 #define regCM0_CM_GAMCOR_RAMB_OFFSET_G 0x0d74 3855 #define regCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 3856 #define regCM0_CM_GAMCOR_RAMB_OFFSET_R 0x0d75 3857 #define regCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 3858 #define regCM0_CM_GAMCOR_RAMB_REGION_0_1 0x0d76 3859 #define regCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 3860 #define regCM0_CM_GAMCOR_RAMB_REGION_2_3 0x0d77 3861 #define regCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 3862 #define regCM0_CM_GAMCOR_RAMB_REGION_4_5 0x0d78 3863 #define regCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 3864 #define regCM0_CM_GAMCOR_RAMB_REGION_6_7 0x0d79 3865 #define regCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 3866 #define regCM0_CM_GAMCOR_RAMB_REGION_8_9 0x0d7a 3867 #define regCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 3868 #define regCM0_CM_GAMCOR_RAMB_REGION_10_11 0x0d7b 3869 #define regCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 3870 #define regCM0_CM_GAMCOR_RAMB_REGION_12_13 0x0d7c 3871 #define regCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 3872 #define regCM0_CM_GAMCOR_RAMB_REGION_14_15 0x0d7d 3873 #define regCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 3874 #define regCM0_CM_GAMCOR_RAMB_REGION_16_17 0x0d7e 3875 #define regCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 3876 #define regCM0_CM_GAMCOR_RAMB_REGION_18_19 0x0d7f 3877 #define regCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 3878 #define regCM0_CM_GAMCOR_RAMB_REGION_20_21 0x0d80 3879 #define regCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 3880 #define regCM0_CM_GAMCOR_RAMB_REGION_22_23 0x0d81 3881 #define regCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 3882 #define regCM0_CM_GAMCOR_RAMB_REGION_24_25 0x0d82 3883 #define regCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 3884 #define regCM0_CM_GAMCOR_RAMB_REGION_26_27 0x0d83 3885 #define regCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 3886 #define regCM0_CM_GAMCOR_RAMB_REGION_28_29 0x0d84 3887 #define regCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 3888 #define regCM0_CM_GAMCOR_RAMB_REGION_30_31 0x0d85 3889 #define regCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 3890 #define regCM0_CM_GAMCOR_RAMB_REGION_32_33 0x0d86 3891 #define regCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 3892 #define regCM0_CM_HDR_MULT_COEF 0x0d87 3893 #define regCM0_CM_HDR_MULT_COEF_BASE_IDX 2 3894 #define regCM0_CM_MEM_PWR_CTRL 0x0d88 3895 #define regCM0_CM_MEM_PWR_CTRL_BASE_IDX 2 3896 #define regCM0_CM_MEM_PWR_STATUS 0x0d89 3897 #define regCM0_CM_MEM_PWR_STATUS_BASE_IDX 2 3898 #define regCM0_CM_DEALPHA 0x0d8b 3899 #define regCM0_CM_DEALPHA_BASE_IDX 2 3900 #define regCM0_CM_COEF_FORMAT 0x0d8c 3901 #define regCM0_CM_COEF_FORMAT_BASE_IDX 2 3902 #define regCM0_CM_TEST_DEBUG_INDEX 0x0d8d 3903 #define regCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2 3904 #define regCM0_CM_TEST_DEBUG_DATA 0x0d8e 3905 #define regCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2 3906 #define regCM0_DPP_CRC_VAL_R 0x0d8f 3907 #define regCM0_DPP_CRC_VAL_R_BASE_IDX 2 3908 #define regCM0_DPP_CRC_VAL_G 0x0d90 3909 #define regCM0_DPP_CRC_VAL_G_BASE_IDX 2 3910 #define regCM0_DPP_CRC_VAL_B 0x0d91 3911 #define regCM0_DPP_CRC_VAL_B_BASE_IDX 2 3912 #define regCM0_DPP_CRC_VAL_A 0x0d92 3913 #define regCM0_DPP_CRC_VAL_A_BASE_IDX 2 3914 3915 3916 // addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec 3917 // base address: 0x0 3918 #define regDPP_TOP0_DPP_CONTROL 0x0cc5 3919 #define regDPP_TOP0_DPP_CONTROL_BASE_IDX 2 3920 #define regDPP_TOP0_DPP_SOFT_RESET 0x0cc6 3921 #define regDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2 3922 #define regDPP_TOP0_DPP_CRC_CTRL 0x0cc9 3923 #define regDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2 3924 #define regDPP_TOP0_HOST_READ_CONTROL 0x0cca 3925 #define regDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2 3926 3927 3928 // addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 3929 // base address: 0x3890 3930 #define regDC_PERFMON11_PERFCOUNTER_CNTL 0x0e24 3931 #define regDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2 3932 #define regDC_PERFMON11_PERFCOUNTER_CNTL2 0x0e25 3933 #define regDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2 3934 #define regDC_PERFMON11_PERFCOUNTER_STATE 0x0e26 3935 #define regDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2 3936 #define regDC_PERFMON11_PERFMON_CNTL 0x0e27 3937 #define regDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2 3938 #define regDC_PERFMON11_PERFMON_CNTL2 0x0e28 3939 #define regDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2 3940 #define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x0e29 3941 #define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 3942 #define regDC_PERFMON11_PERFMON_CVALUE_LOW 0x0e2a 3943 #define regDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2 3944 #define regDC_PERFMON11_PERFMON_HI 0x0e2b 3945 #define regDC_PERFMON11_PERFMON_HI_BASE_IDX 2 3946 #define regDC_PERFMON11_PERFMON_LOW 0x0e2c 3947 #define regDC_PERFMON11_PERFMON_LOW_BASE_IDX 2 3948 3949 3950 // addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec 3951 // base address: 0x5ac 3952 #define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0e3a 3953 #define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 3954 #define regCNVC_CFG1_FORMAT_CONTROL 0x0e3b 3955 #define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2 3956 #define regCNVC_CFG1_FCNV_FP_BIAS_R 0x0e3c 3957 #define regCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX 2 3958 #define regCNVC_CFG1_FCNV_FP_BIAS_G 0x0e3d 3959 #define regCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX 2 3960 #define regCNVC_CFG1_FCNV_FP_BIAS_B 0x0e3e 3961 #define regCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX 2 3962 #define regCNVC_CFG1_FCNV_FP_SCALE_R 0x0e3f 3963 #define regCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX 2 3964 #define regCNVC_CFG1_FCNV_FP_SCALE_G 0x0e40 3965 #define regCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX 2 3966 #define regCNVC_CFG1_FCNV_FP_SCALE_B 0x0e41 3967 #define regCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX 2 3968 #define regCNVC_CFG1_COLOR_KEYER_CONTROL 0x0e42 3969 #define regCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2 3970 #define regCNVC_CFG1_COLOR_KEYER_ALPHA 0x0e43 3971 #define regCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2 3972 #define regCNVC_CFG1_COLOR_KEYER_RED 0x0e44 3973 #define regCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2 3974 #define regCNVC_CFG1_COLOR_KEYER_GREEN 0x0e45 3975 #define regCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2 3976 #define regCNVC_CFG1_COLOR_KEYER_BLUE 0x0e46 3977 #define regCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2 3978 #define regCNVC_CFG1_ALPHA_2BIT_LUT 0x0e48 3979 #define regCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX 2 3980 #define regCNVC_CFG1_PRE_DEALPHA 0x0e49 3981 #define regCNVC_CFG1_PRE_DEALPHA_BASE_IDX 2 3982 #define regCNVC_CFG1_PRE_CSC_MODE 0x0e4a 3983 #define regCNVC_CFG1_PRE_CSC_MODE_BASE_IDX 2 3984 #define regCNVC_CFG1_PRE_CSC_C11_C12 0x0e4b 3985 #define regCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX 2 3986 #define regCNVC_CFG1_PRE_CSC_C13_C14 0x0e4c 3987 #define regCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX 2 3988 #define regCNVC_CFG1_PRE_CSC_C21_C22 0x0e4d 3989 #define regCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX 2 3990 #define regCNVC_CFG1_PRE_CSC_C23_C24 0x0e4e 3991 #define regCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX 2 3992 #define regCNVC_CFG1_PRE_CSC_C31_C32 0x0e4f 3993 #define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX 2 3994 #define regCNVC_CFG1_PRE_CSC_C33_C34 0x0e50 3995 #define regCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX 2 3996 #define regCNVC_CFG1_PRE_CSC_B_C11_C12 0x0e51 3997 #define regCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX 2 3998 #define regCNVC_CFG1_PRE_CSC_B_C13_C14 0x0e52 3999 #define regCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX 2 4000 #define regCNVC_CFG1_PRE_CSC_B_C21_C22 0x0e53 4001 #define regCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX 2 4002 #define regCNVC_CFG1_PRE_CSC_B_C23_C24 0x0e54 4003 #define regCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX 2 4004 #define regCNVC_CFG1_PRE_CSC_B_C31_C32 0x0e55 4005 #define regCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX 2 4006 #define regCNVC_CFG1_PRE_CSC_B_C33_C34 0x0e56 4007 #define regCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX 2 4008 #define regCNVC_CFG1_CNVC_COEF_FORMAT 0x0e57 4009 #define regCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX 2 4010 #define regCNVC_CFG1_PRE_DEGAM 0x0e58 4011 #define regCNVC_CFG1_PRE_DEGAM_BASE_IDX 2 4012 #define regCNVC_CFG1_PRE_REALPHA 0x0e59 4013 #define regCNVC_CFG1_PRE_REALPHA_BASE_IDX 2 4014 4015 4016 // addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec 4017 // base address: 0x5ac 4018 #define regCNVC_CUR1_CURSOR0_CONTROL 0x0e5c 4019 #define regCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2 4020 #define regCNVC_CUR1_CURSOR0_COLOR0 0x0e5d 4021 #define regCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2 4022 #define regCNVC_CUR1_CURSOR0_COLOR1 0x0e5e 4023 #define regCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2 4024 #define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0e5f 4025 #define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 4026 4027 4028 // addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec 4029 // base address: 0x5ac 4030 #define regDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0e64 4031 #define regDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 4032 #define regDSCL1_SCL_COEF_RAM_TAP_DATA 0x0e65 4033 #define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 4034 #define regDSCL1_SCL_MODE 0x0e66 4035 #define regDSCL1_SCL_MODE_BASE_IDX 2 4036 #define regDSCL1_SCL_TAP_CONTROL 0x0e67 4037 #define regDSCL1_SCL_TAP_CONTROL_BASE_IDX 2 4038 #define regDSCL1_DSCL_CONTROL 0x0e68 4039 #define regDSCL1_DSCL_CONTROL_BASE_IDX 2 4040 #define regDSCL1_DSCL_2TAP_CONTROL 0x0e69 4041 #define regDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2 4042 #define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0e6a 4043 #define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 4044 #define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0e6b 4045 #define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 4046 #define regDSCL1_SCL_HORZ_FILTER_INIT 0x0e6c 4047 #define regDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2 4048 #define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0e6d 4049 #define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 4050 #define regDSCL1_SCL_HORZ_FILTER_INIT_C 0x0e6e 4051 #define regDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 4052 #define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0e6f 4053 #define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 4054 #define regDSCL1_SCL_VERT_FILTER_INIT 0x0e70 4055 #define regDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2 4056 #define regDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0e71 4057 #define regDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 4058 #define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0e72 4059 #define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 4060 #define regDSCL1_SCL_VERT_FILTER_INIT_C 0x0e73 4061 #define regDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 4062 #define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0e74 4063 #define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 4064 #define regDSCL1_SCL_BLACK_COLOR 0x0e75 4065 #define regDSCL1_SCL_BLACK_COLOR_BASE_IDX 2 4066 #define regDSCL1_DSCL_UPDATE 0x0e76 4067 #define regDSCL1_DSCL_UPDATE_BASE_IDX 2 4068 #define regDSCL1_DSCL_AUTOCAL 0x0e77 4069 #define regDSCL1_DSCL_AUTOCAL_BASE_IDX 2 4070 #define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0e78 4071 #define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 4072 #define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0e79 4073 #define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 4074 #define regDSCL1_OTG_H_BLANK 0x0e7a 4075 #define regDSCL1_OTG_H_BLANK_BASE_IDX 2 4076 #define regDSCL1_OTG_V_BLANK 0x0e7b 4077 #define regDSCL1_OTG_V_BLANK_BASE_IDX 2 4078 #define regDSCL1_RECOUT_START 0x0e7c 4079 #define regDSCL1_RECOUT_START_BASE_IDX 2 4080 #define regDSCL1_RECOUT_SIZE 0x0e7d 4081 #define regDSCL1_RECOUT_SIZE_BASE_IDX 2 4082 #define regDSCL1_MPC_SIZE 0x0e7e 4083 #define regDSCL1_MPC_SIZE_BASE_IDX 2 4084 #define regDSCL1_LB_DATA_FORMAT 0x0e7f 4085 #define regDSCL1_LB_DATA_FORMAT_BASE_IDX 2 4086 #define regDSCL1_LB_MEMORY_CTRL 0x0e80 4087 #define regDSCL1_LB_MEMORY_CTRL_BASE_IDX 2 4088 #define regDSCL1_LB_V_COUNTER 0x0e81 4089 #define regDSCL1_LB_V_COUNTER_BASE_IDX 2 4090 #define regDSCL1_DSCL_MEM_PWR_CTRL 0x0e82 4091 #define regDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2 4092 #define regDSCL1_DSCL_MEM_PWR_STATUS 0x0e83 4093 #define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2 4094 #define regDSCL1_OBUF_CONTROL 0x0e84 4095 #define regDSCL1_OBUF_CONTROL_BASE_IDX 2 4096 #define regDSCL1_OBUF_MEM_PWR_CTRL 0x0e85 4097 #define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2 4098 4099 4100 // addressBlock: dce_dc_dpp1_dispdec_cm_dispdec 4101 // base address: 0x5ac 4102 #define regCM1_CM_CONTROL 0x0e8b 4103 #define regCM1_CM_CONTROL_BASE_IDX 2 4104 #define regCM1_CM_POST_CSC_CONTROL 0x0e8c 4105 #define regCM1_CM_POST_CSC_CONTROL_BASE_IDX 2 4106 #define regCM1_CM_POST_CSC_C11_C12 0x0e8d 4107 #define regCM1_CM_POST_CSC_C11_C12_BASE_IDX 2 4108 #define regCM1_CM_POST_CSC_C13_C14 0x0e8e 4109 #define regCM1_CM_POST_CSC_C13_C14_BASE_IDX 2 4110 #define regCM1_CM_POST_CSC_C21_C22 0x0e8f 4111 #define regCM1_CM_POST_CSC_C21_C22_BASE_IDX 2 4112 #define regCM1_CM_POST_CSC_C23_C24 0x0e90 4113 #define regCM1_CM_POST_CSC_C23_C24_BASE_IDX 2 4114 #define regCM1_CM_POST_CSC_C31_C32 0x0e91 4115 #define regCM1_CM_POST_CSC_C31_C32_BASE_IDX 2 4116 #define regCM1_CM_POST_CSC_C33_C34 0x0e92 4117 #define regCM1_CM_POST_CSC_C33_C34_BASE_IDX 2 4118 #define regCM1_CM_POST_CSC_B_C11_C12 0x0e93 4119 #define regCM1_CM_POST_CSC_B_C11_C12_BASE_IDX 2 4120 #define regCM1_CM_POST_CSC_B_C13_C14 0x0e94 4121 #define regCM1_CM_POST_CSC_B_C13_C14_BASE_IDX 2 4122 #define regCM1_CM_POST_CSC_B_C21_C22 0x0e95 4123 #define regCM1_CM_POST_CSC_B_C21_C22_BASE_IDX 2 4124 #define regCM1_CM_POST_CSC_B_C23_C24 0x0e96 4125 #define regCM1_CM_POST_CSC_B_C23_C24_BASE_IDX 2 4126 #define regCM1_CM_POST_CSC_B_C31_C32 0x0e97 4127 #define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX 2 4128 #define regCM1_CM_POST_CSC_B_C33_C34 0x0e98 4129 #define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX 2 4130 #define regCM1_CM_GAMUT_REMAP_CONTROL 0x0e99 4131 #define regCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 4132 #define regCM1_CM_GAMUT_REMAP_C11_C12 0x0e9a 4133 #define regCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 4134 #define regCM1_CM_GAMUT_REMAP_C13_C14 0x0e9b 4135 #define regCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 4136 #define regCM1_CM_GAMUT_REMAP_C21_C22 0x0e9c 4137 #define regCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 4138 #define regCM1_CM_GAMUT_REMAP_C23_C24 0x0e9d 4139 #define regCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 4140 #define regCM1_CM_GAMUT_REMAP_C31_C32 0x0e9e 4141 #define regCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 4142 #define regCM1_CM_GAMUT_REMAP_C33_C34 0x0e9f 4143 #define regCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 4144 #define regCM1_CM_GAMUT_REMAP_B_C11_C12 0x0ea0 4145 #define regCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 4146 #define regCM1_CM_GAMUT_REMAP_B_C13_C14 0x0ea1 4147 #define regCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 4148 #define regCM1_CM_GAMUT_REMAP_B_C21_C22 0x0ea2 4149 #define regCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 4150 #define regCM1_CM_GAMUT_REMAP_B_C23_C24 0x0ea3 4151 #define regCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 4152 #define regCM1_CM_GAMUT_REMAP_B_C31_C32 0x0ea4 4153 #define regCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 4154 #define regCM1_CM_GAMUT_REMAP_B_C33_C34 0x0ea5 4155 #define regCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 4156 #define regCM1_CM_BIAS_CR_R 0x0ea6 4157 #define regCM1_CM_BIAS_CR_R_BASE_IDX 2 4158 #define regCM1_CM_BIAS_Y_G_CB_B 0x0ea7 4159 #define regCM1_CM_BIAS_Y_G_CB_B_BASE_IDX 2 4160 #define regCM1_CM_GAMCOR_CONTROL 0x0ea8 4161 #define regCM1_CM_GAMCOR_CONTROL_BASE_IDX 2 4162 #define regCM1_CM_GAMCOR_LUT_INDEX 0x0ea9 4163 #define regCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 4164 #define regCM1_CM_GAMCOR_LUT_DATA 0x0eaa 4165 #define regCM1_CM_GAMCOR_LUT_DATA_BASE_IDX 2 4166 #define regCM1_CM_GAMCOR_LUT_CONTROL 0x0eab 4167 #define regCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 4168 #define regCM1_CM_GAMCOR_RAMA_START_CNTL_B 0x0eac 4169 #define regCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 4170 #define regCM1_CM_GAMCOR_RAMA_START_CNTL_G 0x0ead 4171 #define regCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 4172 #define regCM1_CM_GAMCOR_RAMA_START_CNTL_R 0x0eae 4173 #define regCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 4174 #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0eaf 4175 #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 4176 #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0eb0 4177 #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 4178 #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0eb1 4179 #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 4180 #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0eb2 4181 #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 4182 #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0eb3 4183 #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 4184 #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0eb4 4185 #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 4186 #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B 0x0eb5 4187 #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 4188 #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B 0x0eb6 4189 #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 4190 #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G 0x0eb7 4191 #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 4192 #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G 0x0eb8 4193 #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 4194 #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R 0x0eb9 4195 #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 4196 #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R 0x0eba 4197 #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 4198 #define regCM1_CM_GAMCOR_RAMA_OFFSET_B 0x0ebb 4199 #define regCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 4200 #define regCM1_CM_GAMCOR_RAMA_OFFSET_G 0x0ebc 4201 #define regCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 4202 #define regCM1_CM_GAMCOR_RAMA_OFFSET_R 0x0ebd 4203 #define regCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 4204 #define regCM1_CM_GAMCOR_RAMA_REGION_0_1 0x0ebe 4205 #define regCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 4206 #define regCM1_CM_GAMCOR_RAMA_REGION_2_3 0x0ebf 4207 #define regCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 4208 #define regCM1_CM_GAMCOR_RAMA_REGION_4_5 0x0ec0 4209 #define regCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 4210 #define regCM1_CM_GAMCOR_RAMA_REGION_6_7 0x0ec1 4211 #define regCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 4212 #define regCM1_CM_GAMCOR_RAMA_REGION_8_9 0x0ec2 4213 #define regCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 4214 #define regCM1_CM_GAMCOR_RAMA_REGION_10_11 0x0ec3 4215 #define regCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 4216 #define regCM1_CM_GAMCOR_RAMA_REGION_12_13 0x0ec4 4217 #define regCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 4218 #define regCM1_CM_GAMCOR_RAMA_REGION_14_15 0x0ec5 4219 #define regCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 4220 #define regCM1_CM_GAMCOR_RAMA_REGION_16_17 0x0ec6 4221 #define regCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 4222 #define regCM1_CM_GAMCOR_RAMA_REGION_18_19 0x0ec7 4223 #define regCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 4224 #define regCM1_CM_GAMCOR_RAMA_REGION_20_21 0x0ec8 4225 #define regCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 4226 #define regCM1_CM_GAMCOR_RAMA_REGION_22_23 0x0ec9 4227 #define regCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 4228 #define regCM1_CM_GAMCOR_RAMA_REGION_24_25 0x0eca 4229 #define regCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 4230 #define regCM1_CM_GAMCOR_RAMA_REGION_26_27 0x0ecb 4231 #define regCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 4232 #define regCM1_CM_GAMCOR_RAMA_REGION_28_29 0x0ecc 4233 #define regCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 4234 #define regCM1_CM_GAMCOR_RAMA_REGION_30_31 0x0ecd 4235 #define regCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 4236 #define regCM1_CM_GAMCOR_RAMA_REGION_32_33 0x0ece 4237 #define regCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 4238 #define regCM1_CM_GAMCOR_RAMB_START_CNTL_B 0x0ecf 4239 #define regCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 4240 #define regCM1_CM_GAMCOR_RAMB_START_CNTL_G 0x0ed0 4241 #define regCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 4242 #define regCM1_CM_GAMCOR_RAMB_START_CNTL_R 0x0ed1 4243 #define regCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 4244 #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0ed2 4245 #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 4246 #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0ed3 4247 #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 4248 #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0ed4 4249 #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 4250 #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0ed5 4251 #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 4252 #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0ed6 4253 #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 4254 #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0ed7 4255 #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 4256 #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B 0x0ed8 4257 #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 4258 #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B 0x0ed9 4259 #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 4260 #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G 0x0eda 4261 #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 4262 #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G 0x0edb 4263 #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 4264 #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R 0x0edc 4265 #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 4266 #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R 0x0edd 4267 #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 4268 #define regCM1_CM_GAMCOR_RAMB_OFFSET_B 0x0ede 4269 #define regCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 4270 #define regCM1_CM_GAMCOR_RAMB_OFFSET_G 0x0edf 4271 #define regCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 4272 #define regCM1_CM_GAMCOR_RAMB_OFFSET_R 0x0ee0 4273 #define regCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 4274 #define regCM1_CM_GAMCOR_RAMB_REGION_0_1 0x0ee1 4275 #define regCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 4276 #define regCM1_CM_GAMCOR_RAMB_REGION_2_3 0x0ee2 4277 #define regCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 4278 #define regCM1_CM_GAMCOR_RAMB_REGION_4_5 0x0ee3 4279 #define regCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 4280 #define regCM1_CM_GAMCOR_RAMB_REGION_6_7 0x0ee4 4281 #define regCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 4282 #define regCM1_CM_GAMCOR_RAMB_REGION_8_9 0x0ee5 4283 #define regCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 4284 #define regCM1_CM_GAMCOR_RAMB_REGION_10_11 0x0ee6 4285 #define regCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 4286 #define regCM1_CM_GAMCOR_RAMB_REGION_12_13 0x0ee7 4287 #define regCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 4288 #define regCM1_CM_GAMCOR_RAMB_REGION_14_15 0x0ee8 4289 #define regCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 4290 #define regCM1_CM_GAMCOR_RAMB_REGION_16_17 0x0ee9 4291 #define regCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 4292 #define regCM1_CM_GAMCOR_RAMB_REGION_18_19 0x0eea 4293 #define regCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 4294 #define regCM1_CM_GAMCOR_RAMB_REGION_20_21 0x0eeb 4295 #define regCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 4296 #define regCM1_CM_GAMCOR_RAMB_REGION_22_23 0x0eec 4297 #define regCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 4298 #define regCM1_CM_GAMCOR_RAMB_REGION_24_25 0x0eed 4299 #define regCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 4300 #define regCM1_CM_GAMCOR_RAMB_REGION_26_27 0x0eee 4301 #define regCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 4302 #define regCM1_CM_GAMCOR_RAMB_REGION_28_29 0x0eef 4303 #define regCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 4304 #define regCM1_CM_GAMCOR_RAMB_REGION_30_31 0x0ef0 4305 #define regCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 4306 #define regCM1_CM_GAMCOR_RAMB_REGION_32_33 0x0ef1 4307 #define regCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 4308 #define regCM1_CM_HDR_MULT_COEF 0x0ef2 4309 #define regCM1_CM_HDR_MULT_COEF_BASE_IDX 2 4310 #define regCM1_CM_MEM_PWR_CTRL 0x0ef3 4311 #define regCM1_CM_MEM_PWR_CTRL_BASE_IDX 2 4312 #define regCM1_CM_MEM_PWR_STATUS 0x0ef4 4313 #define regCM1_CM_MEM_PWR_STATUS_BASE_IDX 2 4314 #define regCM1_CM_DEALPHA 0x0ef6 4315 #define regCM1_CM_DEALPHA_BASE_IDX 2 4316 #define regCM1_CM_COEF_FORMAT 0x0ef7 4317 #define regCM1_CM_COEF_FORMAT_BASE_IDX 2 4318 #define regCM1_CM_TEST_DEBUG_INDEX 0x0ef8 4319 #define regCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2 4320 #define regCM1_CM_TEST_DEBUG_DATA 0x0ef9 4321 #define regCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2 4322 #define regCM1_DPP_CRC_VAL_R 0x0efa 4323 #define regCM1_DPP_CRC_VAL_R_BASE_IDX 2 4324 #define regCM1_DPP_CRC_VAL_G 0x0efb 4325 #define regCM1_DPP_CRC_VAL_G_BASE_IDX 2 4326 #define regCM1_DPP_CRC_VAL_B 0x0efc 4327 #define regCM1_DPP_CRC_VAL_B_BASE_IDX 2 4328 #define regCM1_DPP_CRC_VAL_A 0x0efd 4329 #define regCM1_DPP_CRC_VAL_A_BASE_IDX 2 4330 4331 4332 // addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec 4333 // base address: 0x5ac 4334 #define regDPP_TOP1_DPP_CONTROL 0x0e30 4335 #define regDPP_TOP1_DPP_CONTROL_BASE_IDX 2 4336 #define regDPP_TOP1_DPP_SOFT_RESET 0x0e31 4337 #define regDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2 4338 #define regDPP_TOP1_DPP_CRC_CTRL 0x0e34 4339 #define regDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2 4340 #define regDPP_TOP1_HOST_READ_CONTROL 0x0e35 4341 #define regDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2 4342 4343 4344 // addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 4345 // base address: 0x3e3c 4346 #define regDC_PERFMON12_PERFCOUNTER_CNTL 0x0f8f 4347 #define regDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2 4348 #define regDC_PERFMON12_PERFCOUNTER_CNTL2 0x0f90 4349 #define regDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2 4350 #define regDC_PERFMON12_PERFCOUNTER_STATE 0x0f91 4351 #define regDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2 4352 #define regDC_PERFMON12_PERFMON_CNTL 0x0f92 4353 #define regDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2 4354 #define regDC_PERFMON12_PERFMON_CNTL2 0x0f93 4355 #define regDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2 4356 #define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x0f94 4357 #define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 4358 #define regDC_PERFMON12_PERFMON_CVALUE_LOW 0x0f95 4359 #define regDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2 4360 #define regDC_PERFMON12_PERFMON_HI 0x0f96 4361 #define regDC_PERFMON12_PERFMON_HI_BASE_IDX 2 4362 #define regDC_PERFMON12_PERFMON_LOW 0x0f97 4363 #define regDC_PERFMON12_PERFMON_LOW_BASE_IDX 2 4364 4365 4366 // addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec 4367 // base address: 0xb58 4368 #define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0fa5 4369 #define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 4370 #define regCNVC_CFG2_FORMAT_CONTROL 0x0fa6 4371 #define regCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2 4372 #define regCNVC_CFG2_FCNV_FP_BIAS_R 0x0fa7 4373 #define regCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX 2 4374 #define regCNVC_CFG2_FCNV_FP_BIAS_G 0x0fa8 4375 #define regCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX 2 4376 #define regCNVC_CFG2_FCNV_FP_BIAS_B 0x0fa9 4377 #define regCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX 2 4378 #define regCNVC_CFG2_FCNV_FP_SCALE_R 0x0faa 4379 #define regCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX 2 4380 #define regCNVC_CFG2_FCNV_FP_SCALE_G 0x0fab 4381 #define regCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX 2 4382 #define regCNVC_CFG2_FCNV_FP_SCALE_B 0x0fac 4383 #define regCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX 2 4384 #define regCNVC_CFG2_COLOR_KEYER_CONTROL 0x0fad 4385 #define regCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2 4386 #define regCNVC_CFG2_COLOR_KEYER_ALPHA 0x0fae 4387 #define regCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2 4388 #define regCNVC_CFG2_COLOR_KEYER_RED 0x0faf 4389 #define regCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2 4390 #define regCNVC_CFG2_COLOR_KEYER_GREEN 0x0fb0 4391 #define regCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2 4392 #define regCNVC_CFG2_COLOR_KEYER_BLUE 0x0fb1 4393 #define regCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2 4394 #define regCNVC_CFG2_ALPHA_2BIT_LUT 0x0fb3 4395 #define regCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX 2 4396 #define regCNVC_CFG2_PRE_DEALPHA 0x0fb4 4397 #define regCNVC_CFG2_PRE_DEALPHA_BASE_IDX 2 4398 #define regCNVC_CFG2_PRE_CSC_MODE 0x0fb5 4399 #define regCNVC_CFG2_PRE_CSC_MODE_BASE_IDX 2 4400 #define regCNVC_CFG2_PRE_CSC_C11_C12 0x0fb6 4401 #define regCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX 2 4402 #define regCNVC_CFG2_PRE_CSC_C13_C14 0x0fb7 4403 #define regCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX 2 4404 #define regCNVC_CFG2_PRE_CSC_C21_C22 0x0fb8 4405 #define regCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX 2 4406 #define regCNVC_CFG2_PRE_CSC_C23_C24 0x0fb9 4407 #define regCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX 2 4408 #define regCNVC_CFG2_PRE_CSC_C31_C32 0x0fba 4409 #define regCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX 2 4410 #define regCNVC_CFG2_PRE_CSC_C33_C34 0x0fbb 4411 #define regCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX 2 4412 #define regCNVC_CFG2_PRE_CSC_B_C11_C12 0x0fbc 4413 #define regCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX 2 4414 #define regCNVC_CFG2_PRE_CSC_B_C13_C14 0x0fbd 4415 #define regCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX 2 4416 #define regCNVC_CFG2_PRE_CSC_B_C21_C22 0x0fbe 4417 #define regCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX 2 4418 #define regCNVC_CFG2_PRE_CSC_B_C23_C24 0x0fbf 4419 #define regCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX 2 4420 #define regCNVC_CFG2_PRE_CSC_B_C31_C32 0x0fc0 4421 #define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX 2 4422 #define regCNVC_CFG2_PRE_CSC_B_C33_C34 0x0fc1 4423 #define regCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX 2 4424 #define regCNVC_CFG2_CNVC_COEF_FORMAT 0x0fc2 4425 #define regCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX 2 4426 #define regCNVC_CFG2_PRE_DEGAM 0x0fc3 4427 #define regCNVC_CFG2_PRE_DEGAM_BASE_IDX 2 4428 #define regCNVC_CFG2_PRE_REALPHA 0x0fc4 4429 #define regCNVC_CFG2_PRE_REALPHA_BASE_IDX 2 4430 4431 4432 // addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec 4433 // base address: 0xb58 4434 #define regCNVC_CUR2_CURSOR0_CONTROL 0x0fc7 4435 #define regCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX 2 4436 #define regCNVC_CUR2_CURSOR0_COLOR0 0x0fc8 4437 #define regCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX 2 4438 #define regCNVC_CUR2_CURSOR0_COLOR1 0x0fc9 4439 #define regCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX 2 4440 #define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0x0fca 4441 #define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 4442 4443 4444 // addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec 4445 // base address: 0xb58 4446 #define regDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0fcf 4447 #define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 4448 #define regDSCL2_SCL_COEF_RAM_TAP_DATA 0x0fd0 4449 #define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 4450 #define regDSCL2_SCL_MODE 0x0fd1 4451 #define regDSCL2_SCL_MODE_BASE_IDX 2 4452 #define regDSCL2_SCL_TAP_CONTROL 0x0fd2 4453 #define regDSCL2_SCL_TAP_CONTROL_BASE_IDX 2 4454 #define regDSCL2_DSCL_CONTROL 0x0fd3 4455 #define regDSCL2_DSCL_CONTROL_BASE_IDX 2 4456 #define regDSCL2_DSCL_2TAP_CONTROL 0x0fd4 4457 #define regDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2 4458 #define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0fd5 4459 #define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 4460 #define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0fd6 4461 #define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 4462 #define regDSCL2_SCL_HORZ_FILTER_INIT 0x0fd7 4463 #define regDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2 4464 #define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fd8 4465 #define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 4466 #define regDSCL2_SCL_HORZ_FILTER_INIT_C 0x0fd9 4467 #define regDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 4468 #define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0fda 4469 #define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 4470 #define regDSCL2_SCL_VERT_FILTER_INIT 0x0fdb 4471 #define regDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2 4472 #define regDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0fdc 4473 #define regDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 4474 #define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fdd 4475 #define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 4476 #define regDSCL2_SCL_VERT_FILTER_INIT_C 0x0fde 4477 #define regDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 4478 #define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0fdf 4479 #define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 4480 #define regDSCL2_SCL_BLACK_COLOR 0x0fe0 4481 #define regDSCL2_SCL_BLACK_COLOR_BASE_IDX 2 4482 #define regDSCL2_DSCL_UPDATE 0x0fe1 4483 #define regDSCL2_DSCL_UPDATE_BASE_IDX 2 4484 #define regDSCL2_DSCL_AUTOCAL 0x0fe2 4485 #define regDSCL2_DSCL_AUTOCAL_BASE_IDX 2 4486 #define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0fe3 4487 #define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 4488 #define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0fe4 4489 #define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 4490 #define regDSCL2_OTG_H_BLANK 0x0fe5 4491 #define regDSCL2_OTG_H_BLANK_BASE_IDX 2 4492 #define regDSCL2_OTG_V_BLANK 0x0fe6 4493 #define regDSCL2_OTG_V_BLANK_BASE_IDX 2 4494 #define regDSCL2_RECOUT_START 0x0fe7 4495 #define regDSCL2_RECOUT_START_BASE_IDX 2 4496 #define regDSCL2_RECOUT_SIZE 0x0fe8 4497 #define regDSCL2_RECOUT_SIZE_BASE_IDX 2 4498 #define regDSCL2_MPC_SIZE 0x0fe9 4499 #define regDSCL2_MPC_SIZE_BASE_IDX 2 4500 #define regDSCL2_LB_DATA_FORMAT 0x0fea 4501 #define regDSCL2_LB_DATA_FORMAT_BASE_IDX 2 4502 #define regDSCL2_LB_MEMORY_CTRL 0x0feb 4503 #define regDSCL2_LB_MEMORY_CTRL_BASE_IDX 2 4504 #define regDSCL2_LB_V_COUNTER 0x0fec 4505 #define regDSCL2_LB_V_COUNTER_BASE_IDX 2 4506 #define regDSCL2_DSCL_MEM_PWR_CTRL 0x0fed 4507 #define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2 4508 #define regDSCL2_DSCL_MEM_PWR_STATUS 0x0fee 4509 #define regDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2 4510 #define regDSCL2_OBUF_CONTROL 0x0fef 4511 #define regDSCL2_OBUF_CONTROL_BASE_IDX 2 4512 #define regDSCL2_OBUF_MEM_PWR_CTRL 0x0ff0 4513 #define regDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2 4514 4515 4516 // addressBlock: dce_dc_dpp2_dispdec_cm_dispdec 4517 // base address: 0xb58 4518 #define regCM2_CM_CONTROL 0x0ff6 4519 #define regCM2_CM_CONTROL_BASE_IDX 2 4520 #define regCM2_CM_POST_CSC_CONTROL 0x0ff7 4521 #define regCM2_CM_POST_CSC_CONTROL_BASE_IDX 2 4522 #define regCM2_CM_POST_CSC_C11_C12 0x0ff8 4523 #define regCM2_CM_POST_CSC_C11_C12_BASE_IDX 2 4524 #define regCM2_CM_POST_CSC_C13_C14 0x0ff9 4525 #define regCM2_CM_POST_CSC_C13_C14_BASE_IDX 2 4526 #define regCM2_CM_POST_CSC_C21_C22 0x0ffa 4527 #define regCM2_CM_POST_CSC_C21_C22_BASE_IDX 2 4528 #define regCM2_CM_POST_CSC_C23_C24 0x0ffb 4529 #define regCM2_CM_POST_CSC_C23_C24_BASE_IDX 2 4530 #define regCM2_CM_POST_CSC_C31_C32 0x0ffc 4531 #define regCM2_CM_POST_CSC_C31_C32_BASE_IDX 2 4532 #define regCM2_CM_POST_CSC_C33_C34 0x0ffd 4533 #define regCM2_CM_POST_CSC_C33_C34_BASE_IDX 2 4534 #define regCM2_CM_POST_CSC_B_C11_C12 0x0ffe 4535 #define regCM2_CM_POST_CSC_B_C11_C12_BASE_IDX 2 4536 #define regCM2_CM_POST_CSC_B_C13_C14 0x0fff 4537 #define regCM2_CM_POST_CSC_B_C13_C14_BASE_IDX 2 4538 #define regCM2_CM_POST_CSC_B_C21_C22 0x1000 4539 #define regCM2_CM_POST_CSC_B_C21_C22_BASE_IDX 2 4540 #define regCM2_CM_POST_CSC_B_C23_C24 0x1001 4541 #define regCM2_CM_POST_CSC_B_C23_C24_BASE_IDX 2 4542 #define regCM2_CM_POST_CSC_B_C31_C32 0x1002 4543 #define regCM2_CM_POST_CSC_B_C31_C32_BASE_IDX 2 4544 #define regCM2_CM_POST_CSC_B_C33_C34 0x1003 4545 #define regCM2_CM_POST_CSC_B_C33_C34_BASE_IDX 2 4546 #define regCM2_CM_GAMUT_REMAP_CONTROL 0x1004 4547 #define regCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 4548 #define regCM2_CM_GAMUT_REMAP_C11_C12 0x1005 4549 #define regCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 4550 #define regCM2_CM_GAMUT_REMAP_C13_C14 0x1006 4551 #define regCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 4552 #define regCM2_CM_GAMUT_REMAP_C21_C22 0x1007 4553 #define regCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 4554 #define regCM2_CM_GAMUT_REMAP_C23_C24 0x1008 4555 #define regCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 4556 #define regCM2_CM_GAMUT_REMAP_C31_C32 0x1009 4557 #define regCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 4558 #define regCM2_CM_GAMUT_REMAP_C33_C34 0x100a 4559 #define regCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 4560 #define regCM2_CM_GAMUT_REMAP_B_C11_C12 0x100b 4561 #define regCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 4562 #define regCM2_CM_GAMUT_REMAP_B_C13_C14 0x100c 4563 #define regCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 4564 #define regCM2_CM_GAMUT_REMAP_B_C21_C22 0x100d 4565 #define regCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 4566 #define regCM2_CM_GAMUT_REMAP_B_C23_C24 0x100e 4567 #define regCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 4568 #define regCM2_CM_GAMUT_REMAP_B_C31_C32 0x100f 4569 #define regCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 4570 #define regCM2_CM_GAMUT_REMAP_B_C33_C34 0x1010 4571 #define regCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 4572 #define regCM2_CM_BIAS_CR_R 0x1011 4573 #define regCM2_CM_BIAS_CR_R_BASE_IDX 2 4574 #define regCM2_CM_BIAS_Y_G_CB_B 0x1012 4575 #define regCM2_CM_BIAS_Y_G_CB_B_BASE_IDX 2 4576 #define regCM2_CM_GAMCOR_CONTROL 0x1013 4577 #define regCM2_CM_GAMCOR_CONTROL_BASE_IDX 2 4578 #define regCM2_CM_GAMCOR_LUT_INDEX 0x1014 4579 #define regCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 4580 #define regCM2_CM_GAMCOR_LUT_DATA 0x1015 4581 #define regCM2_CM_GAMCOR_LUT_DATA_BASE_IDX 2 4582 #define regCM2_CM_GAMCOR_LUT_CONTROL 0x1016 4583 #define regCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 4584 #define regCM2_CM_GAMCOR_RAMA_START_CNTL_B 0x1017 4585 #define regCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 4586 #define regCM2_CM_GAMCOR_RAMA_START_CNTL_G 0x1018 4587 #define regCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 4588 #define regCM2_CM_GAMCOR_RAMA_START_CNTL_R 0x1019 4589 #define regCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 4590 #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x101a 4591 #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 4592 #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x101b 4593 #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 4594 #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x101c 4595 #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 4596 #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x101d 4597 #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 4598 #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x101e 4599 #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 4600 #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x101f 4601 #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 4602 #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B 0x1020 4603 #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 4604 #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B 0x1021 4605 #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 4606 #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G 0x1022 4607 #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 4608 #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G 0x1023 4609 #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 4610 #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R 0x1024 4611 #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 4612 #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R 0x1025 4613 #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 4614 #define regCM2_CM_GAMCOR_RAMA_OFFSET_B 0x1026 4615 #define regCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 4616 #define regCM2_CM_GAMCOR_RAMA_OFFSET_G 0x1027 4617 #define regCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 4618 #define regCM2_CM_GAMCOR_RAMA_OFFSET_R 0x1028 4619 #define regCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 4620 #define regCM2_CM_GAMCOR_RAMA_REGION_0_1 0x1029 4621 #define regCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 4622 #define regCM2_CM_GAMCOR_RAMA_REGION_2_3 0x102a 4623 #define regCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 4624 #define regCM2_CM_GAMCOR_RAMA_REGION_4_5 0x102b 4625 #define regCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 4626 #define regCM2_CM_GAMCOR_RAMA_REGION_6_7 0x102c 4627 #define regCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 4628 #define regCM2_CM_GAMCOR_RAMA_REGION_8_9 0x102d 4629 #define regCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 4630 #define regCM2_CM_GAMCOR_RAMA_REGION_10_11 0x102e 4631 #define regCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 4632 #define regCM2_CM_GAMCOR_RAMA_REGION_12_13 0x102f 4633 #define regCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 4634 #define regCM2_CM_GAMCOR_RAMA_REGION_14_15 0x1030 4635 #define regCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 4636 #define regCM2_CM_GAMCOR_RAMA_REGION_16_17 0x1031 4637 #define regCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 4638 #define regCM2_CM_GAMCOR_RAMA_REGION_18_19 0x1032 4639 #define regCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 4640 #define regCM2_CM_GAMCOR_RAMA_REGION_20_21 0x1033 4641 #define regCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 4642 #define regCM2_CM_GAMCOR_RAMA_REGION_22_23 0x1034 4643 #define regCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 4644 #define regCM2_CM_GAMCOR_RAMA_REGION_24_25 0x1035 4645 #define regCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 4646 #define regCM2_CM_GAMCOR_RAMA_REGION_26_27 0x1036 4647 #define regCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 4648 #define regCM2_CM_GAMCOR_RAMA_REGION_28_29 0x1037 4649 #define regCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 4650 #define regCM2_CM_GAMCOR_RAMA_REGION_30_31 0x1038 4651 #define regCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 4652 #define regCM2_CM_GAMCOR_RAMA_REGION_32_33 0x1039 4653 #define regCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 4654 #define regCM2_CM_GAMCOR_RAMB_START_CNTL_B 0x103a 4655 #define regCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 4656 #define regCM2_CM_GAMCOR_RAMB_START_CNTL_G 0x103b 4657 #define regCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 4658 #define regCM2_CM_GAMCOR_RAMB_START_CNTL_R 0x103c 4659 #define regCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 4660 #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x103d 4661 #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 4662 #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x103e 4663 #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 4664 #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x103f 4665 #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 4666 #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x1040 4667 #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 4668 #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x1041 4669 #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 4670 #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x1042 4671 #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 4672 #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B 0x1043 4673 #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 4674 #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B 0x1044 4675 #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 4676 #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G 0x1045 4677 #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 4678 #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G 0x1046 4679 #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 4680 #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R 0x1047 4681 #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 4682 #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R 0x1048 4683 #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 4684 #define regCM2_CM_GAMCOR_RAMB_OFFSET_B 0x1049 4685 #define regCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 4686 #define regCM2_CM_GAMCOR_RAMB_OFFSET_G 0x104a 4687 #define regCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 4688 #define regCM2_CM_GAMCOR_RAMB_OFFSET_R 0x104b 4689 #define regCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 4690 #define regCM2_CM_GAMCOR_RAMB_REGION_0_1 0x104c 4691 #define regCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 4692 #define regCM2_CM_GAMCOR_RAMB_REGION_2_3 0x104d 4693 #define regCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 4694 #define regCM2_CM_GAMCOR_RAMB_REGION_4_5 0x104e 4695 #define regCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 4696 #define regCM2_CM_GAMCOR_RAMB_REGION_6_7 0x104f 4697 #define regCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 4698 #define regCM2_CM_GAMCOR_RAMB_REGION_8_9 0x1050 4699 #define regCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 4700 #define regCM2_CM_GAMCOR_RAMB_REGION_10_11 0x1051 4701 #define regCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 4702 #define regCM2_CM_GAMCOR_RAMB_REGION_12_13 0x1052 4703 #define regCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 4704 #define regCM2_CM_GAMCOR_RAMB_REGION_14_15 0x1053 4705 #define regCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 4706 #define regCM2_CM_GAMCOR_RAMB_REGION_16_17 0x1054 4707 #define regCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 4708 #define regCM2_CM_GAMCOR_RAMB_REGION_18_19 0x1055 4709 #define regCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 4710 #define regCM2_CM_GAMCOR_RAMB_REGION_20_21 0x1056 4711 #define regCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 4712 #define regCM2_CM_GAMCOR_RAMB_REGION_22_23 0x1057 4713 #define regCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 4714 #define regCM2_CM_GAMCOR_RAMB_REGION_24_25 0x1058 4715 #define regCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 4716 #define regCM2_CM_GAMCOR_RAMB_REGION_26_27 0x1059 4717 #define regCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 4718 #define regCM2_CM_GAMCOR_RAMB_REGION_28_29 0x105a 4719 #define regCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 4720 #define regCM2_CM_GAMCOR_RAMB_REGION_30_31 0x105b 4721 #define regCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 4722 #define regCM2_CM_GAMCOR_RAMB_REGION_32_33 0x105c 4723 #define regCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 4724 #define regCM2_CM_HDR_MULT_COEF 0x105d 4725 #define regCM2_CM_HDR_MULT_COEF_BASE_IDX 2 4726 #define regCM2_CM_MEM_PWR_CTRL 0x105e 4727 #define regCM2_CM_MEM_PWR_CTRL_BASE_IDX 2 4728 #define regCM2_CM_MEM_PWR_STATUS 0x105f 4729 #define regCM2_CM_MEM_PWR_STATUS_BASE_IDX 2 4730 #define regCM2_CM_DEALPHA 0x1061 4731 #define regCM2_CM_DEALPHA_BASE_IDX 2 4732 #define regCM2_CM_COEF_FORMAT 0x1062 4733 #define regCM2_CM_COEF_FORMAT_BASE_IDX 2 4734 #define regCM2_CM_TEST_DEBUG_INDEX 0x1063 4735 #define regCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2 4736 #define regCM2_CM_TEST_DEBUG_DATA 0x1064 4737 #define regCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2 4738 #define regCM2_DPP_CRC_VAL_R 0x1065 4739 #define regCM2_DPP_CRC_VAL_R_BASE_IDX 2 4740 #define regCM2_DPP_CRC_VAL_G 0x1066 4741 #define regCM2_DPP_CRC_VAL_G_BASE_IDX 2 4742 #define regCM2_DPP_CRC_VAL_B 0x1067 4743 #define regCM2_DPP_CRC_VAL_B_BASE_IDX 2 4744 #define regCM2_DPP_CRC_VAL_A 0x1068 4745 #define regCM2_DPP_CRC_VAL_A_BASE_IDX 2 4746 4747 4748 // addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec 4749 // base address: 0xb58 4750 #define regDPP_TOP2_DPP_CONTROL 0x0f9b 4751 #define regDPP_TOP2_DPP_CONTROL_BASE_IDX 2 4752 #define regDPP_TOP2_DPP_SOFT_RESET 0x0f9c 4753 #define regDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2 4754 #define regDPP_TOP2_DPP_CRC_CTRL 0x0f9f 4755 #define regDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2 4756 #define regDPP_TOP2_HOST_READ_CONTROL 0x0fa0 4757 #define regDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2 4758 4759 4760 // addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 4761 // base address: 0x43e8 4762 #define regDC_PERFMON13_PERFCOUNTER_CNTL 0x10fa 4763 #define regDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2 4764 #define regDC_PERFMON13_PERFCOUNTER_CNTL2 0x10fb 4765 #define regDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2 4766 #define regDC_PERFMON13_PERFCOUNTER_STATE 0x10fc 4767 #define regDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2 4768 #define regDC_PERFMON13_PERFMON_CNTL 0x10fd 4769 #define regDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2 4770 #define regDC_PERFMON13_PERFMON_CNTL2 0x10fe 4771 #define regDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2 4772 #define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x10ff 4773 #define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 4774 #define regDC_PERFMON13_PERFMON_CVALUE_LOW 0x1100 4775 #define regDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2 4776 #define regDC_PERFMON13_PERFMON_HI 0x1101 4777 #define regDC_PERFMON13_PERFMON_HI_BASE_IDX 2 4778 #define regDC_PERFMON13_PERFMON_LOW 0x1102 4779 #define regDC_PERFMON13_PERFMON_LOW_BASE_IDX 2 4780 4781 4782 // addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec 4783 // base address: 0x1104 4784 #define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x1110 4785 #define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 4786 #define regCNVC_CFG3_FORMAT_CONTROL 0x1111 4787 #define regCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2 4788 #define regCNVC_CFG3_FCNV_FP_BIAS_R 0x1112 4789 #define regCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX 2 4790 #define regCNVC_CFG3_FCNV_FP_BIAS_G 0x1113 4791 #define regCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX 2 4792 #define regCNVC_CFG3_FCNV_FP_BIAS_B 0x1114 4793 #define regCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX 2 4794 #define regCNVC_CFG3_FCNV_FP_SCALE_R 0x1115 4795 #define regCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX 2 4796 #define regCNVC_CFG3_FCNV_FP_SCALE_G 0x1116 4797 #define regCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX 2 4798 #define regCNVC_CFG3_FCNV_FP_SCALE_B 0x1117 4799 #define regCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX 2 4800 #define regCNVC_CFG3_COLOR_KEYER_CONTROL 0x1118 4801 #define regCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2 4802 #define regCNVC_CFG3_COLOR_KEYER_ALPHA 0x1119 4803 #define regCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2 4804 #define regCNVC_CFG3_COLOR_KEYER_RED 0x111a 4805 #define regCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2 4806 #define regCNVC_CFG3_COLOR_KEYER_GREEN 0x111b 4807 #define regCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2 4808 #define regCNVC_CFG3_COLOR_KEYER_BLUE 0x111c 4809 #define regCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2 4810 #define regCNVC_CFG3_ALPHA_2BIT_LUT 0x111e 4811 #define regCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX 2 4812 #define regCNVC_CFG3_PRE_DEALPHA 0x111f 4813 #define regCNVC_CFG3_PRE_DEALPHA_BASE_IDX 2 4814 #define regCNVC_CFG3_PRE_CSC_MODE 0x1120 4815 #define regCNVC_CFG3_PRE_CSC_MODE_BASE_IDX 2 4816 #define regCNVC_CFG3_PRE_CSC_C11_C12 0x1121 4817 #define regCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX 2 4818 #define regCNVC_CFG3_PRE_CSC_C13_C14 0x1122 4819 #define regCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX 2 4820 #define regCNVC_CFG3_PRE_CSC_C21_C22 0x1123 4821 #define regCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX 2 4822 #define regCNVC_CFG3_PRE_CSC_C23_C24 0x1124 4823 #define regCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX 2 4824 #define regCNVC_CFG3_PRE_CSC_C31_C32 0x1125 4825 #define regCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX 2 4826 #define regCNVC_CFG3_PRE_CSC_C33_C34 0x1126 4827 #define regCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX 2 4828 #define regCNVC_CFG3_PRE_CSC_B_C11_C12 0x1127 4829 #define regCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX 2 4830 #define regCNVC_CFG3_PRE_CSC_B_C13_C14 0x1128 4831 #define regCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX 2 4832 #define regCNVC_CFG3_PRE_CSC_B_C21_C22 0x1129 4833 #define regCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX 2 4834 #define regCNVC_CFG3_PRE_CSC_B_C23_C24 0x112a 4835 #define regCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX 2 4836 #define regCNVC_CFG3_PRE_CSC_B_C31_C32 0x112b 4837 #define regCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX 2 4838 #define regCNVC_CFG3_PRE_CSC_B_C33_C34 0x112c 4839 #define regCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX 2 4840 #define regCNVC_CFG3_CNVC_COEF_FORMAT 0x112d 4841 #define regCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX 2 4842 #define regCNVC_CFG3_PRE_DEGAM 0x112e 4843 #define regCNVC_CFG3_PRE_DEGAM_BASE_IDX 2 4844 #define regCNVC_CFG3_PRE_REALPHA 0x112f 4845 #define regCNVC_CFG3_PRE_REALPHA_BASE_IDX 2 4846 4847 4848 // addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec 4849 // base address: 0x1104 4850 #define regCNVC_CUR3_CURSOR0_CONTROL 0x1132 4851 #define regCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX 2 4852 #define regCNVC_CUR3_CURSOR0_COLOR0 0x1133 4853 #define regCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX 2 4854 #define regCNVC_CUR3_CURSOR0_COLOR1 0x1134 4855 #define regCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX 2 4856 #define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0x1135 4857 #define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 4858 4859 4860 // addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec 4861 // base address: 0x1104 4862 #define regDSCL3_SCL_COEF_RAM_TAP_SELECT 0x113a 4863 #define regDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 4864 #define regDSCL3_SCL_COEF_RAM_TAP_DATA 0x113b 4865 #define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 4866 #define regDSCL3_SCL_MODE 0x113c 4867 #define regDSCL3_SCL_MODE_BASE_IDX 2 4868 #define regDSCL3_SCL_TAP_CONTROL 0x113d 4869 #define regDSCL3_SCL_TAP_CONTROL_BASE_IDX 2 4870 #define regDSCL3_DSCL_CONTROL 0x113e 4871 #define regDSCL3_DSCL_CONTROL_BASE_IDX 2 4872 #define regDSCL3_DSCL_2TAP_CONTROL 0x113f 4873 #define regDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2 4874 #define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x1140 4875 #define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 4876 #define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x1141 4877 #define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 4878 #define regDSCL3_SCL_HORZ_FILTER_INIT 0x1142 4879 #define regDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2 4880 #define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x1143 4881 #define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 4882 #define regDSCL3_SCL_HORZ_FILTER_INIT_C 0x1144 4883 #define regDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 4884 #define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x1145 4885 #define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 4886 #define regDSCL3_SCL_VERT_FILTER_INIT 0x1146 4887 #define regDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2 4888 #define regDSCL3_SCL_VERT_FILTER_INIT_BOT 0x1147 4889 #define regDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 4890 #define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x1148 4891 #define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 4892 #define regDSCL3_SCL_VERT_FILTER_INIT_C 0x1149 4893 #define regDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 4894 #define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x114a 4895 #define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 4896 #define regDSCL3_SCL_BLACK_COLOR 0x114b 4897 #define regDSCL3_SCL_BLACK_COLOR_BASE_IDX 2 4898 #define regDSCL3_DSCL_UPDATE 0x114c 4899 #define regDSCL3_DSCL_UPDATE_BASE_IDX 2 4900 #define regDSCL3_DSCL_AUTOCAL 0x114d 4901 #define regDSCL3_DSCL_AUTOCAL_BASE_IDX 2 4902 #define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x114e 4903 #define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 4904 #define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x114f 4905 #define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 4906 #define regDSCL3_OTG_H_BLANK 0x1150 4907 #define regDSCL3_OTG_H_BLANK_BASE_IDX 2 4908 #define regDSCL3_OTG_V_BLANK 0x1151 4909 #define regDSCL3_OTG_V_BLANK_BASE_IDX 2 4910 #define regDSCL3_RECOUT_START 0x1152 4911 #define regDSCL3_RECOUT_START_BASE_IDX 2 4912 #define regDSCL3_RECOUT_SIZE 0x1153 4913 #define regDSCL3_RECOUT_SIZE_BASE_IDX 2 4914 #define regDSCL3_MPC_SIZE 0x1154 4915 #define regDSCL3_MPC_SIZE_BASE_IDX 2 4916 #define regDSCL3_LB_DATA_FORMAT 0x1155 4917 #define regDSCL3_LB_DATA_FORMAT_BASE_IDX 2 4918 #define regDSCL3_LB_MEMORY_CTRL 0x1156 4919 #define regDSCL3_LB_MEMORY_CTRL_BASE_IDX 2 4920 #define regDSCL3_LB_V_COUNTER 0x1157 4921 #define regDSCL3_LB_V_COUNTER_BASE_IDX 2 4922 #define regDSCL3_DSCL_MEM_PWR_CTRL 0x1158 4923 #define regDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2 4924 #define regDSCL3_DSCL_MEM_PWR_STATUS 0x1159 4925 #define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2 4926 #define regDSCL3_OBUF_CONTROL 0x115a 4927 #define regDSCL3_OBUF_CONTROL_BASE_IDX 2 4928 #define regDSCL3_OBUF_MEM_PWR_CTRL 0x115b 4929 #define regDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2 4930 4931 4932 // addressBlock: dce_dc_dpp3_dispdec_cm_dispdec 4933 // base address: 0x1104 4934 #define regCM3_CM_CONTROL 0x1161 4935 #define regCM3_CM_CONTROL_BASE_IDX 2 4936 #define regCM3_CM_POST_CSC_CONTROL 0x1162 4937 #define regCM3_CM_POST_CSC_CONTROL_BASE_IDX 2 4938 #define regCM3_CM_POST_CSC_C11_C12 0x1163 4939 #define regCM3_CM_POST_CSC_C11_C12_BASE_IDX 2 4940 #define regCM3_CM_POST_CSC_C13_C14 0x1164 4941 #define regCM3_CM_POST_CSC_C13_C14_BASE_IDX 2 4942 #define regCM3_CM_POST_CSC_C21_C22 0x1165 4943 #define regCM3_CM_POST_CSC_C21_C22_BASE_IDX 2 4944 #define regCM3_CM_POST_CSC_C23_C24 0x1166 4945 #define regCM3_CM_POST_CSC_C23_C24_BASE_IDX 2 4946 #define regCM3_CM_POST_CSC_C31_C32 0x1167 4947 #define regCM3_CM_POST_CSC_C31_C32_BASE_IDX 2 4948 #define regCM3_CM_POST_CSC_C33_C34 0x1168 4949 #define regCM3_CM_POST_CSC_C33_C34_BASE_IDX 2 4950 #define regCM3_CM_POST_CSC_B_C11_C12 0x1169 4951 #define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX 2 4952 #define regCM3_CM_POST_CSC_B_C13_C14 0x116a 4953 #define regCM3_CM_POST_CSC_B_C13_C14_BASE_IDX 2 4954 #define regCM3_CM_POST_CSC_B_C21_C22 0x116b 4955 #define regCM3_CM_POST_CSC_B_C21_C22_BASE_IDX 2 4956 #define regCM3_CM_POST_CSC_B_C23_C24 0x116c 4957 #define regCM3_CM_POST_CSC_B_C23_C24_BASE_IDX 2 4958 #define regCM3_CM_POST_CSC_B_C31_C32 0x116d 4959 #define regCM3_CM_POST_CSC_B_C31_C32_BASE_IDX 2 4960 #define regCM3_CM_POST_CSC_B_C33_C34 0x116e 4961 #define regCM3_CM_POST_CSC_B_C33_C34_BASE_IDX 2 4962 #define regCM3_CM_GAMUT_REMAP_CONTROL 0x116f 4963 #define regCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 4964 #define regCM3_CM_GAMUT_REMAP_C11_C12 0x1170 4965 #define regCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 4966 #define regCM3_CM_GAMUT_REMAP_C13_C14 0x1171 4967 #define regCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 4968 #define regCM3_CM_GAMUT_REMAP_C21_C22 0x1172 4969 #define regCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 4970 #define regCM3_CM_GAMUT_REMAP_C23_C24 0x1173 4971 #define regCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 4972 #define regCM3_CM_GAMUT_REMAP_C31_C32 0x1174 4973 #define regCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 4974 #define regCM3_CM_GAMUT_REMAP_C33_C34 0x1175 4975 #define regCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 4976 #define regCM3_CM_GAMUT_REMAP_B_C11_C12 0x1176 4977 #define regCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 4978 #define regCM3_CM_GAMUT_REMAP_B_C13_C14 0x1177 4979 #define regCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 4980 #define regCM3_CM_GAMUT_REMAP_B_C21_C22 0x1178 4981 #define regCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 4982 #define regCM3_CM_GAMUT_REMAP_B_C23_C24 0x1179 4983 #define regCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 4984 #define regCM3_CM_GAMUT_REMAP_B_C31_C32 0x117a 4985 #define regCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 4986 #define regCM3_CM_GAMUT_REMAP_B_C33_C34 0x117b 4987 #define regCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 4988 #define regCM3_CM_BIAS_CR_R 0x117c 4989 #define regCM3_CM_BIAS_CR_R_BASE_IDX 2 4990 #define regCM3_CM_BIAS_Y_G_CB_B 0x117d 4991 #define regCM3_CM_BIAS_Y_G_CB_B_BASE_IDX 2 4992 #define regCM3_CM_GAMCOR_CONTROL 0x117e 4993 #define regCM3_CM_GAMCOR_CONTROL_BASE_IDX 2 4994 #define regCM3_CM_GAMCOR_LUT_INDEX 0x117f 4995 #define regCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 4996 #define regCM3_CM_GAMCOR_LUT_DATA 0x1180 4997 #define regCM3_CM_GAMCOR_LUT_DATA_BASE_IDX 2 4998 #define regCM3_CM_GAMCOR_LUT_CONTROL 0x1181 4999 #define regCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 5000 #define regCM3_CM_GAMCOR_RAMA_START_CNTL_B 0x1182 5001 #define regCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 5002 #define regCM3_CM_GAMCOR_RAMA_START_CNTL_G 0x1183 5003 #define regCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 5004 #define regCM3_CM_GAMCOR_RAMA_START_CNTL_R 0x1184 5005 #define regCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 5006 #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x1185 5007 #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 5008 #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x1186 5009 #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 5010 #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x1187 5011 #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 5012 #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x1188 5013 #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 5014 #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x1189 5015 #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 5016 #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x118a 5017 #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 5018 #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B 0x118b 5019 #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 5020 #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B 0x118c 5021 #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 5022 #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G 0x118d 5023 #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 5024 #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G 0x118e 5025 #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 5026 #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R 0x118f 5027 #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 5028 #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R 0x1190 5029 #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 5030 #define regCM3_CM_GAMCOR_RAMA_OFFSET_B 0x1191 5031 #define regCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 5032 #define regCM3_CM_GAMCOR_RAMA_OFFSET_G 0x1192 5033 #define regCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 5034 #define regCM3_CM_GAMCOR_RAMA_OFFSET_R 0x1193 5035 #define regCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 5036 #define regCM3_CM_GAMCOR_RAMA_REGION_0_1 0x1194 5037 #define regCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 5038 #define regCM3_CM_GAMCOR_RAMA_REGION_2_3 0x1195 5039 #define regCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 5040 #define regCM3_CM_GAMCOR_RAMA_REGION_4_5 0x1196 5041 #define regCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 5042 #define regCM3_CM_GAMCOR_RAMA_REGION_6_7 0x1197 5043 #define regCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 5044 #define regCM3_CM_GAMCOR_RAMA_REGION_8_9 0x1198 5045 #define regCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 5046 #define regCM3_CM_GAMCOR_RAMA_REGION_10_11 0x1199 5047 #define regCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 5048 #define regCM3_CM_GAMCOR_RAMA_REGION_12_13 0x119a 5049 #define regCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 5050 #define regCM3_CM_GAMCOR_RAMA_REGION_14_15 0x119b 5051 #define regCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 5052 #define regCM3_CM_GAMCOR_RAMA_REGION_16_17 0x119c 5053 #define regCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 5054 #define regCM3_CM_GAMCOR_RAMA_REGION_18_19 0x119d 5055 #define regCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 5056 #define regCM3_CM_GAMCOR_RAMA_REGION_20_21 0x119e 5057 #define regCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 5058 #define regCM3_CM_GAMCOR_RAMA_REGION_22_23 0x119f 5059 #define regCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 5060 #define regCM3_CM_GAMCOR_RAMA_REGION_24_25 0x11a0 5061 #define regCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 5062 #define regCM3_CM_GAMCOR_RAMA_REGION_26_27 0x11a1 5063 #define regCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 5064 #define regCM3_CM_GAMCOR_RAMA_REGION_28_29 0x11a2 5065 #define regCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 5066 #define regCM3_CM_GAMCOR_RAMA_REGION_30_31 0x11a3 5067 #define regCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 5068 #define regCM3_CM_GAMCOR_RAMA_REGION_32_33 0x11a4 5069 #define regCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 5070 #define regCM3_CM_GAMCOR_RAMB_START_CNTL_B 0x11a5 5071 #define regCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 5072 #define regCM3_CM_GAMCOR_RAMB_START_CNTL_G 0x11a6 5073 #define regCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 5074 #define regCM3_CM_GAMCOR_RAMB_START_CNTL_R 0x11a7 5075 #define regCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 5076 #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x11a8 5077 #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 5078 #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x11a9 5079 #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 5080 #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x11aa 5081 #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 5082 #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x11ab 5083 #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 5084 #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x11ac 5085 #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 5086 #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x11ad 5087 #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 5088 #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B 0x11ae 5089 #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 5090 #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B 0x11af 5091 #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 5092 #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G 0x11b0 5093 #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 5094 #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G 0x11b1 5095 #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 5096 #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R 0x11b2 5097 #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 5098 #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R 0x11b3 5099 #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 5100 #define regCM3_CM_GAMCOR_RAMB_OFFSET_B 0x11b4 5101 #define regCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 5102 #define regCM3_CM_GAMCOR_RAMB_OFFSET_G 0x11b5 5103 #define regCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 5104 #define regCM3_CM_GAMCOR_RAMB_OFFSET_R 0x11b6 5105 #define regCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 5106 #define regCM3_CM_GAMCOR_RAMB_REGION_0_1 0x11b7 5107 #define regCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 5108 #define regCM3_CM_GAMCOR_RAMB_REGION_2_3 0x11b8 5109 #define regCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 5110 #define regCM3_CM_GAMCOR_RAMB_REGION_4_5 0x11b9 5111 #define regCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 5112 #define regCM3_CM_GAMCOR_RAMB_REGION_6_7 0x11ba 5113 #define regCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 5114 #define regCM3_CM_GAMCOR_RAMB_REGION_8_9 0x11bb 5115 #define regCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 5116 #define regCM3_CM_GAMCOR_RAMB_REGION_10_11 0x11bc 5117 #define regCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 5118 #define regCM3_CM_GAMCOR_RAMB_REGION_12_13 0x11bd 5119 #define regCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 5120 #define regCM3_CM_GAMCOR_RAMB_REGION_14_15 0x11be 5121 #define regCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 5122 #define regCM3_CM_GAMCOR_RAMB_REGION_16_17 0x11bf 5123 #define regCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 5124 #define regCM3_CM_GAMCOR_RAMB_REGION_18_19 0x11c0 5125 #define regCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 5126 #define regCM3_CM_GAMCOR_RAMB_REGION_20_21 0x11c1 5127 #define regCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 5128 #define regCM3_CM_GAMCOR_RAMB_REGION_22_23 0x11c2 5129 #define regCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 5130 #define regCM3_CM_GAMCOR_RAMB_REGION_24_25 0x11c3 5131 #define regCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 5132 #define regCM3_CM_GAMCOR_RAMB_REGION_26_27 0x11c4 5133 #define regCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 5134 #define regCM3_CM_GAMCOR_RAMB_REGION_28_29 0x11c5 5135 #define regCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 5136 #define regCM3_CM_GAMCOR_RAMB_REGION_30_31 0x11c6 5137 #define regCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 5138 #define regCM3_CM_GAMCOR_RAMB_REGION_32_33 0x11c7 5139 #define regCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 5140 #define regCM3_CM_HDR_MULT_COEF 0x11c8 5141 #define regCM3_CM_HDR_MULT_COEF_BASE_IDX 2 5142 #define regCM3_CM_MEM_PWR_CTRL 0x11c9 5143 #define regCM3_CM_MEM_PWR_CTRL_BASE_IDX 2 5144 #define regCM3_CM_MEM_PWR_STATUS 0x11ca 5145 #define regCM3_CM_MEM_PWR_STATUS_BASE_IDX 2 5146 #define regCM3_CM_DEALPHA 0x11cc 5147 #define regCM3_CM_DEALPHA_BASE_IDX 2 5148 #define regCM3_CM_COEF_FORMAT 0x11cd 5149 #define regCM3_CM_COEF_FORMAT_BASE_IDX 2 5150 #define regCM3_CM_TEST_DEBUG_INDEX 0x11ce 5151 #define regCM3_CM_TEST_DEBUG_INDEX_BASE_IDX 2 5152 #define regCM3_CM_TEST_DEBUG_DATA 0x11cf 5153 #define regCM3_CM_TEST_DEBUG_DATA_BASE_IDX 2 5154 #define regCM3_DPP_CRC_VAL_R 0x11d0 5155 #define regCM3_DPP_CRC_VAL_R_BASE_IDX 2 5156 #define regCM3_DPP_CRC_VAL_G 0x11d1 5157 #define regCM3_DPP_CRC_VAL_G_BASE_IDX 2 5158 #define regCM3_DPP_CRC_VAL_B 0x11d2 5159 #define regCM3_DPP_CRC_VAL_B_BASE_IDX 2 5160 #define regCM3_DPP_CRC_VAL_A 0x11d3 5161 #define regCM3_DPP_CRC_VAL_A_BASE_IDX 2 5162 5163 5164 // addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec 5165 // base address: 0x1104 5166 #define regDPP_TOP3_DPP_CONTROL 0x1106 5167 #define regDPP_TOP3_DPP_CONTROL_BASE_IDX 2 5168 #define regDPP_TOP3_DPP_SOFT_RESET 0x1107 5169 #define regDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2 5170 #define regDPP_TOP3_DPP_CRC_CTRL 0x110a 5171 #define regDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2 5172 #define regDPP_TOP3_HOST_READ_CONTROL 0x110b 5173 #define regDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2 5174 5175 5176 // addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 5177 // base address: 0x4994 5178 #define regDC_PERFMON14_PERFCOUNTER_CNTL 0x1265 5179 #define regDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX 2 5180 #define regDC_PERFMON14_PERFCOUNTER_CNTL2 0x1266 5181 #define regDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX 2 5182 #define regDC_PERFMON14_PERFCOUNTER_STATE 0x1267 5183 #define regDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX 2 5184 #define regDC_PERFMON14_PERFMON_CNTL 0x1268 5185 #define regDC_PERFMON14_PERFMON_CNTL_BASE_IDX 2 5186 #define regDC_PERFMON14_PERFMON_CNTL2 0x1269 5187 #define regDC_PERFMON14_PERFMON_CNTL2_BASE_IDX 2 5188 #define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC 0x126a 5189 #define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 5190 #define regDC_PERFMON14_PERFMON_CVALUE_LOW 0x126b 5191 #define regDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX 2 5192 #define regDC_PERFMON14_PERFMON_HI 0x126c 5193 #define regDC_PERFMON14_PERFMON_HI_BASE_IDX 2 5194 #define regDC_PERFMON14_PERFMON_LOW 0x126d 5195 #define regDC_PERFMON14_PERFMON_LOW_BASE_IDX 2 5196 5197 5198 // addressBlock: dce_dc_mpc_mpcc0_dispdec 5199 // base address: 0x0 5200 #define regMPCC0_MPCC_TOP_SEL 0x0000 5201 #define regMPCC0_MPCC_TOP_SEL_BASE_IDX 3 5202 #define regMPCC0_MPCC_BOT_SEL 0x0001 5203 #define regMPCC0_MPCC_BOT_SEL_BASE_IDX 3 5204 #define regMPCC0_MPCC_OPP_ID 0x0002 5205 #define regMPCC0_MPCC_OPP_ID_BASE_IDX 3 5206 #define regMPCC0_MPCC_CONTROL 0x0003 5207 #define regMPCC0_MPCC_CONTROL_BASE_IDX 3 5208 #define regMPCC0_MPCC_SM_CONTROL 0x0004 5209 #define regMPCC0_MPCC_SM_CONTROL_BASE_IDX 3 5210 #define regMPCC0_MPCC_UPDATE_LOCK_SEL 0x0005 5211 #define regMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 5212 #define regMPCC0_MPCC_TOP_GAIN 0x0006 5213 #define regMPCC0_MPCC_TOP_GAIN_BASE_IDX 3 5214 #define regMPCC0_MPCC_BOT_GAIN_INSIDE 0x0007 5215 #define regMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 5216 #define regMPCC0_MPCC_BOT_GAIN_OUTSIDE 0x0008 5217 #define regMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 5218 #define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x0009 5219 #define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 5220 #define regMPCC0_MPCC_BG_R_CR 0x000a 5221 #define regMPCC0_MPCC_BG_R_CR_BASE_IDX 3 5222 #define regMPCC0_MPCC_BG_G_Y 0x000b 5223 #define regMPCC0_MPCC_BG_G_Y_BASE_IDX 3 5224 #define regMPCC0_MPCC_BG_B_CB 0x000c 5225 #define regMPCC0_MPCC_BG_B_CB_BASE_IDX 3 5226 #define regMPCC0_MPCC_MEM_PWR_CTRL 0x000d 5227 #define regMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 3 5228 #define regMPCC0_MPCC_STATUS 0x000e 5229 #define regMPCC0_MPCC_STATUS_BASE_IDX 3 5230 5231 5232 // addressBlock: dce_dc_mpc_mpcc1_dispdec 5233 // base address: 0x54 5234 #define regMPCC1_MPCC_TOP_SEL 0x0015 5235 #define regMPCC1_MPCC_TOP_SEL_BASE_IDX 3 5236 #define regMPCC1_MPCC_BOT_SEL 0x0016 5237 #define regMPCC1_MPCC_BOT_SEL_BASE_IDX 3 5238 #define regMPCC1_MPCC_OPP_ID 0x0017 5239 #define regMPCC1_MPCC_OPP_ID_BASE_IDX 3 5240 #define regMPCC1_MPCC_CONTROL 0x0018 5241 #define regMPCC1_MPCC_CONTROL_BASE_IDX 3 5242 #define regMPCC1_MPCC_SM_CONTROL 0x0019 5243 #define regMPCC1_MPCC_SM_CONTROL_BASE_IDX 3 5244 #define regMPCC1_MPCC_UPDATE_LOCK_SEL 0x001a 5245 #define regMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 5246 #define regMPCC1_MPCC_TOP_GAIN 0x001b 5247 #define regMPCC1_MPCC_TOP_GAIN_BASE_IDX 3 5248 #define regMPCC1_MPCC_BOT_GAIN_INSIDE 0x001c 5249 #define regMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 5250 #define regMPCC1_MPCC_BOT_GAIN_OUTSIDE 0x001d 5251 #define regMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 5252 #define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x001e 5253 #define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 5254 #define regMPCC1_MPCC_BG_R_CR 0x001f 5255 #define regMPCC1_MPCC_BG_R_CR_BASE_IDX 3 5256 #define regMPCC1_MPCC_BG_G_Y 0x0020 5257 #define regMPCC1_MPCC_BG_G_Y_BASE_IDX 3 5258 #define regMPCC1_MPCC_BG_B_CB 0x0021 5259 #define regMPCC1_MPCC_BG_B_CB_BASE_IDX 3 5260 #define regMPCC1_MPCC_MEM_PWR_CTRL 0x0022 5261 #define regMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 3 5262 #define regMPCC1_MPCC_STATUS 0x0023 5263 #define regMPCC1_MPCC_STATUS_BASE_IDX 3 5264 5265 5266 // addressBlock: dce_dc_mpc_mpcc2_dispdec 5267 // base address: 0xa8 5268 #define regMPCC2_MPCC_TOP_SEL 0x002a 5269 #define regMPCC2_MPCC_TOP_SEL_BASE_IDX 3 5270 #define regMPCC2_MPCC_BOT_SEL 0x002b 5271 #define regMPCC2_MPCC_BOT_SEL_BASE_IDX 3 5272 #define regMPCC2_MPCC_OPP_ID 0x002c 5273 #define regMPCC2_MPCC_OPP_ID_BASE_IDX 3 5274 #define regMPCC2_MPCC_CONTROL 0x002d 5275 #define regMPCC2_MPCC_CONTROL_BASE_IDX 3 5276 #define regMPCC2_MPCC_SM_CONTROL 0x002e 5277 #define regMPCC2_MPCC_SM_CONTROL_BASE_IDX 3 5278 #define regMPCC2_MPCC_UPDATE_LOCK_SEL 0x002f 5279 #define regMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 5280 #define regMPCC2_MPCC_TOP_GAIN 0x0030 5281 #define regMPCC2_MPCC_TOP_GAIN_BASE_IDX 3 5282 #define regMPCC2_MPCC_BOT_GAIN_INSIDE 0x0031 5283 #define regMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 5284 #define regMPCC2_MPCC_BOT_GAIN_OUTSIDE 0x0032 5285 #define regMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 5286 #define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x0033 5287 #define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 5288 #define regMPCC2_MPCC_BG_R_CR 0x0034 5289 #define regMPCC2_MPCC_BG_R_CR_BASE_IDX 3 5290 #define regMPCC2_MPCC_BG_G_Y 0x0035 5291 #define regMPCC2_MPCC_BG_G_Y_BASE_IDX 3 5292 #define regMPCC2_MPCC_BG_B_CB 0x0036 5293 #define regMPCC2_MPCC_BG_B_CB_BASE_IDX 3 5294 #define regMPCC2_MPCC_MEM_PWR_CTRL 0x0037 5295 #define regMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX 3 5296 #define regMPCC2_MPCC_STATUS 0x0038 5297 #define regMPCC2_MPCC_STATUS_BASE_IDX 3 5298 5299 5300 // addressBlock: dce_dc_mpc_mpcc3_dispdec 5301 // base address: 0xfc 5302 #define regMPCC3_MPCC_TOP_SEL 0x003f 5303 #define regMPCC3_MPCC_TOP_SEL_BASE_IDX 3 5304 #define regMPCC3_MPCC_BOT_SEL 0x0040 5305 #define regMPCC3_MPCC_BOT_SEL_BASE_IDX 3 5306 #define regMPCC3_MPCC_OPP_ID 0x0041 5307 #define regMPCC3_MPCC_OPP_ID_BASE_IDX 3 5308 #define regMPCC3_MPCC_CONTROL 0x0042 5309 #define regMPCC3_MPCC_CONTROL_BASE_IDX 3 5310 #define regMPCC3_MPCC_SM_CONTROL 0x0043 5311 #define regMPCC3_MPCC_SM_CONTROL_BASE_IDX 3 5312 #define regMPCC3_MPCC_UPDATE_LOCK_SEL 0x0044 5313 #define regMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 5314 #define regMPCC3_MPCC_TOP_GAIN 0x0045 5315 #define regMPCC3_MPCC_TOP_GAIN_BASE_IDX 3 5316 #define regMPCC3_MPCC_BOT_GAIN_INSIDE 0x0046 5317 #define regMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 5318 #define regMPCC3_MPCC_BOT_GAIN_OUTSIDE 0x0047 5319 #define regMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 5320 #define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x0048 5321 #define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 5322 #define regMPCC3_MPCC_BG_R_CR 0x0049 5323 #define regMPCC3_MPCC_BG_R_CR_BASE_IDX 3 5324 #define regMPCC3_MPCC_BG_G_Y 0x004a 5325 #define regMPCC3_MPCC_BG_G_Y_BASE_IDX 3 5326 #define regMPCC3_MPCC_BG_B_CB 0x004b 5327 #define regMPCC3_MPCC_BG_B_CB_BASE_IDX 3 5328 #define regMPCC3_MPCC_MEM_PWR_CTRL 0x004c 5329 #define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX 3 5330 #define regMPCC3_MPCC_STATUS 0x004d 5331 #define regMPCC3_MPCC_STATUS_BASE_IDX 3 5332 5333 5334 // addressBlock: dce_dc_mpc_mpc_cfg_dispdec 5335 // base address: 0x0 5336 #define regMPC_CLOCK_CONTROL 0x0398 5337 #define regMPC_CLOCK_CONTROL_BASE_IDX 3 5338 #define regMPC_SOFT_RESET 0x0399 5339 #define regMPC_SOFT_RESET_BASE_IDX 3 5340 #define regMPC_CRC_CTRL 0x039a 5341 #define regMPC_CRC_CTRL_BASE_IDX 3 5342 #define regMPC_CRC_SEL_CONTROL 0x039b 5343 #define regMPC_CRC_SEL_CONTROL_BASE_IDX 3 5344 #define regMPC_PERFMON_EVENT_CTRL 0x03a1 5345 #define regMPC_PERFMON_EVENT_CTRL_BASE_IDX 3 5346 #define regMPC_BYPASS_BG_AR 0x03a2 5347 #define regMPC_BYPASS_BG_AR_BASE_IDX 3 5348 #define regMPC_BYPASS_BG_GB 0x03a3 5349 #define regMPC_BYPASS_BG_GB_BASE_IDX 3 5350 #define regMPC_HOST_READ_CONTROL 0x03a4 5351 #define regMPC_HOST_READ_CONTROL_BASE_IDX 3 5352 #define regMPC_DPP_PENDING_STATUS 0x03a5 5353 #define regMPC_DPP_PENDING_STATUS_BASE_IDX 3 5354 #define regMPC_PENDING_STATUS_MISC 0x03a6 5355 #define regMPC_PENDING_STATUS_MISC_BASE_IDX 3 5356 #define regADR_CFG_CUR_VUPDATE_LOCK_SET0 0x03a7 5357 #define regADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX 3 5358 #define regADR_CFG_VUPDATE_LOCK_SET0 0x03a8 5359 #define regADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 3 5360 #define regADR_VUPDATE_LOCK_SET0 0x03a9 5361 #define regADR_VUPDATE_LOCK_SET0_BASE_IDX 3 5362 #define regCFG_VUPDATE_LOCK_SET0 0x03aa 5363 #define regCFG_VUPDATE_LOCK_SET0_BASE_IDX 3 5364 #define regCUR_VUPDATE_LOCK_SET0 0x03ab 5365 #define regCUR_VUPDATE_LOCK_SET0_BASE_IDX 3 5366 #define regADR_CFG_CUR_VUPDATE_LOCK_SET1 0x03ac 5367 #define regADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX 3 5368 #define regADR_CFG_VUPDATE_LOCK_SET1 0x03ad 5369 #define regADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 3 5370 #define regADR_VUPDATE_LOCK_SET1 0x03ae 5371 #define regADR_VUPDATE_LOCK_SET1_BASE_IDX 3 5372 #define regCFG_VUPDATE_LOCK_SET1 0x03af 5373 #define regCFG_VUPDATE_LOCK_SET1_BASE_IDX 3 5374 #define regCUR_VUPDATE_LOCK_SET1 0x03b0 5375 #define regCUR_VUPDATE_LOCK_SET1_BASE_IDX 3 5376 #define regADR_CFG_CUR_VUPDATE_LOCK_SET2 0x03b1 5377 #define regADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX 3 5378 #define regADR_CFG_VUPDATE_LOCK_SET2 0x03b2 5379 #define regADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 3 5380 #define regADR_VUPDATE_LOCK_SET2 0x03b3 5381 #define regADR_VUPDATE_LOCK_SET2_BASE_IDX 3 5382 #define regCFG_VUPDATE_LOCK_SET2 0x03b4 5383 #define regCFG_VUPDATE_LOCK_SET2_BASE_IDX 3 5384 #define regCUR_VUPDATE_LOCK_SET2 0x03b5 5385 #define regCUR_VUPDATE_LOCK_SET2_BASE_IDX 3 5386 #define regADR_CFG_CUR_VUPDATE_LOCK_SET3 0x03b6 5387 #define regADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX 3 5388 #define regADR_CFG_VUPDATE_LOCK_SET3 0x03b7 5389 #define regADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 3 5390 #define regADR_VUPDATE_LOCK_SET3 0x03b8 5391 #define regADR_VUPDATE_LOCK_SET3_BASE_IDX 3 5392 #define regCFG_VUPDATE_LOCK_SET3 0x03b9 5393 #define regCFG_VUPDATE_LOCK_SET3_BASE_IDX 3 5394 #define regCUR_VUPDATE_LOCK_SET3 0x03ba 5395 #define regCUR_VUPDATE_LOCK_SET3_BASE_IDX 3 5396 #define regMPC_CRC_RESULT_A 0x03c0 5397 #define regMPC_CRC_RESULT_A_BASE_IDX 3 5398 #define regMPC_CRC_RESULT_R 0x03c1 5399 #define regMPC_CRC_RESULT_R_BASE_IDX 3 5400 #define regMPC_CRC_RESULT_G 0x03c2 5401 #define regMPC_CRC_RESULT_G_BASE_IDX 3 5402 #define regMPC_CRC_RESULT_B 0x03c3 5403 #define regMPC_CRC_RESULT_B_BASE_IDX 3 5404 #define regMPC_DWB0_MUX 0x03c6 5405 #define regMPC_DWB0_MUX_BASE_IDX 3 5406 5407 5408 // addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec 5409 // base address: 0x17e1c 5410 #define regDC_PERFMON15_PERFCOUNTER_CNTL 0x0447 5411 #define regDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX 3 5412 #define regDC_PERFMON15_PERFCOUNTER_CNTL2 0x0448 5413 #define regDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX 3 5414 #define regDC_PERFMON15_PERFCOUNTER_STATE 0x0449 5415 #define regDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX 3 5416 #define regDC_PERFMON15_PERFMON_CNTL 0x044a 5417 #define regDC_PERFMON15_PERFMON_CNTL_BASE_IDX 3 5418 #define regDC_PERFMON15_PERFMON_CNTL2 0x044b 5419 #define regDC_PERFMON15_PERFMON_CNTL2_BASE_IDX 3 5420 #define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC 0x044c 5421 #define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 5422 #define regDC_PERFMON15_PERFMON_CVALUE_LOW 0x044d 5423 #define regDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX 3 5424 #define regDC_PERFMON15_PERFMON_HI 0x044e 5425 #define regDC_PERFMON15_PERFMON_HI_BASE_IDX 3 5426 #define regDC_PERFMON15_PERFMON_LOW 0x044f 5427 #define regDC_PERFMON15_PERFMON_LOW_BASE_IDX 3 5428 5429 5430 // addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec 5431 // base address: 0x0 5432 #define regMPCC_OGAM0_MPCC_OGAM_CONTROL 0x00a8 5433 #define regMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX 3 5434 #define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX 0x00a9 5435 #define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 5436 #define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA 0x00aa 5437 #define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX 3 5438 #define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL 0x00ab 5439 #define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 5440 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B 0x00ac 5441 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 5442 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G 0x00ad 5443 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 5444 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R 0x00ae 5445 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 5446 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x00af 5447 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 5448 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x00b0 5449 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 5450 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x00b1 5451 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 5452 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x00b2 5453 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 5454 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x00b3 5455 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 5456 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x00b4 5457 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 5458 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B 0x00b5 5459 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 5460 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B 0x00b6 5461 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 5462 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G 0x00b7 5463 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 5464 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G 0x00b8 5465 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 5466 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R 0x00b9 5467 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 5468 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R 0x00ba 5469 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 5470 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B 0x00bb 5471 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 5472 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G 0x00bc 5473 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 5474 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R 0x00bd 5475 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 5476 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 0x00be 5477 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 5478 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 0x00bf 5479 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 5480 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 0x00c0 5481 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 5482 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 0x00c1 5483 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 5484 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 0x00c2 5485 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 5486 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 0x00c3 5487 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 5488 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 0x00c4 5489 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 5490 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 0x00c5 5491 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 5492 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 0x00c6 5493 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 5494 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 0x00c7 5495 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 5496 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 0x00c8 5497 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 5498 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 0x00c9 5499 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 5500 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 0x00ca 5501 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 5502 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 0x00cb 5503 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 5504 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 0x00cc 5505 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 5506 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 0x00cd 5507 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 5508 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 0x00ce 5509 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 5510 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B 0x00cf 5511 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 5512 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G 0x00d0 5513 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 5514 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R 0x00d1 5515 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 5516 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x00d2 5517 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 5518 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x00d3 5519 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 5520 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x00d4 5521 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 5522 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x00d5 5523 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 5524 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x00d6 5525 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 5526 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x00d7 5527 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 5528 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B 0x00d8 5529 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 5530 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B 0x00d9 5531 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 5532 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G 0x00da 5533 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 5534 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G 0x00db 5535 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 5536 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R 0x00dc 5537 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 5538 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R 0x00dd 5539 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 5540 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B 0x00de 5541 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 5542 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G 0x00df 5543 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 5544 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R 0x00e0 5545 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 5546 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 0x00e1 5547 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 5548 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 0x00e2 5549 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 5550 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 0x00e3 5551 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 5552 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 0x00e4 5553 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 5554 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 0x00e5 5555 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 5556 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 0x00e6 5557 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 5558 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 0x00e7 5559 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 5560 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 0x00e8 5561 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 5562 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 0x00e9 5563 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 5564 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 0x00ea 5565 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 5566 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 0x00eb 5567 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 5568 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 0x00ec 5569 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 5570 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 0x00ed 5571 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 5572 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 0x00ee 5573 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 5574 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 0x00ef 5575 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 5576 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 0x00f0 5577 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 5578 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 0x00f1 5579 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 5580 #define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT 0x00f2 5581 #define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 5582 #define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE 0x00f3 5583 #define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 5584 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A 0x00f4 5585 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 5586 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A 0x00f5 5587 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 5588 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A 0x00f6 5589 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 5590 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A 0x00f7 5591 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 5592 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A 0x00f8 5593 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 5594 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A 0x00f9 5595 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 5596 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B 0x00fa 5597 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 5598 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B 0x00fb 5599 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 5600 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B 0x00fc 5601 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 5602 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B 0x00fd 5603 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 5604 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B 0x00fe 5605 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 5606 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B 0x00ff 5607 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 5608 5609 5610 // addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec 5611 // base address: 0x178 5612 #define regMPCC_OGAM1_MPCC_OGAM_CONTROL 0x0106 5613 #define regMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX 3 5614 #define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX 0x0107 5615 #define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 5616 #define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA 0x0108 5617 #define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX 3 5618 #define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL 0x0109 5619 #define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 5620 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B 0x010a 5621 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 5622 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G 0x010b 5623 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 5624 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R 0x010c 5625 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 5626 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x010d 5627 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 5628 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x010e 5629 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 5630 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x010f 5631 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 5632 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x0110 5633 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 5634 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x0111 5635 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 5636 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x0112 5637 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 5638 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B 0x0113 5639 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 5640 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B 0x0114 5641 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 5642 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G 0x0115 5643 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 5644 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G 0x0116 5645 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 5646 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R 0x0117 5647 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 5648 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R 0x0118 5649 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 5650 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B 0x0119 5651 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 5652 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G 0x011a 5653 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 5654 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R 0x011b 5655 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 5656 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 0x011c 5657 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 5658 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 0x011d 5659 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 5660 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 0x011e 5661 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 5662 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 0x011f 5663 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 5664 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 0x0120 5665 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 5666 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 0x0121 5667 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 5668 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 0x0122 5669 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 5670 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 0x0123 5671 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 5672 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 0x0124 5673 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 5674 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 0x0125 5675 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 5676 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 0x0126 5677 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 5678 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 0x0127 5679 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 5680 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 0x0128 5681 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 5682 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 0x0129 5683 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 5684 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 0x012a 5685 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 5686 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 0x012b 5687 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 5688 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 0x012c 5689 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 5690 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B 0x012d 5691 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 5692 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G 0x012e 5693 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 5694 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R 0x012f 5695 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 5696 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x0130 5697 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 5698 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x0131 5699 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 5700 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x0132 5701 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 5702 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x0133 5703 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 5704 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x0134 5705 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 5706 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x0135 5707 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 5708 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B 0x0136 5709 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 5710 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B 0x0137 5711 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 5712 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G 0x0138 5713 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 5714 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G 0x0139 5715 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 5716 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R 0x013a 5717 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 5718 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R 0x013b 5719 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 5720 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B 0x013c 5721 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 5722 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G 0x013d 5723 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 5724 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R 0x013e 5725 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 5726 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 0x013f 5727 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 5728 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 0x0140 5729 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 5730 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 0x0141 5731 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 5732 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 0x0142 5733 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 5734 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 0x0143 5735 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 5736 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 0x0144 5737 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 5738 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 0x0145 5739 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 5740 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 0x0146 5741 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 5742 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 0x0147 5743 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 5744 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 0x0148 5745 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 5746 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 0x0149 5747 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 5748 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 0x014a 5749 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 5750 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 0x014b 5751 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 5752 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 0x014c 5753 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 5754 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 0x014d 5755 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 5756 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 0x014e 5757 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 5758 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 0x014f 5759 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 5760 #define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT 0x0150 5761 #define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 5762 #define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE 0x0151 5763 #define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 5764 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A 0x0152 5765 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 5766 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A 0x0153 5767 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 5768 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A 0x0154 5769 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 5770 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A 0x0155 5771 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 5772 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A 0x0156 5773 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 5774 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A 0x0157 5775 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 5776 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B 0x0158 5777 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 5778 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B 0x0159 5779 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 5780 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B 0x015a 5781 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 5782 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B 0x015b 5783 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 5784 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B 0x015c 5785 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 5786 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B 0x015d 5787 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 5788 5789 5790 // addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec 5791 // base address: 0x2f0 5792 #define regMPCC_OGAM2_MPCC_OGAM_CONTROL 0x0164 5793 #define regMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX 3 5794 #define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX 0x0165 5795 #define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 5796 #define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA 0x0166 5797 #define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX 3 5798 #define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL 0x0167 5799 #define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 5800 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B 0x0168 5801 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 5802 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G 0x0169 5803 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 5804 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R 0x016a 5805 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 5806 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x016b 5807 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 5808 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x016c 5809 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 5810 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x016d 5811 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 5812 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x016e 5813 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 5814 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x016f 5815 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 5816 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x0170 5817 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 5818 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B 0x0171 5819 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 5820 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B 0x0172 5821 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 5822 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G 0x0173 5823 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 5824 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G 0x0174 5825 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 5826 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R 0x0175 5827 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 5828 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R 0x0176 5829 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 5830 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B 0x0177 5831 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 5832 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G 0x0178 5833 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 5834 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R 0x0179 5835 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 5836 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 0x017a 5837 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 5838 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 0x017b 5839 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 5840 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 0x017c 5841 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 5842 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 0x017d 5843 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 5844 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 0x017e 5845 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 5846 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 0x017f 5847 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 5848 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 0x0180 5849 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 5850 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 0x0181 5851 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 5852 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 0x0182 5853 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 5854 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 0x0183 5855 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 5856 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 0x0184 5857 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 5858 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 0x0185 5859 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 5860 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 0x0186 5861 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 5862 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 0x0187 5863 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 5864 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 0x0188 5865 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 5866 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 0x0189 5867 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 5868 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 0x018a 5869 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 5870 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B 0x018b 5871 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 5872 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G 0x018c 5873 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 5874 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R 0x018d 5875 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 5876 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x018e 5877 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 5878 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x018f 5879 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 5880 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x0190 5881 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 5882 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x0191 5883 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 5884 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x0192 5885 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 5886 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x0193 5887 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 5888 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B 0x0194 5889 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 5890 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B 0x0195 5891 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 5892 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G 0x0196 5893 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 5894 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G 0x0197 5895 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 5896 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R 0x0198 5897 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 5898 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R 0x0199 5899 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 5900 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B 0x019a 5901 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 5902 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G 0x019b 5903 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 5904 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R 0x019c 5905 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 5906 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 0x019d 5907 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 5908 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 0x019e 5909 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 5910 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 0x019f 5911 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 5912 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 0x01a0 5913 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 5914 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 0x01a1 5915 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 5916 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 0x01a2 5917 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 5918 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 0x01a3 5919 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 5920 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 0x01a4 5921 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 5922 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 0x01a5 5923 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 5924 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 0x01a6 5925 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 5926 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 0x01a7 5927 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 5928 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 0x01a8 5929 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 5930 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 0x01a9 5931 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 5932 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 0x01aa 5933 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 5934 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 0x01ab 5935 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 5936 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 0x01ac 5937 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 5938 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 0x01ad 5939 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 5940 #define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT 0x01ae 5941 #define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 5942 #define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE 0x01af 5943 #define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 5944 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A 0x01b0 5945 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 5946 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A 0x01b1 5947 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 5948 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A 0x01b2 5949 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 5950 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A 0x01b3 5951 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 5952 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A 0x01b4 5953 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 5954 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A 0x01b5 5955 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 5956 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B 0x01b6 5957 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 5958 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B 0x01b7 5959 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 5960 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B 0x01b8 5961 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 5962 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B 0x01b9 5963 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 5964 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B 0x01ba 5965 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 5966 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B 0x01bb 5967 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 5968 5969 5970 // addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec 5971 // base address: 0x468 5972 #define regMPCC_OGAM3_MPCC_OGAM_CONTROL 0x01c2 5973 #define regMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX 3 5974 #define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX 0x01c3 5975 #define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 5976 #define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA 0x01c4 5977 #define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX 3 5978 #define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL 0x01c5 5979 #define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 5980 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B 0x01c6 5981 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 5982 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G 0x01c7 5983 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 5984 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R 0x01c8 5985 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 5986 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x01c9 5987 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 5988 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x01ca 5989 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 5990 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x01cb 5991 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 5992 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x01cc 5993 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 5994 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x01cd 5995 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 5996 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x01ce 5997 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 5998 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B 0x01cf 5999 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 6000 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B 0x01d0 6001 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 6002 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G 0x01d1 6003 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 6004 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G 0x01d2 6005 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 6006 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R 0x01d3 6007 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 6008 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R 0x01d4 6009 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 6010 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B 0x01d5 6011 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 6012 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G 0x01d6 6013 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 6014 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R 0x01d7 6015 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 6016 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 0x01d8 6017 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 6018 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 0x01d9 6019 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 6020 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 0x01da 6021 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 6022 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 0x01db 6023 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 6024 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 0x01dc 6025 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 6026 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 0x01dd 6027 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 6028 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 0x01de 6029 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 6030 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 0x01df 6031 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 6032 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 0x01e0 6033 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 6034 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 0x01e1 6035 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 6036 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 0x01e2 6037 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 6038 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 0x01e3 6039 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 6040 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 0x01e4 6041 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 6042 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 0x01e5 6043 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 6044 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 0x01e6 6045 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 6046 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 0x01e7 6047 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 6048 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 0x01e8 6049 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 6050 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B 0x01e9 6051 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 6052 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G 0x01ea 6053 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 6054 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R 0x01eb 6055 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 6056 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x01ec 6057 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 6058 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x01ed 6059 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 6060 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x01ee 6061 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 6062 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x01ef 6063 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 6064 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x01f0 6065 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 6066 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x01f1 6067 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 6068 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B 0x01f2 6069 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 6070 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B 0x01f3 6071 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 6072 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G 0x01f4 6073 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 6074 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G 0x01f5 6075 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 6076 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R 0x01f6 6077 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 6078 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R 0x01f7 6079 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 6080 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B 0x01f8 6081 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 6082 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G 0x01f9 6083 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 6084 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R 0x01fa 6085 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 6086 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 0x01fb 6087 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 6088 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 0x01fc 6089 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 6090 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 0x01fd 6091 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 6092 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 0x01fe 6093 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 6094 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 0x01ff 6095 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 6096 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 0x0200 6097 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 6098 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 0x0201 6099 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 6100 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 0x0202 6101 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 6102 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 0x0203 6103 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 6104 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 0x0204 6105 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 6106 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 0x0205 6107 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 6108 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 0x0206 6109 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 6110 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 0x0207 6111 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 6112 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 0x0208 6113 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 6114 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 0x0209 6115 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 6116 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 0x020a 6117 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 6118 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 0x020b 6119 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 6120 #define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT 0x020c 6121 #define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 6122 #define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE 0x020d 6123 #define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 6124 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A 0x020e 6125 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 6126 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A 0x020f 6127 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 6128 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A 0x0210 6129 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 6130 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A 0x0211 6131 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 6132 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A 0x0212 6133 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 6134 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A 0x0213 6135 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 6136 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B 0x0214 6137 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 6138 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B 0x0215 6139 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 6140 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B 0x0216 6141 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 6142 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B 0x0217 6143 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 6144 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B 0x0218 6145 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 6146 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B 0x0219 6147 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 6148 6149 6150 // addressBlock: dce_dc_mpc_mpcc_mcm0_dispdec 6151 // base address: 0x0 6152 #define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL 0x0453 6153 #define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 6154 #define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R 0x0454 6155 #define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 6156 #define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G 0x0455 6157 #define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 6158 #define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B 0x0456 6159 #define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 6160 #define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R 0x0457 6161 #define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 6162 #define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B 0x0458 6163 #define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 6164 #define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX 0x0459 6165 #define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 6166 #define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA 0x045a 6167 #define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 6168 #define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x045b 6169 #define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 6170 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x045c 6171 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 6172 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x045d 6173 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 6174 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x045e 6175 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 6176 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x045f 6177 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 6178 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x0460 6179 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 6180 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x0461 6181 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 6182 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x0462 6183 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 6184 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x0463 6185 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 6186 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x0464 6187 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 6188 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x0465 6189 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 6190 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x0466 6191 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 6192 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x0467 6193 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 6194 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x0468 6195 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 6196 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x0469 6197 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 6198 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x046a 6199 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 6200 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x046b 6201 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 6202 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x046c 6203 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 6204 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x046d 6205 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 6206 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x046e 6207 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 6208 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x046f 6209 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 6210 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0470 6211 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 6212 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0471 6213 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 6214 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0472 6215 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 6216 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0473 6217 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 6218 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0474 6219 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 6220 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0475 6221 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 6222 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0476 6223 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 6224 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0477 6225 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 6226 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0478 6227 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 6228 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0479 6229 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 6230 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x047a 6231 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 6232 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x047b 6233 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 6234 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x047c 6235 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 6236 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x047d 6237 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 6238 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x047e 6239 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 6240 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x047f 6241 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 6242 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x0480 6243 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 6244 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x0481 6245 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 6246 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x0482 6247 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 6248 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x0483 6249 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 6250 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x0484 6251 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 6252 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x0485 6253 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 6254 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x0486 6255 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 6256 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x0487 6257 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 6258 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x0488 6259 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 6260 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x0489 6261 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 6262 #define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE 0x048a 6263 #define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 6264 #define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX 0x048b 6265 #define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 6266 #define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA 0x048c 6267 #define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 6268 #define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT 0x048d 6269 #define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 6270 #define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x048e 6271 #define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 6272 #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x048f 6273 #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 6274 #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x0490 6275 #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 6276 #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x0491 6277 #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 6278 #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x0492 6279 #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 6280 #define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL 0x0493 6281 #define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 6282 #define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX 0x0494 6283 #define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 6284 #define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA 0x0495 6285 #define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 6286 #define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL 0x0496 6287 #define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 6288 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x0497 6289 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 6290 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x0498 6291 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 6292 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x0499 6293 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 6294 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x049a 6295 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 6296 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x049b 6297 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 6298 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x049c 6299 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 6300 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x049d 6301 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 6302 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x049e 6303 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 6304 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x049f 6305 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 6306 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x04a0 6307 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 6308 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x04a1 6309 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 6310 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x04a2 6311 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 6312 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x04a3 6313 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 6314 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x04a4 6315 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 6316 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x04a5 6317 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 6318 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x04a6 6319 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 6320 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x04a7 6321 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 6322 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x04a8 6323 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 6324 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x04a9 6325 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 6326 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x04aa 6327 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 6328 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x04ab 6329 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 6330 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x04ac 6331 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 6332 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x04ad 6333 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 6334 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x04ae 6335 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 6336 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x04af 6337 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 6338 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x04b0 6339 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 6340 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x04b1 6341 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 6342 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x04b2 6343 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 6344 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x04b3 6345 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 6346 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x04b4 6347 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 6348 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x04b5 6349 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 6350 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x04b6 6351 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 6352 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x04b7 6353 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 6354 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x04b8 6355 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 6356 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x04b9 6357 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 6358 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x04ba 6359 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 6360 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x04bb 6361 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 6362 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x04bc 6363 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 6364 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x04bd 6365 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 6366 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x04be 6367 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 6368 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x04bf 6369 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 6370 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x04c0 6371 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 6372 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x04c1 6373 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 6374 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x04c2 6375 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 6376 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x04c3 6377 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 6378 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x04c4 6379 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 6380 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x04c5 6381 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 6382 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x04c6 6383 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 6384 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x04c7 6385 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 6386 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x04c8 6387 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 6388 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x04c9 6389 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 6390 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x04ca 6391 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 6392 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x04cb 6393 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 6394 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x04cc 6395 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 6396 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x04cd 6397 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 6398 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x04ce 6399 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 6400 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x04cf 6401 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 6402 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x04d0 6403 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 6404 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x04d1 6405 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 6406 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x04d2 6407 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 6408 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x04d3 6409 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 6410 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x04d4 6411 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 6412 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x04d5 6413 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 6414 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x04d6 6415 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 6416 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x04d7 6417 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 6418 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x04d8 6419 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 6420 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x04d9 6421 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 6422 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x04da 6423 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 6424 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x04db 6425 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 6426 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x04dc 6427 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 6428 #define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL 0x04dd 6429 #define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 6430 6431 6432 // addressBlock: dce_dc_mpc_mpcc_mcm1_dispdec 6433 // base address: 0x240 6434 #define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL 0x04e3 6435 #define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 6436 #define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R 0x04e4 6437 #define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 6438 #define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G 0x04e5 6439 #define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 6440 #define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B 0x04e6 6441 #define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 6442 #define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R 0x04e7 6443 #define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 6444 #define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B 0x04e8 6445 #define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 6446 #define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX 0x04e9 6447 #define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 6448 #define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA 0x04ea 6449 #define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 6450 #define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x04eb 6451 #define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 6452 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x04ec 6453 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 6454 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x04ed 6455 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 6456 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x04ee 6457 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 6458 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x04ef 6459 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 6460 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x04f0 6461 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 6462 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x04f1 6463 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 6464 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x04f2 6465 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 6466 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x04f3 6467 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 6468 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x04f4 6469 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 6470 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x04f5 6471 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 6472 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x04f6 6473 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 6474 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x04f7 6475 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 6476 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x04f8 6477 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 6478 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x04f9 6479 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 6480 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x04fa 6481 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 6482 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x04fb 6483 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 6484 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x04fc 6485 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 6486 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x04fd 6487 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 6488 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x04fe 6489 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 6490 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x04ff 6491 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 6492 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0500 6493 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 6494 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0501 6495 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 6496 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0502 6497 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 6498 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0503 6499 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 6500 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0504 6501 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 6502 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0505 6503 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 6504 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0506 6505 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 6506 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0507 6507 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 6508 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0508 6509 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 6510 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0509 6511 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 6512 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x050a 6513 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 6514 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x050b 6515 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 6516 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x050c 6517 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 6518 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x050d 6519 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 6520 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x050e 6521 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 6522 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x050f 6523 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 6524 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x0510 6525 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 6526 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x0511 6527 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 6528 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x0512 6529 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 6530 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x0513 6531 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 6532 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x0514 6533 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 6534 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x0515 6535 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 6536 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x0516 6537 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 6538 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x0517 6539 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 6540 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x0518 6541 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 6542 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x0519 6543 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 6544 #define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE 0x051a 6545 #define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 6546 #define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX 0x051b 6547 #define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 6548 #define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA 0x051c 6549 #define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 6550 #define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT 0x051d 6551 #define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 6552 #define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x051e 6553 #define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 6554 #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x051f 6555 #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 6556 #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x0520 6557 #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 6558 #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x0521 6559 #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 6560 #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x0522 6561 #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 6562 #define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL 0x0523 6563 #define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 6564 #define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX 0x0524 6565 #define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 6566 #define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA 0x0525 6567 #define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 6568 #define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL 0x0526 6569 #define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 6570 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x0527 6571 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 6572 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x0528 6573 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 6574 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x0529 6575 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 6576 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x052a 6577 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 6578 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x052b 6579 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 6580 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x052c 6581 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 6582 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x052d 6583 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 6584 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x052e 6585 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 6586 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x052f 6587 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 6588 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x0530 6589 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 6590 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x0531 6591 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 6592 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x0532 6593 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 6594 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x0533 6595 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 6596 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x0534 6597 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 6598 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x0535 6599 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 6600 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x0536 6601 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 6602 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x0537 6603 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 6604 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x0538 6605 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 6606 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x0539 6607 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 6608 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x053a 6609 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 6610 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x053b 6611 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 6612 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x053c 6613 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 6614 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x053d 6615 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 6616 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x053e 6617 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 6618 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x053f 6619 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 6620 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x0540 6621 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 6622 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x0541 6623 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 6624 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x0542 6625 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 6626 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x0543 6627 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 6628 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x0544 6629 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 6630 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x0545 6631 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 6632 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x0546 6633 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 6634 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x0547 6635 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 6636 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x0548 6637 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 6638 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x0549 6639 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 6640 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x054a 6641 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 6642 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x054b 6643 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 6644 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x054c 6645 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 6646 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x054d 6647 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 6648 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x054e 6649 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 6650 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x054f 6651 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 6652 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x0550 6653 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 6654 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x0551 6655 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 6656 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x0552 6657 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 6658 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x0553 6659 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 6660 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x0554 6661 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 6662 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x0555 6663 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 6664 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x0556 6665 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 6666 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x0557 6667 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 6668 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x0558 6669 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 6670 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x0559 6671 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 6672 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x055a 6673 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 6674 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x055b 6675 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 6676 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x055c 6677 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 6678 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x055d 6679 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 6680 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x055e 6681 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 6682 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x055f 6683 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 6684 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x0560 6685 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 6686 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x0561 6687 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 6688 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x0562 6689 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 6690 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x0563 6691 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 6692 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x0564 6693 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 6694 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x0565 6695 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 6696 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x0566 6697 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 6698 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x0567 6699 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 6700 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x0568 6701 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 6702 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x0569 6703 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 6704 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x056a 6705 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 6706 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x056b 6707 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 6708 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x056c 6709 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 6710 #define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL 0x056d 6711 #define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 6712 6713 6714 // addressBlock: dce_dc_mpc_mpcc_mcm2_dispdec 6715 // base address: 0x480 6716 #define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL 0x0573 6717 #define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 6718 #define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R 0x0574 6719 #define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 6720 #define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G 0x0575 6721 #define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 6722 #define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B 0x0576 6723 #define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 6724 #define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R 0x0577 6725 #define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 6726 #define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B 0x0578 6727 #define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 6728 #define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX 0x0579 6729 #define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 6730 #define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA 0x057a 6731 #define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 6732 #define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x057b 6733 #define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 6734 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x057c 6735 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 6736 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x057d 6737 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 6738 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x057e 6739 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 6740 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x057f 6741 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 6742 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x0580 6743 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 6744 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x0581 6745 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 6746 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x0582 6747 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 6748 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x0583 6749 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 6750 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x0584 6751 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 6752 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x0585 6753 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 6754 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x0586 6755 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 6756 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x0587 6757 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 6758 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x0588 6759 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 6760 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x0589 6761 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 6762 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x058a 6763 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 6764 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x058b 6765 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 6766 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x058c 6767 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 6768 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x058d 6769 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 6770 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x058e 6771 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 6772 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x058f 6773 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 6774 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0590 6775 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 6776 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0591 6777 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 6778 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0592 6779 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 6780 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0593 6781 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 6782 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0594 6783 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 6784 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0595 6785 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 6786 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0596 6787 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 6788 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0597 6789 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 6790 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0598 6791 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 6792 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0599 6793 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 6794 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x059a 6795 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 6796 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x059b 6797 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 6798 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x059c 6799 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 6800 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x059d 6801 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 6802 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x059e 6803 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 6804 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x059f 6805 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 6806 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x05a0 6807 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 6808 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x05a1 6809 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 6810 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x05a2 6811 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 6812 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x05a3 6813 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 6814 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x05a4 6815 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 6816 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x05a5 6817 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 6818 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x05a6 6819 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 6820 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x05a7 6821 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 6822 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x05a8 6823 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 6824 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x05a9 6825 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 6826 #define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE 0x05aa 6827 #define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 6828 #define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX 0x05ab 6829 #define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 6830 #define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA 0x05ac 6831 #define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 6832 #define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT 0x05ad 6833 #define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 6834 #define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x05ae 6835 #define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 6836 #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x05af 6837 #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 6838 #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x05b0 6839 #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 6840 #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x05b1 6841 #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 6842 #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x05b2 6843 #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 6844 #define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL 0x05b3 6845 #define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 6846 #define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX 0x05b4 6847 #define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 6848 #define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA 0x05b5 6849 #define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 6850 #define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL 0x05b6 6851 #define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 6852 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x05b7 6853 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 6854 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x05b8 6855 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 6856 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x05b9 6857 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 6858 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x05ba 6859 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 6860 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x05bb 6861 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 6862 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x05bc 6863 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 6864 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x05bd 6865 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 6866 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x05be 6867 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 6868 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x05bf 6869 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 6870 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x05c0 6871 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 6872 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x05c1 6873 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 6874 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x05c2 6875 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 6876 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x05c3 6877 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 6878 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x05c4 6879 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 6880 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x05c5 6881 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 6882 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x05c6 6883 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 6884 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x05c7 6885 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 6886 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x05c8 6887 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 6888 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x05c9 6889 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 6890 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x05ca 6891 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 6892 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x05cb 6893 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 6894 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x05cc 6895 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 6896 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x05cd 6897 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 6898 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x05ce 6899 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 6900 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x05cf 6901 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 6902 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x05d0 6903 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 6904 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x05d1 6905 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 6906 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x05d2 6907 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 6908 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x05d3 6909 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 6910 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x05d4 6911 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 6912 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x05d5 6913 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 6914 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x05d6 6915 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 6916 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x05d7 6917 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 6918 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x05d8 6919 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 6920 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x05d9 6921 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 6922 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x05da 6923 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 6924 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x05db 6925 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 6926 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x05dc 6927 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 6928 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x05dd 6929 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 6930 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x05de 6931 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 6932 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x05df 6933 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 6934 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x05e0 6935 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 6936 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x05e1 6937 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 6938 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x05e2 6939 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 6940 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x05e3 6941 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 6942 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x05e4 6943 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 6944 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x05e5 6945 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 6946 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x05e6 6947 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 6948 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x05e7 6949 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 6950 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x05e8 6951 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 6952 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x05e9 6953 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 6954 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x05ea 6955 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 6956 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x05eb 6957 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 6958 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x05ec 6959 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 6960 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x05ed 6961 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 6962 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x05ee 6963 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 6964 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x05ef 6965 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 6966 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x05f0 6967 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 6968 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x05f1 6969 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 6970 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x05f2 6971 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 6972 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x05f3 6973 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 6974 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x05f4 6975 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 6976 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x05f5 6977 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 6978 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x05f6 6979 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 6980 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x05f7 6981 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 6982 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x05f8 6983 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 6984 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x05f9 6985 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 6986 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x05fa 6987 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 6988 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x05fb 6989 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 6990 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x05fc 6991 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 6992 #define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL 0x05fd 6993 #define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 6994 6995 6996 // addressBlock: dce_dc_mpc_mpcc_mcm3_dispdec 6997 // base address: 0x6c0 6998 #define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL 0x0603 6999 #define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 7000 #define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R 0x0604 7001 #define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 7002 #define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G 0x0605 7003 #define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 7004 #define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B 0x0606 7005 #define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 7006 #define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R 0x0607 7007 #define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 7008 #define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B 0x0608 7009 #define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 7010 #define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX 0x0609 7011 #define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 7012 #define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA 0x060a 7013 #define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 7014 #define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x060b 7015 #define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 7016 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x060c 7017 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 7018 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x060d 7019 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 7020 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x060e 7021 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 7022 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x060f 7023 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 7024 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x0610 7025 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 7026 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x0611 7027 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 7028 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x0612 7029 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 7030 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x0613 7031 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 7032 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x0614 7033 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 7034 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x0615 7035 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 7036 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x0616 7037 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 7038 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x0617 7039 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 7040 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x0618 7041 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 7042 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x0619 7043 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 7044 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x061a 7045 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 7046 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x061b 7047 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 7048 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x061c 7049 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 7050 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x061d 7051 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 7052 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x061e 7053 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 7054 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x061f 7055 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 7056 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0620 7057 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 7058 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0621 7059 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 7060 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0622 7061 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 7062 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0623 7063 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 7064 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0624 7065 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 7066 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0625 7067 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 7068 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0626 7069 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 7070 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0627 7071 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 7072 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0628 7073 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 7074 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0629 7075 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 7076 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x062a 7077 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 7078 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x062b 7079 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 7080 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x062c 7081 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 7082 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x062d 7083 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 7084 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x062e 7085 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 7086 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x062f 7087 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 7088 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x0630 7089 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 7090 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x0631 7091 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 7092 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x0632 7093 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 7094 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x0633 7095 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 7096 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x0634 7097 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 7098 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x0635 7099 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 7100 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x0636 7101 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 7102 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x0637 7103 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 7104 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x0638 7105 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 7106 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x0639 7107 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 7108 #define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE 0x063a 7109 #define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 7110 #define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX 0x063b 7111 #define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 7112 #define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA 0x063c 7113 #define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 7114 #define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT 0x063d 7115 #define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 7116 #define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x063e 7117 #define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 7118 #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x063f 7119 #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 7120 #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x0640 7121 #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 7122 #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x0641 7123 #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 7124 #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x0642 7125 #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 7126 #define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL 0x0643 7127 #define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 7128 #define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX 0x0644 7129 #define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 7130 #define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA 0x0645 7131 #define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 7132 #define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL 0x0646 7133 #define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 7134 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x0647 7135 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 7136 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x0648 7137 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 7138 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x0649 7139 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 7140 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x064a 7141 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 7142 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x064b 7143 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 7144 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x064c 7145 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 7146 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x064d 7147 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 7148 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x064e 7149 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 7150 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x064f 7151 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 7152 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x0650 7153 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 7154 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x0651 7155 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 7156 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x0652 7157 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 7158 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x0653 7159 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 7160 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x0654 7161 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 7162 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x0655 7163 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 7164 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x0656 7165 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 7166 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x0657 7167 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 7168 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x0658 7169 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 7170 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x0659 7171 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 7172 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x065a 7173 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 7174 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x065b 7175 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 7176 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x065c 7177 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 7178 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x065d 7179 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 7180 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x065e 7181 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 7182 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x065f 7183 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 7184 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x0660 7185 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 7186 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x0661 7187 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 7188 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x0662 7189 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 7190 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x0663 7191 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 7192 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x0664 7193 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 7194 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x0665 7195 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 7196 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x0666 7197 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 7198 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x0667 7199 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 7200 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x0668 7201 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 7202 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x0669 7203 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 7204 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x066a 7205 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 7206 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x066b 7207 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 7208 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x066c 7209 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 7210 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x066d 7211 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 7212 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x066e 7213 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 7214 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x066f 7215 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 7216 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x0670 7217 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 7218 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x0671 7219 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 7220 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x0672 7221 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 7222 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x0673 7223 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 7224 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x0674 7225 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 7226 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x0675 7227 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 7228 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x0676 7229 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 7230 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x0677 7231 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 7232 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x0678 7233 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 7234 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x0679 7235 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 7236 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x067a 7237 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 7238 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x067b 7239 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 7240 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x067c 7241 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 7242 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x067d 7243 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 7244 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x067e 7245 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 7246 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x067f 7247 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 7248 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x0680 7249 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 7250 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x0681 7251 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 7252 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x0682 7253 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 7254 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x0683 7255 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 7256 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x0684 7257 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 7258 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x0685 7259 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 7260 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x0686 7261 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 7262 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x0687 7263 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 7264 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x0688 7265 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 7266 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x0689 7267 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 7268 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x068a 7269 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 7270 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x068b 7271 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 7272 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x068c 7273 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 7274 #define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL 0x068d 7275 #define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 7276 7277 7278 // addressBlock: dce_dc_mpc_mpc_ocsc_dispdec 7279 // base address: 0x0 7280 #define regMPC_OUT0_MUX 0x03d8 7281 #define regMPC_OUT0_MUX_BASE_IDX 3 7282 #define regMPC_OUT0_DENORM_CONTROL 0x03d9 7283 #define regMPC_OUT0_DENORM_CONTROL_BASE_IDX 3 7284 #define regMPC_OUT0_DENORM_CLAMP_G_Y 0x03da 7285 #define regMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX 3 7286 #define regMPC_OUT0_DENORM_CLAMP_B_CB 0x03db 7287 #define regMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX 3 7288 #define regMPC_OUT1_MUX 0x03dc 7289 #define regMPC_OUT1_MUX_BASE_IDX 3 7290 #define regMPC_OUT1_DENORM_CONTROL 0x03dd 7291 #define regMPC_OUT1_DENORM_CONTROL_BASE_IDX 3 7292 #define regMPC_OUT1_DENORM_CLAMP_G_Y 0x03de 7293 #define regMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX 3 7294 #define regMPC_OUT1_DENORM_CLAMP_B_CB 0x03df 7295 #define regMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX 3 7296 #define regMPC_OUT2_MUX 0x03e0 7297 #define regMPC_OUT2_MUX_BASE_IDX 3 7298 #define regMPC_OUT2_DENORM_CONTROL 0x03e1 7299 #define regMPC_OUT2_DENORM_CONTROL_BASE_IDX 3 7300 #define regMPC_OUT2_DENORM_CLAMP_G_Y 0x03e2 7301 #define regMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX 3 7302 #define regMPC_OUT2_DENORM_CLAMP_B_CB 0x03e3 7303 #define regMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX 3 7304 #define regMPC_OUT3_MUX 0x03e4 7305 #define regMPC_OUT3_MUX_BASE_IDX 3 7306 #define regMPC_OUT3_DENORM_CONTROL 0x03e5 7307 #define regMPC_OUT3_DENORM_CONTROL_BASE_IDX 3 7308 #define regMPC_OUT3_DENORM_CLAMP_G_Y 0x03e6 7309 #define regMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX 3 7310 #define regMPC_OUT3_DENORM_CLAMP_B_CB 0x03e7 7311 #define regMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX 3 7312 #define regMPC_OUT_CSC_COEF_FORMAT 0x03f0 7313 #define regMPC_OUT_CSC_COEF_FORMAT_BASE_IDX 3 7314 #define regMPC_OUT0_CSC_MODE 0x03f1 7315 #define regMPC_OUT0_CSC_MODE_BASE_IDX 3 7316 #define regMPC_OUT0_CSC_C11_C12_A 0x03f2 7317 #define regMPC_OUT0_CSC_C11_C12_A_BASE_IDX 3 7318 #define regMPC_OUT0_CSC_C13_C14_A 0x03f3 7319 #define regMPC_OUT0_CSC_C13_C14_A_BASE_IDX 3 7320 #define regMPC_OUT0_CSC_C21_C22_A 0x03f4 7321 #define regMPC_OUT0_CSC_C21_C22_A_BASE_IDX 3 7322 #define regMPC_OUT0_CSC_C23_C24_A 0x03f5 7323 #define regMPC_OUT0_CSC_C23_C24_A_BASE_IDX 3 7324 #define regMPC_OUT0_CSC_C31_C32_A 0x03f6 7325 #define regMPC_OUT0_CSC_C31_C32_A_BASE_IDX 3 7326 #define regMPC_OUT0_CSC_C33_C34_A 0x03f7 7327 #define regMPC_OUT0_CSC_C33_C34_A_BASE_IDX 3 7328 #define regMPC_OUT0_CSC_C11_C12_B 0x03f8 7329 #define regMPC_OUT0_CSC_C11_C12_B_BASE_IDX 3 7330 #define regMPC_OUT0_CSC_C13_C14_B 0x03f9 7331 #define regMPC_OUT0_CSC_C13_C14_B_BASE_IDX 3 7332 #define regMPC_OUT0_CSC_C21_C22_B 0x03fa 7333 #define regMPC_OUT0_CSC_C21_C22_B_BASE_IDX 3 7334 #define regMPC_OUT0_CSC_C23_C24_B 0x03fb 7335 #define regMPC_OUT0_CSC_C23_C24_B_BASE_IDX 3 7336 #define regMPC_OUT0_CSC_C31_C32_B 0x03fc 7337 #define regMPC_OUT0_CSC_C31_C32_B_BASE_IDX 3 7338 #define regMPC_OUT0_CSC_C33_C34_B 0x03fd 7339 #define regMPC_OUT0_CSC_C33_C34_B_BASE_IDX 3 7340 #define regMPC_OUT1_CSC_MODE 0x03fe 7341 #define regMPC_OUT1_CSC_MODE_BASE_IDX 3 7342 #define regMPC_OUT1_CSC_C11_C12_A 0x03ff 7343 #define regMPC_OUT1_CSC_C11_C12_A_BASE_IDX 3 7344 #define regMPC_OUT1_CSC_C13_C14_A 0x0400 7345 #define regMPC_OUT1_CSC_C13_C14_A_BASE_IDX 3 7346 #define regMPC_OUT1_CSC_C21_C22_A 0x0401 7347 #define regMPC_OUT1_CSC_C21_C22_A_BASE_IDX 3 7348 #define regMPC_OUT1_CSC_C23_C24_A 0x0402 7349 #define regMPC_OUT1_CSC_C23_C24_A_BASE_IDX 3 7350 #define regMPC_OUT1_CSC_C31_C32_A 0x0403 7351 #define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX 3 7352 #define regMPC_OUT1_CSC_C33_C34_A 0x0404 7353 #define regMPC_OUT1_CSC_C33_C34_A_BASE_IDX 3 7354 #define regMPC_OUT1_CSC_C11_C12_B 0x0405 7355 #define regMPC_OUT1_CSC_C11_C12_B_BASE_IDX 3 7356 #define regMPC_OUT1_CSC_C13_C14_B 0x0406 7357 #define regMPC_OUT1_CSC_C13_C14_B_BASE_IDX 3 7358 #define regMPC_OUT1_CSC_C21_C22_B 0x0407 7359 #define regMPC_OUT1_CSC_C21_C22_B_BASE_IDX 3 7360 #define regMPC_OUT1_CSC_C23_C24_B 0x0408 7361 #define regMPC_OUT1_CSC_C23_C24_B_BASE_IDX 3 7362 #define regMPC_OUT1_CSC_C31_C32_B 0x0409 7363 #define regMPC_OUT1_CSC_C31_C32_B_BASE_IDX 3 7364 #define regMPC_OUT1_CSC_C33_C34_B 0x040a 7365 #define regMPC_OUT1_CSC_C33_C34_B_BASE_IDX 3 7366 #define regMPC_OUT2_CSC_MODE 0x040b 7367 #define regMPC_OUT2_CSC_MODE_BASE_IDX 3 7368 #define regMPC_OUT2_CSC_C11_C12_A 0x040c 7369 #define regMPC_OUT2_CSC_C11_C12_A_BASE_IDX 3 7370 #define regMPC_OUT2_CSC_C13_C14_A 0x040d 7371 #define regMPC_OUT2_CSC_C13_C14_A_BASE_IDX 3 7372 #define regMPC_OUT2_CSC_C21_C22_A 0x040e 7373 #define regMPC_OUT2_CSC_C21_C22_A_BASE_IDX 3 7374 #define regMPC_OUT2_CSC_C23_C24_A 0x040f 7375 #define regMPC_OUT2_CSC_C23_C24_A_BASE_IDX 3 7376 #define regMPC_OUT2_CSC_C31_C32_A 0x0410 7377 #define regMPC_OUT2_CSC_C31_C32_A_BASE_IDX 3 7378 #define regMPC_OUT2_CSC_C33_C34_A 0x0411 7379 #define regMPC_OUT2_CSC_C33_C34_A_BASE_IDX 3 7380 #define regMPC_OUT2_CSC_C11_C12_B 0x0412 7381 #define regMPC_OUT2_CSC_C11_C12_B_BASE_IDX 3 7382 #define regMPC_OUT2_CSC_C13_C14_B 0x0413 7383 #define regMPC_OUT2_CSC_C13_C14_B_BASE_IDX 3 7384 #define regMPC_OUT2_CSC_C21_C22_B 0x0414 7385 #define regMPC_OUT2_CSC_C21_C22_B_BASE_IDX 3 7386 #define regMPC_OUT2_CSC_C23_C24_B 0x0415 7387 #define regMPC_OUT2_CSC_C23_C24_B_BASE_IDX 3 7388 #define regMPC_OUT2_CSC_C31_C32_B 0x0416 7389 #define regMPC_OUT2_CSC_C31_C32_B_BASE_IDX 3 7390 #define regMPC_OUT2_CSC_C33_C34_B 0x0417 7391 #define regMPC_OUT2_CSC_C33_C34_B_BASE_IDX 3 7392 #define regMPC_OUT3_CSC_MODE 0x0418 7393 #define regMPC_OUT3_CSC_MODE_BASE_IDX 3 7394 #define regMPC_OUT3_CSC_C11_C12_A 0x0419 7395 #define regMPC_OUT3_CSC_C11_C12_A_BASE_IDX 3 7396 #define regMPC_OUT3_CSC_C13_C14_A 0x041a 7397 #define regMPC_OUT3_CSC_C13_C14_A_BASE_IDX 3 7398 #define regMPC_OUT3_CSC_C21_C22_A 0x041b 7399 #define regMPC_OUT3_CSC_C21_C22_A_BASE_IDX 3 7400 #define regMPC_OUT3_CSC_C23_C24_A 0x041c 7401 #define regMPC_OUT3_CSC_C23_C24_A_BASE_IDX 3 7402 #define regMPC_OUT3_CSC_C31_C32_A 0x041d 7403 #define regMPC_OUT3_CSC_C31_C32_A_BASE_IDX 3 7404 #define regMPC_OUT3_CSC_C33_C34_A 0x041e 7405 #define regMPC_OUT3_CSC_C33_C34_A_BASE_IDX 3 7406 #define regMPC_OUT3_CSC_C11_C12_B 0x041f 7407 #define regMPC_OUT3_CSC_C11_C12_B_BASE_IDX 3 7408 #define regMPC_OUT3_CSC_C13_C14_B 0x0420 7409 #define regMPC_OUT3_CSC_C13_C14_B_BASE_IDX 3 7410 #define regMPC_OUT3_CSC_C21_C22_B 0x0421 7411 #define regMPC_OUT3_CSC_C21_C22_B_BASE_IDX 3 7412 #define regMPC_OUT3_CSC_C23_C24_B 0x0422 7413 #define regMPC_OUT3_CSC_C23_C24_B_BASE_IDX 3 7414 #define regMPC_OUT3_CSC_C31_C32_B 0x0423 7415 #define regMPC_OUT3_CSC_C31_C32_B_BASE_IDX 3 7416 #define regMPC_OUT3_CSC_C33_C34_B 0x0424 7417 #define regMPC_OUT3_CSC_C33_C34_B_BASE_IDX 3 7418 7419 7420 // addressBlock: dce_dc_opp_abm0_dispdec 7421 // base address: 0x0 7422 #define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0e7a 7423 #define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 7424 #define regABM0_BL1_PWM_USER_LEVEL 0x0e7b 7425 #define regABM0_BL1_PWM_USER_LEVEL_BASE_IDX 3 7426 #define regABM0_BL1_PWM_TARGET_ABM_LEVEL 0x0e7c 7427 #define regABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 7428 #define regABM0_BL1_PWM_CURRENT_ABM_LEVEL 0x0e7d 7429 #define regABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 7430 #define regABM0_BL1_PWM_FINAL_DUTY_CYCLE 0x0e7e 7431 #define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 7432 #define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0e7f 7433 #define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 7434 #define regABM0_BL1_PWM_ABM_CNTL 0x0e80 7435 #define regABM0_BL1_PWM_ABM_CNTL_BASE_IDX 3 7436 #define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0e81 7437 #define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 7438 #define regABM0_BL1_PWM_GRP2_REG_LOCK 0x0e82 7439 #define regABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 7440 #define regABM0_DC_ABM1_CNTL 0x0e83 7441 #define regABM0_DC_ABM1_CNTL_BASE_IDX 3 7442 #define regABM0_DC_ABM1_IPCSC_COEFF_SEL 0x0e84 7443 #define regABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 7444 #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0e85 7445 #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 7446 #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0e86 7447 #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 7448 #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0e87 7449 #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 7450 #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0e88 7451 #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 7452 #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0e89 7453 #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 7454 #define regABM0_DC_ABM1_ACE_THRES_12 0x0e8a 7455 #define regABM0_DC_ABM1_ACE_THRES_12_BASE_IDX 3 7456 #define regABM0_DC_ABM1_ACE_THRES_34 0x0e8b 7457 #define regABM0_DC_ABM1_ACE_THRES_34_BASE_IDX 3 7458 #define regABM0_DC_ABM1_ACE_CNTL_MISC 0x0e8c 7459 #define regABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 7460 #define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0e8e 7461 #define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 7462 #define regABM0_DC_ABM1_HG_MISC_CTRL 0x0e8f 7463 #define regABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 7464 #define regABM0_DC_ABM1_LS_SUM_OF_LUMA 0x0e90 7465 #define regABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 7466 #define regABM0_DC_ABM1_LS_MIN_MAX_LUMA 0x0e91 7467 #define regABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 7468 #define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0e92 7469 #define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 7470 #define regABM0_DC_ABM1_LS_PIXEL_COUNT 0x0e93 7471 #define regABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 7472 #define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0e94 7473 #define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 7474 #define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0e95 7475 #define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 7476 #define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0e96 7477 #define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 7478 #define regABM0_DC_ABM1_HG_SAMPLE_RATE 0x0e97 7479 #define regABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 7480 #define regABM0_DC_ABM1_LS_SAMPLE_RATE 0x0e98 7481 #define regABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 7482 #define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0e99 7483 #define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 7484 #define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0e9a 7485 #define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 7486 #define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0e9b 7487 #define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 7488 #define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0e9c 7489 #define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 7490 #define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0e9d 7491 #define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 7492 #define regABM0_DC_ABM1_HG_RESULT_1 0x0e9e 7493 #define regABM0_DC_ABM1_HG_RESULT_1_BASE_IDX 3 7494 #define regABM0_DC_ABM1_HG_RESULT_2 0x0e9f 7495 #define regABM0_DC_ABM1_HG_RESULT_2_BASE_IDX 3 7496 #define regABM0_DC_ABM1_HG_RESULT_3 0x0ea0 7497 #define regABM0_DC_ABM1_HG_RESULT_3_BASE_IDX 3 7498 #define regABM0_DC_ABM1_HG_RESULT_4 0x0ea1 7499 #define regABM0_DC_ABM1_HG_RESULT_4_BASE_IDX 3 7500 #define regABM0_DC_ABM1_HG_RESULT_5 0x0ea2 7501 #define regABM0_DC_ABM1_HG_RESULT_5_BASE_IDX 3 7502 #define regABM0_DC_ABM1_HG_RESULT_6 0x0ea3 7503 #define regABM0_DC_ABM1_HG_RESULT_6_BASE_IDX 3 7504 #define regABM0_DC_ABM1_HG_RESULT_7 0x0ea4 7505 #define regABM0_DC_ABM1_HG_RESULT_7_BASE_IDX 3 7506 #define regABM0_DC_ABM1_HG_RESULT_8 0x0ea5 7507 #define regABM0_DC_ABM1_HG_RESULT_8_BASE_IDX 3 7508 #define regABM0_DC_ABM1_HG_RESULT_9 0x0ea6 7509 #define regABM0_DC_ABM1_HG_RESULT_9_BASE_IDX 3 7510 #define regABM0_DC_ABM1_HG_RESULT_10 0x0ea7 7511 #define regABM0_DC_ABM1_HG_RESULT_10_BASE_IDX 3 7512 #define regABM0_DC_ABM1_HG_RESULT_11 0x0ea8 7513 #define regABM0_DC_ABM1_HG_RESULT_11_BASE_IDX 3 7514 #define regABM0_DC_ABM1_HG_RESULT_12 0x0ea9 7515 #define regABM0_DC_ABM1_HG_RESULT_12_BASE_IDX 3 7516 #define regABM0_DC_ABM1_HG_RESULT_13 0x0eaa 7517 #define regABM0_DC_ABM1_HG_RESULT_13_BASE_IDX 3 7518 #define regABM0_DC_ABM1_HG_RESULT_14 0x0eab 7519 #define regABM0_DC_ABM1_HG_RESULT_14_BASE_IDX 3 7520 #define regABM0_DC_ABM1_HG_RESULT_15 0x0eac 7521 #define regABM0_DC_ABM1_HG_RESULT_15_BASE_IDX 3 7522 #define regABM0_DC_ABM1_HG_RESULT_16 0x0ead 7523 #define regABM0_DC_ABM1_HG_RESULT_16_BASE_IDX 3 7524 #define regABM0_DC_ABM1_HG_RESULT_17 0x0eae 7525 #define regABM0_DC_ABM1_HG_RESULT_17_BASE_IDX 3 7526 #define regABM0_DC_ABM1_HG_RESULT_18 0x0eaf 7527 #define regABM0_DC_ABM1_HG_RESULT_18_BASE_IDX 3 7528 #define regABM0_DC_ABM1_HG_RESULT_19 0x0eb0 7529 #define regABM0_DC_ABM1_HG_RESULT_19_BASE_IDX 3 7530 #define regABM0_DC_ABM1_HG_RESULT_20 0x0eb1 7531 #define regABM0_DC_ABM1_HG_RESULT_20_BASE_IDX 3 7532 #define regABM0_DC_ABM1_HG_RESULT_21 0x0eb2 7533 #define regABM0_DC_ABM1_HG_RESULT_21_BASE_IDX 3 7534 #define regABM0_DC_ABM1_HG_RESULT_22 0x0eb3 7535 #define regABM0_DC_ABM1_HG_RESULT_22_BASE_IDX 3 7536 #define regABM0_DC_ABM1_HG_RESULT_23 0x0eb4 7537 #define regABM0_DC_ABM1_HG_RESULT_23_BASE_IDX 3 7538 #define regABM0_DC_ABM1_HG_RESULT_24 0x0eb5 7539 #define regABM0_DC_ABM1_HG_RESULT_24_BASE_IDX 3 7540 #define regABM0_DC_ABM1_BL_MASTER_LOCK 0x0eb6 7541 #define regABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 7542 7543 7544 // addressBlock: dce_dc_opp_abm1_dispdec 7545 // base address: 0x104 7546 #define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0ebb 7547 #define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 7548 #define regABM1_BL1_PWM_USER_LEVEL 0x0ebc 7549 #define regABM1_BL1_PWM_USER_LEVEL_BASE_IDX 3 7550 #define regABM1_BL1_PWM_TARGET_ABM_LEVEL 0x0ebd 7551 #define regABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 7552 #define regABM1_BL1_PWM_CURRENT_ABM_LEVEL 0x0ebe 7553 #define regABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 7554 #define regABM1_BL1_PWM_FINAL_DUTY_CYCLE 0x0ebf 7555 #define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 7556 #define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0ec0 7557 #define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 7558 #define regABM1_BL1_PWM_ABM_CNTL 0x0ec1 7559 #define regABM1_BL1_PWM_ABM_CNTL_BASE_IDX 3 7560 #define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0ec2 7561 #define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 7562 #define regABM1_BL1_PWM_GRP2_REG_LOCK 0x0ec3 7563 #define regABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 7564 #define regABM1_DC_ABM1_CNTL 0x0ec4 7565 #define regABM1_DC_ABM1_CNTL_BASE_IDX 3 7566 #define regABM1_DC_ABM1_IPCSC_COEFF_SEL 0x0ec5 7567 #define regABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 7568 #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0ec6 7569 #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 7570 #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0ec7 7571 #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 7572 #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0ec8 7573 #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 7574 #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0ec9 7575 #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 7576 #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0eca 7577 #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 7578 #define regABM1_DC_ABM1_ACE_THRES_12 0x0ecb 7579 #define regABM1_DC_ABM1_ACE_THRES_12_BASE_IDX 3 7580 #define regABM1_DC_ABM1_ACE_THRES_34 0x0ecc 7581 #define regABM1_DC_ABM1_ACE_THRES_34_BASE_IDX 3 7582 #define regABM1_DC_ABM1_ACE_CNTL_MISC 0x0ecd 7583 #define regABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 7584 #define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0ecf 7585 #define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 7586 #define regABM1_DC_ABM1_HG_MISC_CTRL 0x0ed0 7587 #define regABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 7588 #define regABM1_DC_ABM1_LS_SUM_OF_LUMA 0x0ed1 7589 #define regABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 7590 #define regABM1_DC_ABM1_LS_MIN_MAX_LUMA 0x0ed2 7591 #define regABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 7592 #define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0ed3 7593 #define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 7594 #define regABM1_DC_ABM1_LS_PIXEL_COUNT 0x0ed4 7595 #define regABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 7596 #define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0ed5 7597 #define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 7598 #define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0ed6 7599 #define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 7600 #define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0ed7 7601 #define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 7602 #define regABM1_DC_ABM1_HG_SAMPLE_RATE 0x0ed8 7603 #define regABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 7604 #define regABM1_DC_ABM1_LS_SAMPLE_RATE 0x0ed9 7605 #define regABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 7606 #define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0eda 7607 #define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 7608 #define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0edb 7609 #define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 7610 #define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0edc 7611 #define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 7612 #define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0edd 7613 #define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 7614 #define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0ede 7615 #define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 7616 #define regABM1_DC_ABM1_HG_RESULT_1 0x0edf 7617 #define regABM1_DC_ABM1_HG_RESULT_1_BASE_IDX 3 7618 #define regABM1_DC_ABM1_HG_RESULT_2 0x0ee0 7619 #define regABM1_DC_ABM1_HG_RESULT_2_BASE_IDX 3 7620 #define regABM1_DC_ABM1_HG_RESULT_3 0x0ee1 7621 #define regABM1_DC_ABM1_HG_RESULT_3_BASE_IDX 3 7622 #define regABM1_DC_ABM1_HG_RESULT_4 0x0ee2 7623 #define regABM1_DC_ABM1_HG_RESULT_4_BASE_IDX 3 7624 #define regABM1_DC_ABM1_HG_RESULT_5 0x0ee3 7625 #define regABM1_DC_ABM1_HG_RESULT_5_BASE_IDX 3 7626 #define regABM1_DC_ABM1_HG_RESULT_6 0x0ee4 7627 #define regABM1_DC_ABM1_HG_RESULT_6_BASE_IDX 3 7628 #define regABM1_DC_ABM1_HG_RESULT_7 0x0ee5 7629 #define regABM1_DC_ABM1_HG_RESULT_7_BASE_IDX 3 7630 #define regABM1_DC_ABM1_HG_RESULT_8 0x0ee6 7631 #define regABM1_DC_ABM1_HG_RESULT_8_BASE_IDX 3 7632 #define regABM1_DC_ABM1_HG_RESULT_9 0x0ee7 7633 #define regABM1_DC_ABM1_HG_RESULT_9_BASE_IDX 3 7634 #define regABM1_DC_ABM1_HG_RESULT_10 0x0ee8 7635 #define regABM1_DC_ABM1_HG_RESULT_10_BASE_IDX 3 7636 #define regABM1_DC_ABM1_HG_RESULT_11 0x0ee9 7637 #define regABM1_DC_ABM1_HG_RESULT_11_BASE_IDX 3 7638 #define regABM1_DC_ABM1_HG_RESULT_12 0x0eea 7639 #define regABM1_DC_ABM1_HG_RESULT_12_BASE_IDX 3 7640 #define regABM1_DC_ABM1_HG_RESULT_13 0x0eeb 7641 #define regABM1_DC_ABM1_HG_RESULT_13_BASE_IDX 3 7642 #define regABM1_DC_ABM1_HG_RESULT_14 0x0eec 7643 #define regABM1_DC_ABM1_HG_RESULT_14_BASE_IDX 3 7644 #define regABM1_DC_ABM1_HG_RESULT_15 0x0eed 7645 #define regABM1_DC_ABM1_HG_RESULT_15_BASE_IDX 3 7646 #define regABM1_DC_ABM1_HG_RESULT_16 0x0eee 7647 #define regABM1_DC_ABM1_HG_RESULT_16_BASE_IDX 3 7648 #define regABM1_DC_ABM1_HG_RESULT_17 0x0eef 7649 #define regABM1_DC_ABM1_HG_RESULT_17_BASE_IDX 3 7650 #define regABM1_DC_ABM1_HG_RESULT_18 0x0ef0 7651 #define regABM1_DC_ABM1_HG_RESULT_18_BASE_IDX 3 7652 #define regABM1_DC_ABM1_HG_RESULT_19 0x0ef1 7653 #define regABM1_DC_ABM1_HG_RESULT_19_BASE_IDX 3 7654 #define regABM1_DC_ABM1_HG_RESULT_20 0x0ef2 7655 #define regABM1_DC_ABM1_HG_RESULT_20_BASE_IDX 3 7656 #define regABM1_DC_ABM1_HG_RESULT_21 0x0ef3 7657 #define regABM1_DC_ABM1_HG_RESULT_21_BASE_IDX 3 7658 #define regABM1_DC_ABM1_HG_RESULT_22 0x0ef4 7659 #define regABM1_DC_ABM1_HG_RESULT_22_BASE_IDX 3 7660 #define regABM1_DC_ABM1_HG_RESULT_23 0x0ef5 7661 #define regABM1_DC_ABM1_HG_RESULT_23_BASE_IDX 3 7662 #define regABM1_DC_ABM1_HG_RESULT_24 0x0ef6 7663 #define regABM1_DC_ABM1_HG_RESULT_24_BASE_IDX 3 7664 #define regABM1_DC_ABM1_BL_MASTER_LOCK 0x0ef7 7665 #define regABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 7666 7667 7668 // addressBlock: dce_dc_opp_abm2_dispdec 7669 // base address: 0x208 7670 #define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0efc 7671 #define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 7672 #define regABM2_BL1_PWM_USER_LEVEL 0x0efd 7673 #define regABM2_BL1_PWM_USER_LEVEL_BASE_IDX 3 7674 #define regABM2_BL1_PWM_TARGET_ABM_LEVEL 0x0efe 7675 #define regABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 7676 #define regABM2_BL1_PWM_CURRENT_ABM_LEVEL 0x0eff 7677 #define regABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 7678 #define regABM2_BL1_PWM_FINAL_DUTY_CYCLE 0x0f00 7679 #define regABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 7680 #define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f01 7681 #define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 7682 #define regABM2_BL1_PWM_ABM_CNTL 0x0f02 7683 #define regABM2_BL1_PWM_ABM_CNTL_BASE_IDX 3 7684 #define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f03 7685 #define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 7686 #define regABM2_BL1_PWM_GRP2_REG_LOCK 0x0f04 7687 #define regABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 7688 #define regABM2_DC_ABM1_CNTL 0x0f05 7689 #define regABM2_DC_ABM1_CNTL_BASE_IDX 3 7690 #define regABM2_DC_ABM1_IPCSC_COEFF_SEL 0x0f06 7691 #define regABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 7692 #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f07 7693 #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 7694 #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f08 7695 #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 7696 #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f09 7697 #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 7698 #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f0a 7699 #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 7700 #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f0b 7701 #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 7702 #define regABM2_DC_ABM1_ACE_THRES_12 0x0f0c 7703 #define regABM2_DC_ABM1_ACE_THRES_12_BASE_IDX 3 7704 #define regABM2_DC_ABM1_ACE_THRES_34 0x0f0d 7705 #define regABM2_DC_ABM1_ACE_THRES_34_BASE_IDX 3 7706 #define regABM2_DC_ABM1_ACE_CNTL_MISC 0x0f0e 7707 #define regABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 7708 #define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f10 7709 #define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 7710 #define regABM2_DC_ABM1_HG_MISC_CTRL 0x0f11 7711 #define regABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 7712 #define regABM2_DC_ABM1_LS_SUM_OF_LUMA 0x0f12 7713 #define regABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 7714 #define regABM2_DC_ABM1_LS_MIN_MAX_LUMA 0x0f13 7715 #define regABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 7716 #define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f14 7717 #define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 7718 #define regABM2_DC_ABM1_LS_PIXEL_COUNT 0x0f15 7719 #define regABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 7720 #define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f16 7721 #define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 7722 #define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f17 7723 #define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 7724 #define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f18 7725 #define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 7726 #define regABM2_DC_ABM1_HG_SAMPLE_RATE 0x0f19 7727 #define regABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 7728 #define regABM2_DC_ABM1_LS_SAMPLE_RATE 0x0f1a 7729 #define regABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 7730 #define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f1b 7731 #define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 7732 #define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f1c 7733 #define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 7734 #define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f1d 7735 #define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 7736 #define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f1e 7737 #define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 7738 #define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f1f 7739 #define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 7740 #define regABM2_DC_ABM1_HG_RESULT_1 0x0f20 7741 #define regABM2_DC_ABM1_HG_RESULT_1_BASE_IDX 3 7742 #define regABM2_DC_ABM1_HG_RESULT_2 0x0f21 7743 #define regABM2_DC_ABM1_HG_RESULT_2_BASE_IDX 3 7744 #define regABM2_DC_ABM1_HG_RESULT_3 0x0f22 7745 #define regABM2_DC_ABM1_HG_RESULT_3_BASE_IDX 3 7746 #define regABM2_DC_ABM1_HG_RESULT_4 0x0f23 7747 #define regABM2_DC_ABM1_HG_RESULT_4_BASE_IDX 3 7748 #define regABM2_DC_ABM1_HG_RESULT_5 0x0f24 7749 #define regABM2_DC_ABM1_HG_RESULT_5_BASE_IDX 3 7750 #define regABM2_DC_ABM1_HG_RESULT_6 0x0f25 7751 #define regABM2_DC_ABM1_HG_RESULT_6_BASE_IDX 3 7752 #define regABM2_DC_ABM1_HG_RESULT_7 0x0f26 7753 #define regABM2_DC_ABM1_HG_RESULT_7_BASE_IDX 3 7754 #define regABM2_DC_ABM1_HG_RESULT_8 0x0f27 7755 #define regABM2_DC_ABM1_HG_RESULT_8_BASE_IDX 3 7756 #define regABM2_DC_ABM1_HG_RESULT_9 0x0f28 7757 #define regABM2_DC_ABM1_HG_RESULT_9_BASE_IDX 3 7758 #define regABM2_DC_ABM1_HG_RESULT_10 0x0f29 7759 #define regABM2_DC_ABM1_HG_RESULT_10_BASE_IDX 3 7760 #define regABM2_DC_ABM1_HG_RESULT_11 0x0f2a 7761 #define regABM2_DC_ABM1_HG_RESULT_11_BASE_IDX 3 7762 #define regABM2_DC_ABM1_HG_RESULT_12 0x0f2b 7763 #define regABM2_DC_ABM1_HG_RESULT_12_BASE_IDX 3 7764 #define regABM2_DC_ABM1_HG_RESULT_13 0x0f2c 7765 #define regABM2_DC_ABM1_HG_RESULT_13_BASE_IDX 3 7766 #define regABM2_DC_ABM1_HG_RESULT_14 0x0f2d 7767 #define regABM2_DC_ABM1_HG_RESULT_14_BASE_IDX 3 7768 #define regABM2_DC_ABM1_HG_RESULT_15 0x0f2e 7769 #define regABM2_DC_ABM1_HG_RESULT_15_BASE_IDX 3 7770 #define regABM2_DC_ABM1_HG_RESULT_16 0x0f2f 7771 #define regABM2_DC_ABM1_HG_RESULT_16_BASE_IDX 3 7772 #define regABM2_DC_ABM1_HG_RESULT_17 0x0f30 7773 #define regABM2_DC_ABM1_HG_RESULT_17_BASE_IDX 3 7774 #define regABM2_DC_ABM1_HG_RESULT_18 0x0f31 7775 #define regABM2_DC_ABM1_HG_RESULT_18_BASE_IDX 3 7776 #define regABM2_DC_ABM1_HG_RESULT_19 0x0f32 7777 #define regABM2_DC_ABM1_HG_RESULT_19_BASE_IDX 3 7778 #define regABM2_DC_ABM1_HG_RESULT_20 0x0f33 7779 #define regABM2_DC_ABM1_HG_RESULT_20_BASE_IDX 3 7780 #define regABM2_DC_ABM1_HG_RESULT_21 0x0f34 7781 #define regABM2_DC_ABM1_HG_RESULT_21_BASE_IDX 3 7782 #define regABM2_DC_ABM1_HG_RESULT_22 0x0f35 7783 #define regABM2_DC_ABM1_HG_RESULT_22_BASE_IDX 3 7784 #define regABM2_DC_ABM1_HG_RESULT_23 0x0f36 7785 #define regABM2_DC_ABM1_HG_RESULT_23_BASE_IDX 3 7786 #define regABM2_DC_ABM1_HG_RESULT_24 0x0f37 7787 #define regABM2_DC_ABM1_HG_RESULT_24_BASE_IDX 3 7788 #define regABM2_DC_ABM1_BL_MASTER_LOCK 0x0f38 7789 #define regABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 7790 7791 7792 // addressBlock: dce_dc_opp_abm3_dispdec 7793 // base address: 0x30c 7794 #define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0f3d 7795 #define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 7796 #define regABM3_BL1_PWM_USER_LEVEL 0x0f3e 7797 #define regABM3_BL1_PWM_USER_LEVEL_BASE_IDX 3 7798 #define regABM3_BL1_PWM_TARGET_ABM_LEVEL 0x0f3f 7799 #define regABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 7800 #define regABM3_BL1_PWM_CURRENT_ABM_LEVEL 0x0f40 7801 #define regABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 7802 #define regABM3_BL1_PWM_FINAL_DUTY_CYCLE 0x0f41 7803 #define regABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 7804 #define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f42 7805 #define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 7806 #define regABM3_BL1_PWM_ABM_CNTL 0x0f43 7807 #define regABM3_BL1_PWM_ABM_CNTL_BASE_IDX 3 7808 #define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f44 7809 #define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 7810 #define regABM3_BL1_PWM_GRP2_REG_LOCK 0x0f45 7811 #define regABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 7812 #define regABM3_DC_ABM1_CNTL 0x0f46 7813 #define regABM3_DC_ABM1_CNTL_BASE_IDX 3 7814 #define regABM3_DC_ABM1_IPCSC_COEFF_SEL 0x0f47 7815 #define regABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 7816 #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f48 7817 #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 7818 #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f49 7819 #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 7820 #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f4a 7821 #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 7822 #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f4b 7823 #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 7824 #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f4c 7825 #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 7826 #define regABM3_DC_ABM1_ACE_THRES_12 0x0f4d 7827 #define regABM3_DC_ABM1_ACE_THRES_12_BASE_IDX 3 7828 #define regABM3_DC_ABM1_ACE_THRES_34 0x0f4e 7829 #define regABM3_DC_ABM1_ACE_THRES_34_BASE_IDX 3 7830 #define regABM3_DC_ABM1_ACE_CNTL_MISC 0x0f4f 7831 #define regABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 7832 #define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f51 7833 #define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 7834 #define regABM3_DC_ABM1_HG_MISC_CTRL 0x0f52 7835 #define regABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 7836 #define regABM3_DC_ABM1_LS_SUM_OF_LUMA 0x0f53 7837 #define regABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 7838 #define regABM3_DC_ABM1_LS_MIN_MAX_LUMA 0x0f54 7839 #define regABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 7840 #define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f55 7841 #define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 7842 #define regABM3_DC_ABM1_LS_PIXEL_COUNT 0x0f56 7843 #define regABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 7844 #define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f57 7845 #define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 7846 #define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f58 7847 #define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 7848 #define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f59 7849 #define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 7850 #define regABM3_DC_ABM1_HG_SAMPLE_RATE 0x0f5a 7851 #define regABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 7852 #define regABM3_DC_ABM1_LS_SAMPLE_RATE 0x0f5b 7853 #define regABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 7854 #define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f5c 7855 #define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 7856 #define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f5d 7857 #define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 7858 #define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f5e 7859 #define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 7860 #define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f5f 7861 #define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 7862 #define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f60 7863 #define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 7864 #define regABM3_DC_ABM1_HG_RESULT_1 0x0f61 7865 #define regABM3_DC_ABM1_HG_RESULT_1_BASE_IDX 3 7866 #define regABM3_DC_ABM1_HG_RESULT_2 0x0f62 7867 #define regABM3_DC_ABM1_HG_RESULT_2_BASE_IDX 3 7868 #define regABM3_DC_ABM1_HG_RESULT_3 0x0f63 7869 #define regABM3_DC_ABM1_HG_RESULT_3_BASE_IDX 3 7870 #define regABM3_DC_ABM1_HG_RESULT_4 0x0f64 7871 #define regABM3_DC_ABM1_HG_RESULT_4_BASE_IDX 3 7872 #define regABM3_DC_ABM1_HG_RESULT_5 0x0f65 7873 #define regABM3_DC_ABM1_HG_RESULT_5_BASE_IDX 3 7874 #define regABM3_DC_ABM1_HG_RESULT_6 0x0f66 7875 #define regABM3_DC_ABM1_HG_RESULT_6_BASE_IDX 3 7876 #define regABM3_DC_ABM1_HG_RESULT_7 0x0f67 7877 #define regABM3_DC_ABM1_HG_RESULT_7_BASE_IDX 3 7878 #define regABM3_DC_ABM1_HG_RESULT_8 0x0f68 7879 #define regABM3_DC_ABM1_HG_RESULT_8_BASE_IDX 3 7880 #define regABM3_DC_ABM1_HG_RESULT_9 0x0f69 7881 #define regABM3_DC_ABM1_HG_RESULT_9_BASE_IDX 3 7882 #define regABM3_DC_ABM1_HG_RESULT_10 0x0f6a 7883 #define regABM3_DC_ABM1_HG_RESULT_10_BASE_IDX 3 7884 #define regABM3_DC_ABM1_HG_RESULT_11 0x0f6b 7885 #define regABM3_DC_ABM1_HG_RESULT_11_BASE_IDX 3 7886 #define regABM3_DC_ABM1_HG_RESULT_12 0x0f6c 7887 #define regABM3_DC_ABM1_HG_RESULT_12_BASE_IDX 3 7888 #define regABM3_DC_ABM1_HG_RESULT_13 0x0f6d 7889 #define regABM3_DC_ABM1_HG_RESULT_13_BASE_IDX 3 7890 #define regABM3_DC_ABM1_HG_RESULT_14 0x0f6e 7891 #define regABM3_DC_ABM1_HG_RESULT_14_BASE_IDX 3 7892 #define regABM3_DC_ABM1_HG_RESULT_15 0x0f6f 7893 #define regABM3_DC_ABM1_HG_RESULT_15_BASE_IDX 3 7894 #define regABM3_DC_ABM1_HG_RESULT_16 0x0f70 7895 #define regABM3_DC_ABM1_HG_RESULT_16_BASE_IDX 3 7896 #define regABM3_DC_ABM1_HG_RESULT_17 0x0f71 7897 #define regABM3_DC_ABM1_HG_RESULT_17_BASE_IDX 3 7898 #define regABM3_DC_ABM1_HG_RESULT_18 0x0f72 7899 #define regABM3_DC_ABM1_HG_RESULT_18_BASE_IDX 3 7900 #define regABM3_DC_ABM1_HG_RESULT_19 0x0f73 7901 #define regABM3_DC_ABM1_HG_RESULT_19_BASE_IDX 3 7902 #define regABM3_DC_ABM1_HG_RESULT_20 0x0f74 7903 #define regABM3_DC_ABM1_HG_RESULT_20_BASE_IDX 3 7904 #define regABM3_DC_ABM1_HG_RESULT_21 0x0f75 7905 #define regABM3_DC_ABM1_HG_RESULT_21_BASE_IDX 3 7906 #define regABM3_DC_ABM1_HG_RESULT_22 0x0f76 7907 #define regABM3_DC_ABM1_HG_RESULT_22_BASE_IDX 3 7908 #define regABM3_DC_ABM1_HG_RESULT_23 0x0f77 7909 #define regABM3_DC_ABM1_HG_RESULT_23_BASE_IDX 3 7910 #define regABM3_DC_ABM1_HG_RESULT_24 0x0f78 7911 #define regABM3_DC_ABM1_HG_RESULT_24_BASE_IDX 3 7912 #define regABM3_DC_ABM1_BL_MASTER_LOCK 0x0f79 7913 #define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 7914 7915 7916 // addressBlock: dce_dc_opp_dpg0_dispdec 7917 // base address: 0x0 7918 #define regDPG0_DPG_CONTROL 0x1854 7919 #define regDPG0_DPG_CONTROL_BASE_IDX 2 7920 #define regDPG0_DPG_RAMP_CONTROL 0x1855 7921 #define regDPG0_DPG_RAMP_CONTROL_BASE_IDX 2 7922 #define regDPG0_DPG_DIMENSIONS 0x1856 7923 #define regDPG0_DPG_DIMENSIONS_BASE_IDX 2 7924 #define regDPG0_DPG_COLOUR_R_CR 0x1857 7925 #define regDPG0_DPG_COLOUR_R_CR_BASE_IDX 2 7926 #define regDPG0_DPG_COLOUR_G_Y 0x1858 7927 #define regDPG0_DPG_COLOUR_G_Y_BASE_IDX 2 7928 #define regDPG0_DPG_COLOUR_B_CB 0x1859 7929 #define regDPG0_DPG_COLOUR_B_CB_BASE_IDX 2 7930 #define regDPG0_DPG_OFFSET_SEGMENT 0x185a 7931 #define regDPG0_DPG_OFFSET_SEGMENT_BASE_IDX 2 7932 #define regDPG0_DPG_STATUS 0x185b 7933 #define regDPG0_DPG_STATUS_BASE_IDX 2 7934 #define regDPG0_OPP_PIPE_CRC_RESULTA 0x185e 7935 #define regDPG0_OPP_PIPE_CRC_RESULTA_BASE_IDX 2 7936 #define regDPG0_OPP_PIPE_CRC_RESULTR 0x185f 7937 #define regDPG0_OPP_PIPE_CRC_RESULTR_BASE_IDX 2 7938 #define regDPG0_OPP_PIPE_CRC_RESULTG 0x1860 7939 #define regDPG0_OPP_PIPE_CRC_RESULTG_BASE_IDX 2 7940 #define regDPG0_OPP_PIPE_CRC_RESULTB 0x1861 7941 #define regDPG0_OPP_PIPE_CRC_RESULTB_BASE_IDX 2 7942 #define regDPG0_OPP_PIPE_CRC_RESULTC 0x1862 7943 #define regDPG0_OPP_PIPE_CRC_RESULTC_BASE_IDX 2 7944 7945 7946 // addressBlock: dce_dc_opp_fmt0_dispdec 7947 // base address: 0x0 7948 #define regFMT0_FMT_CLAMP_COMPONENT_R 0x183c 7949 #define regFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 7950 #define regFMT0_FMT_CLAMP_COMPONENT_G 0x183d 7951 #define regFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 7952 #define regFMT0_FMT_CLAMP_COMPONENT_B 0x183e 7953 #define regFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 7954 #define regFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f 7955 #define regFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 7956 #define regFMT0_FMT_CONTROL 0x1840 7957 #define regFMT0_FMT_CONTROL_BASE_IDX 2 7958 #define regFMT0_FMT_BIT_DEPTH_CONTROL 0x1841 7959 #define regFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 7960 #define regFMT0_FMT_DITHER_RAND_R_SEED 0x1842 7961 #define regFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 7962 #define regFMT0_FMT_DITHER_RAND_G_SEED 0x1843 7963 #define regFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 7964 #define regFMT0_FMT_DITHER_RAND_B_SEED 0x1844 7965 #define regFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 7966 #define regFMT0_FMT_CLAMP_CNTL 0x1845 7967 #define regFMT0_FMT_CLAMP_CNTL_BASE_IDX 2 7968 #define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1846 7969 #define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 7970 #define regFMT0_FMT_MAP420_MEMORY_CONTROL 0x1847 7971 #define regFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 7972 #define regFMT0_FMT_422_CONTROL 0x1849 7973 #define regFMT0_FMT_422_CONTROL_BASE_IDX 2 7974 7975 7976 // addressBlock: dce_dc_opp_oppbuf0_dispdec 7977 // base address: 0x0 7978 #define regOPPBUF0_OPPBUF_CONTROL 0x1884 7979 #define regOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2 7980 #define regOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885 7981 #define regOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 7982 #define regOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886 7983 #define regOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 7984 #define regOPPBUF0_OPPBUF_CONTROL1 0x1889 7985 #define regOPPBUF0_OPPBUF_CONTROL1_BASE_IDX 2 7986 7987 7988 // addressBlock: dce_dc_opp_opp_pipe0_dispdec 7989 // base address: 0x0 7990 #define regOPP_PIPE0_OPP_PIPE_CONTROL 0x188c 7991 #define regOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2 7992 7993 7994 // addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec 7995 // base address: 0x0 7996 #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891 7997 #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 7998 #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892 7999 #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2 8000 8001 8002 // addressBlock: dce_dc_opp_dpg1_dispdec 8003 // base address: 0x168 8004 #define regDPG1_DPG_CONTROL 0x18ae 8005 #define regDPG1_DPG_CONTROL_BASE_IDX 2 8006 #define regDPG1_DPG_RAMP_CONTROL 0x18af 8007 #define regDPG1_DPG_RAMP_CONTROL_BASE_IDX 2 8008 #define regDPG1_DPG_DIMENSIONS 0x18b0 8009 #define regDPG1_DPG_DIMENSIONS_BASE_IDX 2 8010 #define regDPG1_DPG_COLOUR_R_CR 0x18b1 8011 #define regDPG1_DPG_COLOUR_R_CR_BASE_IDX 2 8012 #define regDPG1_DPG_COLOUR_G_Y 0x18b2 8013 #define regDPG1_DPG_COLOUR_G_Y_BASE_IDX 2 8014 #define regDPG1_DPG_COLOUR_B_CB 0x18b3 8015 #define regDPG1_DPG_COLOUR_B_CB_BASE_IDX 2 8016 #define regDPG1_DPG_OFFSET_SEGMENT 0x18b4 8017 #define regDPG1_DPG_OFFSET_SEGMENT_BASE_IDX 2 8018 #define regDPG1_DPG_STATUS 0x18b5 8019 #define regDPG1_DPG_STATUS_BASE_IDX 2 8020 #define regDPG1_OPP_PIPE_CRC_RESULTA 0x18b8 8021 #define regDPG1_OPP_PIPE_CRC_RESULTA_BASE_IDX 2 8022 #define regDPG1_OPP_PIPE_CRC_RESULTR 0x18b9 8023 #define regDPG1_OPP_PIPE_CRC_RESULTR_BASE_IDX 2 8024 #define regDPG1_OPP_PIPE_CRC_RESULTG 0x18ba 8025 #define regDPG1_OPP_PIPE_CRC_RESULTG_BASE_IDX 2 8026 #define regDPG1_OPP_PIPE_CRC_RESULTB 0x18bb 8027 #define regDPG1_OPP_PIPE_CRC_RESULTB_BASE_IDX 2 8028 #define regDPG1_OPP_PIPE_CRC_RESULTC 0x18bc 8029 #define regDPG1_OPP_PIPE_CRC_RESULTC_BASE_IDX 2 8030 8031 8032 // addressBlock: dce_dc_opp_fmt1_dispdec 8033 // base address: 0x168 8034 #define regFMT1_FMT_CLAMP_COMPONENT_R 0x1896 8035 #define regFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8036 #define regFMT1_FMT_CLAMP_COMPONENT_G 0x1897 8037 #define regFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8038 #define regFMT1_FMT_CLAMP_COMPONENT_B 0x1898 8039 #define regFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8040 #define regFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899 8041 #define regFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8042 #define regFMT1_FMT_CONTROL 0x189a 8043 #define regFMT1_FMT_CONTROL_BASE_IDX 2 8044 #define regFMT1_FMT_BIT_DEPTH_CONTROL 0x189b 8045 #define regFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8046 #define regFMT1_FMT_DITHER_RAND_R_SEED 0x189c 8047 #define regFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8048 #define regFMT1_FMT_DITHER_RAND_G_SEED 0x189d 8049 #define regFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8050 #define regFMT1_FMT_DITHER_RAND_B_SEED 0x189e 8051 #define regFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8052 #define regFMT1_FMT_CLAMP_CNTL 0x189f 8053 #define regFMT1_FMT_CLAMP_CNTL_BASE_IDX 2 8054 #define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a0 8055 #define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8056 #define regFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a1 8057 #define regFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8058 #define regFMT1_FMT_422_CONTROL 0x18a3 8059 #define regFMT1_FMT_422_CONTROL_BASE_IDX 2 8060 8061 8062 // addressBlock: dce_dc_opp_oppbuf1_dispdec 8063 // base address: 0x168 8064 #define regOPPBUF1_OPPBUF_CONTROL 0x18de 8065 #define regOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2 8066 #define regOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df 8067 #define regOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8068 #define regOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0 8069 #define regOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8070 #define regOPPBUF1_OPPBUF_CONTROL1 0x18e3 8071 #define regOPPBUF1_OPPBUF_CONTROL1_BASE_IDX 2 8072 8073 8074 // addressBlock: dce_dc_opp_opp_pipe1_dispdec 8075 // base address: 0x168 8076 #define regOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6 8077 #define regOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2 8078 8079 8080 // addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec 8081 // base address: 0x168 8082 #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb 8083 #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8084 #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec 8085 #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2 8086 8087 8088 // addressBlock: dce_dc_opp_dpg2_dispdec 8089 // base address: 0x2d0 8090 #define regDPG2_DPG_CONTROL 0x1908 8091 #define regDPG2_DPG_CONTROL_BASE_IDX 2 8092 #define regDPG2_DPG_RAMP_CONTROL 0x1909 8093 #define regDPG2_DPG_RAMP_CONTROL_BASE_IDX 2 8094 #define regDPG2_DPG_DIMENSIONS 0x190a 8095 #define regDPG2_DPG_DIMENSIONS_BASE_IDX 2 8096 #define regDPG2_DPG_COLOUR_R_CR 0x190b 8097 #define regDPG2_DPG_COLOUR_R_CR_BASE_IDX 2 8098 #define regDPG2_DPG_COLOUR_G_Y 0x190c 8099 #define regDPG2_DPG_COLOUR_G_Y_BASE_IDX 2 8100 #define regDPG2_DPG_COLOUR_B_CB 0x190d 8101 #define regDPG2_DPG_COLOUR_B_CB_BASE_IDX 2 8102 #define regDPG2_DPG_OFFSET_SEGMENT 0x190e 8103 #define regDPG2_DPG_OFFSET_SEGMENT_BASE_IDX 2 8104 #define regDPG2_DPG_STATUS 0x190f 8105 #define regDPG2_DPG_STATUS_BASE_IDX 2 8106 #define regDPG2_OPP_PIPE_CRC_RESULTA 0x1912 8107 #define regDPG2_OPP_PIPE_CRC_RESULTA_BASE_IDX 2 8108 #define regDPG2_OPP_PIPE_CRC_RESULTR 0x1913 8109 #define regDPG2_OPP_PIPE_CRC_RESULTR_BASE_IDX 2 8110 #define regDPG2_OPP_PIPE_CRC_RESULTG 0x1914 8111 #define regDPG2_OPP_PIPE_CRC_RESULTG_BASE_IDX 2 8112 #define regDPG2_OPP_PIPE_CRC_RESULTB 0x1915 8113 #define regDPG2_OPP_PIPE_CRC_RESULTB_BASE_IDX 2 8114 #define regDPG2_OPP_PIPE_CRC_RESULTC 0x1916 8115 #define regDPG2_OPP_PIPE_CRC_RESULTC_BASE_IDX 2 8116 8117 8118 // addressBlock: dce_dc_opp_fmt2_dispdec 8119 // base address: 0x2d0 8120 #define regFMT2_FMT_CLAMP_COMPONENT_R 0x18f0 8121 #define regFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8122 #define regFMT2_FMT_CLAMP_COMPONENT_G 0x18f1 8123 #define regFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8124 #define regFMT2_FMT_CLAMP_COMPONENT_B 0x18f2 8125 #define regFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8126 #define regFMT2_FMT_DYNAMIC_EXP_CNTL 0x18f3 8127 #define regFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8128 #define regFMT2_FMT_CONTROL 0x18f4 8129 #define regFMT2_FMT_CONTROL_BASE_IDX 2 8130 #define regFMT2_FMT_BIT_DEPTH_CONTROL 0x18f5 8131 #define regFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8132 #define regFMT2_FMT_DITHER_RAND_R_SEED 0x18f6 8133 #define regFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8134 #define regFMT2_FMT_DITHER_RAND_G_SEED 0x18f7 8135 #define regFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8136 #define regFMT2_FMT_DITHER_RAND_B_SEED 0x18f8 8137 #define regFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8138 #define regFMT2_FMT_CLAMP_CNTL 0x18f9 8139 #define regFMT2_FMT_CLAMP_CNTL_BASE_IDX 2 8140 #define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18fa 8141 #define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8142 #define regFMT2_FMT_MAP420_MEMORY_CONTROL 0x18fb 8143 #define regFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8144 #define regFMT2_FMT_422_CONTROL 0x18fd 8145 #define regFMT2_FMT_422_CONTROL_BASE_IDX 2 8146 8147 8148 // addressBlock: dce_dc_opp_oppbuf2_dispdec 8149 // base address: 0x2d0 8150 #define regOPPBUF2_OPPBUF_CONTROL 0x1938 8151 #define regOPPBUF2_OPPBUF_CONTROL_BASE_IDX 2 8152 #define regOPPBUF2_OPPBUF_3D_PARAMETERS_0 0x1939 8153 #define regOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8154 #define regOPPBUF2_OPPBUF_3D_PARAMETERS_1 0x193a 8155 #define regOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8156 #define regOPPBUF2_OPPBUF_CONTROL1 0x193d 8157 #define regOPPBUF2_OPPBUF_CONTROL1_BASE_IDX 2 8158 8159 8160 // addressBlock: dce_dc_opp_opp_pipe2_dispdec 8161 // base address: 0x2d0 8162 #define regOPP_PIPE2_OPP_PIPE_CONTROL 0x1940 8163 #define regOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX 2 8164 8165 8166 // addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec 8167 // base address: 0x2d0 8168 #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0x1945 8169 #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8170 #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0x1946 8171 #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX 2 8172 8173 8174 // addressBlock: dce_dc_opp_dpg3_dispdec 8175 // base address: 0x438 8176 #define regDPG3_DPG_CONTROL 0x1962 8177 #define regDPG3_DPG_CONTROL_BASE_IDX 2 8178 #define regDPG3_DPG_RAMP_CONTROL 0x1963 8179 #define regDPG3_DPG_RAMP_CONTROL_BASE_IDX 2 8180 #define regDPG3_DPG_DIMENSIONS 0x1964 8181 #define regDPG3_DPG_DIMENSIONS_BASE_IDX 2 8182 #define regDPG3_DPG_COLOUR_R_CR 0x1965 8183 #define regDPG3_DPG_COLOUR_R_CR_BASE_IDX 2 8184 #define regDPG3_DPG_COLOUR_G_Y 0x1966 8185 #define regDPG3_DPG_COLOUR_G_Y_BASE_IDX 2 8186 #define regDPG3_DPG_COLOUR_B_CB 0x1967 8187 #define regDPG3_DPG_COLOUR_B_CB_BASE_IDX 2 8188 #define regDPG3_DPG_OFFSET_SEGMENT 0x1968 8189 #define regDPG3_DPG_OFFSET_SEGMENT_BASE_IDX 2 8190 #define regDPG3_DPG_STATUS 0x1969 8191 #define regDPG3_DPG_STATUS_BASE_IDX 2 8192 #define regDPG3_OPP_PIPE_CRC_RESULTA 0x196c 8193 #define regDPG3_OPP_PIPE_CRC_RESULTA_BASE_IDX 2 8194 #define regDPG3_OPP_PIPE_CRC_RESULTR 0x196d 8195 #define regDPG3_OPP_PIPE_CRC_RESULTR_BASE_IDX 2 8196 #define regDPG3_OPP_PIPE_CRC_RESULTG 0x196e 8197 #define regDPG3_OPP_PIPE_CRC_RESULTG_BASE_IDX 2 8198 #define regDPG3_OPP_PIPE_CRC_RESULTB 0x196f 8199 #define regDPG3_OPP_PIPE_CRC_RESULTB_BASE_IDX 2 8200 #define regDPG3_OPP_PIPE_CRC_RESULTC 0x1970 8201 #define regDPG3_OPP_PIPE_CRC_RESULTC_BASE_IDX 2 8202 8203 8204 // addressBlock: dce_dc_opp_fmt3_dispdec 8205 // base address: 0x438 8206 #define regFMT3_FMT_CLAMP_COMPONENT_R 0x194a 8207 #define regFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8208 #define regFMT3_FMT_CLAMP_COMPONENT_G 0x194b 8209 #define regFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8210 #define regFMT3_FMT_CLAMP_COMPONENT_B 0x194c 8211 #define regFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8212 #define regFMT3_FMT_DYNAMIC_EXP_CNTL 0x194d 8213 #define regFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8214 #define regFMT3_FMT_CONTROL 0x194e 8215 #define regFMT3_FMT_CONTROL_BASE_IDX 2 8216 #define regFMT3_FMT_BIT_DEPTH_CONTROL 0x194f 8217 #define regFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8218 #define regFMT3_FMT_DITHER_RAND_R_SEED 0x1950 8219 #define regFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8220 #define regFMT3_FMT_DITHER_RAND_G_SEED 0x1951 8221 #define regFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8222 #define regFMT3_FMT_DITHER_RAND_B_SEED 0x1952 8223 #define regFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8224 #define regFMT3_FMT_CLAMP_CNTL 0x1953 8225 #define regFMT3_FMT_CLAMP_CNTL_BASE_IDX 2 8226 #define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1954 8227 #define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8228 #define regFMT3_FMT_MAP420_MEMORY_CONTROL 0x1955 8229 #define regFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8230 #define regFMT3_FMT_422_CONTROL 0x1957 8231 #define regFMT3_FMT_422_CONTROL_BASE_IDX 2 8232 8233 8234 // addressBlock: dce_dc_opp_oppbuf3_dispdec 8235 // base address: 0x438 8236 #define regOPPBUF3_OPPBUF_CONTROL 0x1992 8237 #define regOPPBUF3_OPPBUF_CONTROL_BASE_IDX 2 8238 #define regOPPBUF3_OPPBUF_3D_PARAMETERS_0 0x1993 8239 #define regOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8240 #define regOPPBUF3_OPPBUF_3D_PARAMETERS_1 0x1994 8241 #define regOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8242 #define regOPPBUF3_OPPBUF_CONTROL1 0x1997 8243 #define regOPPBUF3_OPPBUF_CONTROL1_BASE_IDX 2 8244 8245 8246 // addressBlock: dce_dc_opp_opp_pipe3_dispdec 8247 // base address: 0x438 8248 #define regOPP_PIPE3_OPP_PIPE_CONTROL 0x199a 8249 #define regOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX 2 8250 8251 8252 // addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec 8253 // base address: 0x438 8254 #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0x199f 8255 #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8256 #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0x19a0 8257 #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX 2 8258 8259 8260 // addressBlock: dce_dc_opp_dscrm0_dispdec 8261 // base address: 0x0 8262 #define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG 0x1a64 8263 #define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8264 8265 8266 // addressBlock: dce_dc_opp_dscrm1_dispdec 8267 // base address: 0x4 8268 #define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG 0x1a65 8269 #define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8270 8271 8272 // addressBlock: dce_dc_opp_dscrm2_dispdec 8273 // base address: 0x8 8274 #define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG 0x1a66 8275 #define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8276 8277 8278 // addressBlock: dce_dc_opp_dscrm3_dispdec 8279 // base address: 0xc 8280 #define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG 0x1a67 8281 #define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8282 8283 8284 // addressBlock: dce_dc_opp_opp_top_dispdec 8285 // base address: 0x0 8286 #define regOPP_TOP_CLK_CONTROL 0x1a5e 8287 #define regOPP_TOP_CLK_CONTROL_BASE_IDX 2 8288 #define regOPP_ABM_CONTROL 0x1a60 8289 #define regOPP_ABM_CONTROL_BASE_IDX 2 8290 8291 8292 // addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec 8293 // base address: 0x6af8 8294 #define regDC_PERFMON16_PERFCOUNTER_CNTL 0x1abe 8295 #define regDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX 2 8296 #define regDC_PERFMON16_PERFCOUNTER_CNTL2 0x1abf 8297 #define regDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX 2 8298 #define regDC_PERFMON16_PERFCOUNTER_STATE 0x1ac0 8299 #define regDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX 2 8300 #define regDC_PERFMON16_PERFMON_CNTL 0x1ac1 8301 #define regDC_PERFMON16_PERFMON_CNTL_BASE_IDX 2 8302 #define regDC_PERFMON16_PERFMON_CNTL2 0x1ac2 8303 #define regDC_PERFMON16_PERFMON_CNTL2_BASE_IDX 2 8304 #define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC 0x1ac3 8305 #define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 8306 #define regDC_PERFMON16_PERFMON_CVALUE_LOW 0x1ac4 8307 #define regDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX 2 8308 #define regDC_PERFMON16_PERFMON_HI 0x1ac5 8309 #define regDC_PERFMON16_PERFMON_HI_BASE_IDX 2 8310 #define regDC_PERFMON16_PERFMON_LOW 0x1ac6 8311 #define regDC_PERFMON16_PERFMON_LOW_BASE_IDX 2 8312 8313 8314 // addressBlock: dce_dc_optc_odm0_dispdec 8315 // base address: 0x0 8316 #define regODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca 8317 #define regODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8318 #define regODM0_OPTC_DATA_SOURCE_SELECT 0x1acb 8319 #define regODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8320 #define regODM0_OPTC_DATA_FORMAT_CONTROL 0x1acc 8321 #define regODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8322 #define regODM0_OPTC_BYTES_PER_PIXEL 0x1acd 8323 #define regODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8324 #define regODM0_OPTC_WIDTH_CONTROL 0x1ace 8325 #define regODM0_OPTC_WIDTH_CONTROL_BASE_IDX 2 8326 #define regODM0_OPTC_INPUT_CLOCK_CONTROL 0x1acf 8327 #define regODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8328 #define regODM0_OPTC_MEMORY_CONFIG 0x1ad0 8329 #define regODM0_OPTC_MEMORY_CONFIG_BASE_IDX 2 8330 #define regODM0_OPTC_INPUT_SPARE_REGISTER 0x1ad1 8331 #define regODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8332 #define regODM0_OPTC_UNDERFLOW_THRESHOLD 0x1ad5 8333 #define regODM0_OPTC_UNDERFLOW_THRESHOLD_BASE_IDX 2 8334 8335 8336 // addressBlock: dce_dc_optc_odm1_dispdec 8337 // base address: 0x40 8338 #define regODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada 8339 #define regODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8340 #define regODM1_OPTC_DATA_SOURCE_SELECT 0x1adb 8341 #define regODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8342 #define regODM1_OPTC_DATA_FORMAT_CONTROL 0x1adc 8343 #define regODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8344 #define regODM1_OPTC_BYTES_PER_PIXEL 0x1add 8345 #define regODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8346 #define regODM1_OPTC_WIDTH_CONTROL 0x1ade 8347 #define regODM1_OPTC_WIDTH_CONTROL_BASE_IDX 2 8348 #define regODM1_OPTC_INPUT_CLOCK_CONTROL 0x1adf 8349 #define regODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8350 #define regODM1_OPTC_MEMORY_CONFIG 0x1ae0 8351 #define regODM1_OPTC_MEMORY_CONFIG_BASE_IDX 2 8352 #define regODM1_OPTC_INPUT_SPARE_REGISTER 0x1ae1 8353 #define regODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8354 #define regODM1_OPTC_UNDERFLOW_THRESHOLD 0x1ae5 8355 #define regODM1_OPTC_UNDERFLOW_THRESHOLD_BASE_IDX 2 8356 8357 8358 // addressBlock: dce_dc_optc_odm2_dispdec 8359 // base address: 0x80 8360 #define regODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea 8361 #define regODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8362 #define regODM2_OPTC_DATA_SOURCE_SELECT 0x1aeb 8363 #define regODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8364 #define regODM2_OPTC_DATA_FORMAT_CONTROL 0x1aec 8365 #define regODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8366 #define regODM2_OPTC_BYTES_PER_PIXEL 0x1aed 8367 #define regODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8368 #define regODM2_OPTC_WIDTH_CONTROL 0x1aee 8369 #define regODM2_OPTC_WIDTH_CONTROL_BASE_IDX 2 8370 #define regODM2_OPTC_INPUT_CLOCK_CONTROL 0x1aef 8371 #define regODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8372 #define regODM2_OPTC_MEMORY_CONFIG 0x1af0 8373 #define regODM2_OPTC_MEMORY_CONFIG_BASE_IDX 2 8374 #define regODM2_OPTC_INPUT_SPARE_REGISTER 0x1af1 8375 #define regODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8376 #define regODM2_OPTC_UNDERFLOW_THRESHOLD 0x1af5 8377 #define regODM2_OPTC_UNDERFLOW_THRESHOLD_BASE_IDX 2 8378 8379 8380 // addressBlock: dce_dc_optc_odm3_dispdec 8381 // base address: 0xc0 8382 #define regODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa 8383 #define regODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8384 #define regODM3_OPTC_DATA_SOURCE_SELECT 0x1afb 8385 #define regODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8386 #define regODM3_OPTC_DATA_FORMAT_CONTROL 0x1afc 8387 #define regODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8388 #define regODM3_OPTC_BYTES_PER_PIXEL 0x1afd 8389 #define regODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8390 #define regODM3_OPTC_WIDTH_CONTROL 0x1afe 8391 #define regODM3_OPTC_WIDTH_CONTROL_BASE_IDX 2 8392 #define regODM3_OPTC_INPUT_CLOCK_CONTROL 0x1aff 8393 #define regODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8394 #define regODM3_OPTC_MEMORY_CONFIG 0x1b00 8395 #define regODM3_OPTC_MEMORY_CONFIG_BASE_IDX 2 8396 #define regODM3_OPTC_INPUT_SPARE_REGISTER 0x1b01 8397 #define regODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8398 #define regODM3_OPTC_UNDERFLOW_THRESHOLD 0x1b05 8399 #define regODM3_OPTC_UNDERFLOW_THRESHOLD_BASE_IDX 2 8400 8401 8402 // addressBlock: dce_dc_optc_otg0_dispdec 8403 // base address: 0x0 8404 #define regOTG0_OTG_H_TOTAL 0x1b2a 8405 #define regOTG0_OTG_H_TOTAL_BASE_IDX 2 8406 #define regOTG0_OTG_H_BLANK_START_END 0x1b2b 8407 #define regOTG0_OTG_H_BLANK_START_END_BASE_IDX 2 8408 #define regOTG0_OTG_H_SYNC_A 0x1b2c 8409 #define regOTG0_OTG_H_SYNC_A_BASE_IDX 2 8410 #define regOTG0_OTG_H_SYNC_A_CNTL 0x1b2d 8411 #define regOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2 8412 #define regOTG0_OTG_H_TIMING_CNTL 0x1b2e 8413 #define regOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2 8414 #define regOTG0_OTG_V_TOTAL 0x1b2f 8415 #define regOTG0_OTG_V_TOTAL_BASE_IDX 2 8416 #define regOTG0_OTG_V_TOTAL_MIN 0x1b30 8417 #define regOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2 8418 #define regOTG0_OTG_V_TOTAL_MAX 0x1b31 8419 #define regOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2 8420 #define regOTG0_OTG_V_TOTAL_MID 0x1b32 8421 #define regOTG0_OTG_V_TOTAL_MID_BASE_IDX 2 8422 #define regOTG0_OTG_V_TOTAL_CONTROL 0x1b33 8423 #define regOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2 8424 #define regOTG0_OTG_V_COUNT_STOP_CONTROL 0x1b34 8425 #define regOTG0_OTG_V_COUNT_STOP_CONTROL_BASE_IDX 2 8426 #define regOTG0_OTG_V_COUNT_STOP_CONTROL2 0x1b35 8427 #define regOTG0_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX 2 8428 #define regOTG0_OTG_V_TOTAL_INT_STATUS 0x1b36 8429 #define regOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 8430 #define regOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b37 8431 #define regOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 8432 #define regOTG0_OTG_V_BLANK_START_END 0x1b38 8433 #define regOTG0_OTG_V_BLANK_START_END_BASE_IDX 2 8434 #define regOTG0_OTG_V_SYNC_A 0x1b39 8435 #define regOTG0_OTG_V_SYNC_A_BASE_IDX 2 8436 #define regOTG0_OTG_V_SYNC_A_CNTL 0x1b3a 8437 #define regOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2 8438 #define regOTG0_OTG_TRIGA_CNTL 0x1b3b 8439 #define regOTG0_OTG_TRIGA_CNTL_BASE_IDX 2 8440 #define regOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3c 8441 #define regOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 8442 #define regOTG0_OTG_TRIGB_CNTL 0x1b3d 8443 #define regOTG0_OTG_TRIGB_CNTL_BASE_IDX 2 8444 #define regOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3e 8445 #define regOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 8446 #define regOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3f 8447 #define regOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 8448 #define regOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b41 8449 #define regOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 8450 #define regOTG0_OTG_CONTROL 0x1b43 8451 #define regOTG0_OTG_CONTROL_BASE_IDX 2 8452 #define regOTG0_OTG_DLPC_CONTROL 0x1b44 8453 #define regOTG0_OTG_DLPC_CONTROL_BASE_IDX 2 8454 #define regOTG0_OTG_INTERLACE_CONTROL 0x1b45 8455 #define regOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2 8456 #define regOTG0_OTG_INTERLACE_STATUS 0x1b46 8457 #define regOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2 8458 #define regOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47 8459 #define regOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 8460 #define regOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48 8461 #define regOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 8462 #define regOTG0_OTG_STATUS 0x1b49 8463 #define regOTG0_OTG_STATUS_BASE_IDX 2 8464 #define regOTG0_OTG_STATUS_POSITION 0x1b4a 8465 #define regOTG0_OTG_STATUS_POSITION_BASE_IDX 2 8466 #define regOTG0_OTG_LONG_VBLANK_STATUS 0x1b4b 8467 #define regOTG0_OTG_LONG_VBLANK_STATUS_BASE_IDX 2 8468 #define regOTG0_OTG_NOM_VERT_POSITION 0x1b4c 8469 #define regOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2 8470 #define regOTG0_OTG_STATUS_FRAME_COUNT 0x1b4d 8471 #define regOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 8472 #define regOTG0_OTG_STATUS_VF_COUNT 0x1b4e 8473 #define regOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2 8474 #define regOTG0_OTG_STATUS_HV_COUNT 0x1b4f 8475 #define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2 8476 #define regOTG0_OTG_COUNT_CONTROL 0x1b50 8477 #define regOTG0_OTG_COUNT_CONTROL_BASE_IDX 2 8478 #define regOTG0_OTG_COUNT_RESET 0x1b51 8479 #define regOTG0_OTG_COUNT_RESET_BASE_IDX 2 8480 #define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b52 8481 #define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 8482 #define regOTG0_OTG_VERT_SYNC_CONTROL 0x1b53 8483 #define regOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 8484 #define regOTG0_OTG_STEREO_STATUS 0x1b54 8485 #define regOTG0_OTG_STEREO_STATUS_BASE_IDX 2 8486 #define regOTG0_OTG_STEREO_CONTROL 0x1b55 8487 #define regOTG0_OTG_STEREO_CONTROL_BASE_IDX 2 8488 #define regOTG0_OTG_SNAPSHOT_STATUS 0x1b56 8489 #define regOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2 8490 #define regOTG0_OTG_SNAPSHOT_CONTROL 0x1b57 8491 #define regOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 8492 #define regOTG0_OTG_SNAPSHOT_POSITION 0x1b58 8493 #define regOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2 8494 #define regOTG0_OTG_SNAPSHOT_FRAME 0x1b59 8495 #define regOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2 8496 #define regOTG0_OTG_INTERRUPT_CONTROL 0x1b5a 8497 #define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2 8498 #define regOTG0_OTG_UPDATE_LOCK 0x1b5b 8499 #define regOTG0_OTG_UPDATE_LOCK_BASE_IDX 2 8500 #define regOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5c 8501 #define regOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 8502 #define regOTG0_OTG_MASTER_EN 0x1b5d 8503 #define regOTG0_OTG_MASTER_EN_BASE_IDX 2 8504 #define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b5f 8505 #define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 8506 #define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b60 8507 #define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 8508 #define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b61 8509 #define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 8510 #define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b62 8511 #define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 8512 #define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b63 8513 #define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 8514 #define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b64 8515 #define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 8516 #define regOTG0_OTG_CRC_CNTL 0x1b65 8517 #define regOTG0_OTG_CRC_CNTL_BASE_IDX 2 8518 #define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b66 8519 #define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 8520 #define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b67 8521 #define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 8522 #define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b68 8523 #define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 8524 #define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b69 8525 #define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 8526 #define regOTG0_OTG_CRC0_DATA_RG 0x1b6a 8527 #define regOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2 8528 #define regOTG0_OTG_CRC0_DATA_B 0x1b6b 8529 #define regOTG0_OTG_CRC0_DATA_B_BASE_IDX 2 8530 #define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b6c 8531 #define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 8532 #define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b6d 8533 #define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 8534 #define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b6e 8535 #define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 8536 #define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b6f 8537 #define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 8538 #define regOTG0_OTG_CRC1_DATA_RG 0x1b70 8539 #define regOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2 8540 #define regOTG0_OTG_CRC1_DATA_B 0x1b71 8541 #define regOTG0_OTG_CRC1_DATA_B_BASE_IDX 2 8542 #define regOTG0_OTG_CRC2_DATA_RG 0x1b72 8543 #define regOTG0_OTG_CRC2_DATA_RG_BASE_IDX 2 8544 #define regOTG0_OTG_CRC2_DATA_B 0x1b73 8545 #define regOTG0_OTG_CRC2_DATA_B_BASE_IDX 2 8546 #define regOTG0_OTG_CRC3_DATA_RG 0x1b74 8547 #define regOTG0_OTG_CRC3_DATA_RG_BASE_IDX 2 8548 #define regOTG0_OTG_CRC3_DATA_B 0x1b75 8549 #define regOTG0_OTG_CRC3_DATA_B_BASE_IDX 2 8550 #define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b76 8551 #define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 8552 #define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b77 8553 #define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 8554 #define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK 0x1b78 8555 #define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 8556 #define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK 0x1b79 8557 #define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 8558 #define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK 0x1b7a 8559 #define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 8560 #define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK 0x1b7b 8561 #define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 8562 #define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK 0x1b7c 8563 #define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 8564 #define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK 0x1b7d 8565 #define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 8566 #define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK 0x1b7e 8567 #define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 8568 #define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK 0x1b7f 8569 #define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 8570 #define regOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b80 8571 #define regOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 8572 #define regOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b81 8573 #define regOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 8574 #define regOTG0_OTG_GSL_VSYNC_GAP 0x1b82 8575 #define regOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2 8576 #define regOTG0_OTG_MASTER_UPDATE_MODE 0x1b83 8577 #define regOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 8578 #define regOTG0_OTG_CLOCK_CONTROL 0x1b84 8579 #define regOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2 8580 #define regOTG0_OTG_VSTARTUP_PARAM 0x1b85 8581 #define regOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2 8582 #define regOTG0_OTG_VUPDATE_PARAM 0x1b86 8583 #define regOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2 8584 #define regOTG0_OTG_VREADY_PARAM 0x1b87 8585 #define regOTG0_OTG_VREADY_PARAM_BASE_IDX 2 8586 #define regOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b88 8587 #define regOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 8588 #define regOTG0_OTG_MASTER_UPDATE_LOCK 0x1b89 8589 #define regOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 8590 #define regOTG0_OTG_GSL_CONTROL 0x1b8a 8591 #define regOTG0_OTG_GSL_CONTROL_BASE_IDX 2 8592 #define regOTG0_OTG_GSL_WINDOW_X 0x1b8b 8593 #define regOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2 8594 #define regOTG0_OTG_GSL_WINDOW_Y 0x1b8c 8595 #define regOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2 8596 #define regOTG0_OTG_VUPDATE_KEEPOUT 0x1b8d 8597 #define regOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 8598 #define regOTG0_OTG_GLOBAL_CONTROL0 0x1b8e 8599 #define regOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2 8600 #define regOTG0_OTG_GLOBAL_CONTROL1 0x1b8f 8601 #define regOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2 8602 #define regOTG0_OTG_GLOBAL_CONTROL2 0x1b90 8603 #define regOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2 8604 #define regOTG0_OTG_GLOBAL_CONTROL3 0x1b91 8605 #define regOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2 8606 #define regOTG0_OTG_GLOBAL_CONTROL4 0x1b92 8607 #define regOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX 2 8608 #define regOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b93 8609 #define regOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 8610 #define regOTG0_OTG_DRR_TIMING_INT_STATUS 0x1b95 8611 #define regOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 8612 #define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE 0x1b96 8613 #define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 8614 #define regOTG0_OTG_DRR_V_TOTAL_CHANGE 0x1b97 8615 #define regOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 8616 #define regOTG0_OTG_DRR_TRIGGER_WINDOW 0x1b98 8617 #define regOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 8618 #define regOTG0_OTG_DRR_CONTROL 0x1b99 8619 #define regOTG0_OTG_DRR_CONTROL_BASE_IDX 2 8620 #define regOTG0_OTG_DRR_CONTOL2 0x1b9a 8621 #define regOTG0_OTG_DRR_CONTOL2_BASE_IDX 2 8622 #define regOTG0_OTG_M_CONST_DTO0 0x1b9b 8623 #define regOTG0_OTG_M_CONST_DTO0_BASE_IDX 2 8624 #define regOTG0_OTG_M_CONST_DTO1 0x1b9c 8625 #define regOTG0_OTG_M_CONST_DTO1_BASE_IDX 2 8626 #define regOTG0_OTG_REQUEST_CONTROL 0x1b9d 8627 #define regOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2 8628 #define regOTG0_OTG_DSC_START_POSITION 0x1b9e 8629 #define regOTG0_OTG_DSC_START_POSITION_BASE_IDX 2 8630 #define regOTG0_OTG_PIPE_UPDATE_STATUS 0x1b9f 8631 #define regOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 8632 #define regOTG0_OTG_SPARE_REGISTER 0x1ba0 8633 #define regOTG0_OTG_SPARE_REGISTER_BASE_IDX 2 8634 8635 8636 // addressBlock: dce_dc_optc_otg1_dispdec 8637 // base address: 0x200 8638 #define regOTG1_OTG_H_TOTAL 0x1baa 8639 #define regOTG1_OTG_H_TOTAL_BASE_IDX 2 8640 #define regOTG1_OTG_H_BLANK_START_END 0x1bab 8641 #define regOTG1_OTG_H_BLANK_START_END_BASE_IDX 2 8642 #define regOTG1_OTG_H_SYNC_A 0x1bac 8643 #define regOTG1_OTG_H_SYNC_A_BASE_IDX 2 8644 #define regOTG1_OTG_H_SYNC_A_CNTL 0x1bad 8645 #define regOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2 8646 #define regOTG1_OTG_H_TIMING_CNTL 0x1bae 8647 #define regOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2 8648 #define regOTG1_OTG_V_TOTAL 0x1baf 8649 #define regOTG1_OTG_V_TOTAL_BASE_IDX 2 8650 #define regOTG1_OTG_V_TOTAL_MIN 0x1bb0 8651 #define regOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2 8652 #define regOTG1_OTG_V_TOTAL_MAX 0x1bb1 8653 #define regOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2 8654 #define regOTG1_OTG_V_TOTAL_MID 0x1bb2 8655 #define regOTG1_OTG_V_TOTAL_MID_BASE_IDX 2 8656 #define regOTG1_OTG_V_TOTAL_CONTROL 0x1bb3 8657 #define regOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2 8658 #define regOTG1_OTG_V_COUNT_STOP_CONTROL 0x1bb4 8659 #define regOTG1_OTG_V_COUNT_STOP_CONTROL_BASE_IDX 2 8660 #define regOTG1_OTG_V_COUNT_STOP_CONTROL2 0x1bb5 8661 #define regOTG1_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX 2 8662 #define regOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb6 8663 #define regOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 8664 #define regOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb7 8665 #define regOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 8666 #define regOTG1_OTG_V_BLANK_START_END 0x1bb8 8667 #define regOTG1_OTG_V_BLANK_START_END_BASE_IDX 2 8668 #define regOTG1_OTG_V_SYNC_A 0x1bb9 8669 #define regOTG1_OTG_V_SYNC_A_BASE_IDX 2 8670 #define regOTG1_OTG_V_SYNC_A_CNTL 0x1bba 8671 #define regOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2 8672 #define regOTG1_OTG_TRIGA_CNTL 0x1bbb 8673 #define regOTG1_OTG_TRIGA_CNTL_BASE_IDX 2 8674 #define regOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bbc 8675 #define regOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 8676 #define regOTG1_OTG_TRIGB_CNTL 0x1bbd 8677 #define regOTG1_OTG_TRIGB_CNTL_BASE_IDX 2 8678 #define regOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbe 8679 #define regOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 8680 #define regOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbf 8681 #define regOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 8682 #define regOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bc1 8683 #define regOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 8684 #define regOTG1_OTG_CONTROL 0x1bc3 8685 #define regOTG1_OTG_CONTROL_BASE_IDX 2 8686 #define regOTG1_OTG_DLPC_CONTROL 0x1bc4 8687 #define regOTG1_OTG_DLPC_CONTROL_BASE_IDX 2 8688 #define regOTG1_OTG_INTERLACE_CONTROL 0x1bc5 8689 #define regOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2 8690 #define regOTG1_OTG_INTERLACE_STATUS 0x1bc6 8691 #define regOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2 8692 #define regOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7 8693 #define regOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 8694 #define regOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8 8695 #define regOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 8696 #define regOTG1_OTG_STATUS 0x1bc9 8697 #define regOTG1_OTG_STATUS_BASE_IDX 2 8698 #define regOTG1_OTG_STATUS_POSITION 0x1bca 8699 #define regOTG1_OTG_STATUS_POSITION_BASE_IDX 2 8700 #define regOTG1_OTG_LONG_VBLANK_STATUS 0x1bcb 8701 #define regOTG1_OTG_LONG_VBLANK_STATUS_BASE_IDX 2 8702 #define regOTG1_OTG_NOM_VERT_POSITION 0x1bcc 8703 #define regOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2 8704 #define regOTG1_OTG_STATUS_FRAME_COUNT 0x1bcd 8705 #define regOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 8706 #define regOTG1_OTG_STATUS_VF_COUNT 0x1bce 8707 #define regOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2 8708 #define regOTG1_OTG_STATUS_HV_COUNT 0x1bcf 8709 #define regOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2 8710 #define regOTG1_OTG_COUNT_CONTROL 0x1bd0 8711 #define regOTG1_OTG_COUNT_CONTROL_BASE_IDX 2 8712 #define regOTG1_OTG_COUNT_RESET 0x1bd1 8713 #define regOTG1_OTG_COUNT_RESET_BASE_IDX 2 8714 #define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd2 8715 #define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 8716 #define regOTG1_OTG_VERT_SYNC_CONTROL 0x1bd3 8717 #define regOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 8718 #define regOTG1_OTG_STEREO_STATUS 0x1bd4 8719 #define regOTG1_OTG_STEREO_STATUS_BASE_IDX 2 8720 #define regOTG1_OTG_STEREO_CONTROL 0x1bd5 8721 #define regOTG1_OTG_STEREO_CONTROL_BASE_IDX 2 8722 #define regOTG1_OTG_SNAPSHOT_STATUS 0x1bd6 8723 #define regOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2 8724 #define regOTG1_OTG_SNAPSHOT_CONTROL 0x1bd7 8725 #define regOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 8726 #define regOTG1_OTG_SNAPSHOT_POSITION 0x1bd8 8727 #define regOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2 8728 #define regOTG1_OTG_SNAPSHOT_FRAME 0x1bd9 8729 #define regOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2 8730 #define regOTG1_OTG_INTERRUPT_CONTROL 0x1bda 8731 #define regOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2 8732 #define regOTG1_OTG_UPDATE_LOCK 0x1bdb 8733 #define regOTG1_OTG_UPDATE_LOCK_BASE_IDX 2 8734 #define regOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdc 8735 #define regOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 8736 #define regOTG1_OTG_MASTER_EN 0x1bdd 8737 #define regOTG1_OTG_MASTER_EN_BASE_IDX 2 8738 #define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1bdf 8739 #define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 8740 #define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be0 8741 #define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 8742 #define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be1 8743 #define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 8744 #define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be2 8745 #define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 8746 #define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be3 8747 #define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 8748 #define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1be4 8749 #define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 8750 #define regOTG1_OTG_CRC_CNTL 0x1be5 8751 #define regOTG1_OTG_CRC_CNTL_BASE_IDX 2 8752 #define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1be6 8753 #define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 8754 #define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1be7 8755 #define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 8756 #define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1be8 8757 #define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 8758 #define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1be9 8759 #define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 8760 #define regOTG1_OTG_CRC0_DATA_RG 0x1bea 8761 #define regOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2 8762 #define regOTG1_OTG_CRC0_DATA_B 0x1beb 8763 #define regOTG1_OTG_CRC0_DATA_B_BASE_IDX 2 8764 #define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bec 8765 #define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 8766 #define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bed 8767 #define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 8768 #define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bee 8769 #define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 8770 #define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bef 8771 #define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 8772 #define regOTG1_OTG_CRC1_DATA_RG 0x1bf0 8773 #define regOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2 8774 #define regOTG1_OTG_CRC1_DATA_B 0x1bf1 8775 #define regOTG1_OTG_CRC1_DATA_B_BASE_IDX 2 8776 #define regOTG1_OTG_CRC2_DATA_RG 0x1bf2 8777 #define regOTG1_OTG_CRC2_DATA_RG_BASE_IDX 2 8778 #define regOTG1_OTG_CRC2_DATA_B 0x1bf3 8779 #define regOTG1_OTG_CRC2_DATA_B_BASE_IDX 2 8780 #define regOTG1_OTG_CRC3_DATA_RG 0x1bf4 8781 #define regOTG1_OTG_CRC3_DATA_RG_BASE_IDX 2 8782 #define regOTG1_OTG_CRC3_DATA_B 0x1bf5 8783 #define regOTG1_OTG_CRC3_DATA_B_BASE_IDX 2 8784 #define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bf6 8785 #define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 8786 #define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bf7 8787 #define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 8788 #define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK 0x1bf8 8789 #define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 8790 #define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK 0x1bf9 8791 #define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 8792 #define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK 0x1bfa 8793 #define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 8794 #define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK 0x1bfb 8795 #define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 8796 #define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK 0x1bfc 8797 #define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 8798 #define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK 0x1bfd 8799 #define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 8800 #define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK 0x1bfe 8801 #define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 8802 #define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK 0x1bff 8803 #define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 8804 #define regOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c00 8805 #define regOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 8806 #define regOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c01 8807 #define regOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 8808 #define regOTG1_OTG_GSL_VSYNC_GAP 0x1c02 8809 #define regOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2 8810 #define regOTG1_OTG_MASTER_UPDATE_MODE 0x1c03 8811 #define regOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 8812 #define regOTG1_OTG_CLOCK_CONTROL 0x1c04 8813 #define regOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2 8814 #define regOTG1_OTG_VSTARTUP_PARAM 0x1c05 8815 #define regOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2 8816 #define regOTG1_OTG_VUPDATE_PARAM 0x1c06 8817 #define regOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2 8818 #define regOTG1_OTG_VREADY_PARAM 0x1c07 8819 #define regOTG1_OTG_VREADY_PARAM_BASE_IDX 2 8820 #define regOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c08 8821 #define regOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 8822 #define regOTG1_OTG_MASTER_UPDATE_LOCK 0x1c09 8823 #define regOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 8824 #define regOTG1_OTG_GSL_CONTROL 0x1c0a 8825 #define regOTG1_OTG_GSL_CONTROL_BASE_IDX 2 8826 #define regOTG1_OTG_GSL_WINDOW_X 0x1c0b 8827 #define regOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2 8828 #define regOTG1_OTG_GSL_WINDOW_Y 0x1c0c 8829 #define regOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2 8830 #define regOTG1_OTG_VUPDATE_KEEPOUT 0x1c0d 8831 #define regOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 8832 #define regOTG1_OTG_GLOBAL_CONTROL0 0x1c0e 8833 #define regOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2 8834 #define regOTG1_OTG_GLOBAL_CONTROL1 0x1c0f 8835 #define regOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2 8836 #define regOTG1_OTG_GLOBAL_CONTROL2 0x1c10 8837 #define regOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2 8838 #define regOTG1_OTG_GLOBAL_CONTROL3 0x1c11 8839 #define regOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2 8840 #define regOTG1_OTG_GLOBAL_CONTROL4 0x1c12 8841 #define regOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX 2 8842 #define regOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c13 8843 #define regOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 8844 #define regOTG1_OTG_DRR_TIMING_INT_STATUS 0x1c15 8845 #define regOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 8846 #define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c16 8847 #define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 8848 #define regOTG1_OTG_DRR_V_TOTAL_CHANGE 0x1c17 8849 #define regOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 8850 #define regOTG1_OTG_DRR_TRIGGER_WINDOW 0x1c18 8851 #define regOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 8852 #define regOTG1_OTG_DRR_CONTROL 0x1c19 8853 #define regOTG1_OTG_DRR_CONTROL_BASE_IDX 2 8854 #define regOTG1_OTG_DRR_CONTOL2 0x1c1a 8855 #define regOTG1_OTG_DRR_CONTOL2_BASE_IDX 2 8856 #define regOTG1_OTG_M_CONST_DTO0 0x1c1b 8857 #define regOTG1_OTG_M_CONST_DTO0_BASE_IDX 2 8858 #define regOTG1_OTG_M_CONST_DTO1 0x1c1c 8859 #define regOTG1_OTG_M_CONST_DTO1_BASE_IDX 2 8860 #define regOTG1_OTG_REQUEST_CONTROL 0x1c1d 8861 #define regOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2 8862 #define regOTG1_OTG_DSC_START_POSITION 0x1c1e 8863 #define regOTG1_OTG_DSC_START_POSITION_BASE_IDX 2 8864 #define regOTG1_OTG_PIPE_UPDATE_STATUS 0x1c1f 8865 #define regOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 8866 #define regOTG1_OTG_SPARE_REGISTER 0x1c20 8867 #define regOTG1_OTG_SPARE_REGISTER_BASE_IDX 2 8868 8869 8870 // addressBlock: dce_dc_optc_otg2_dispdec 8871 // base address: 0x400 8872 #define regOTG2_OTG_H_TOTAL 0x1c2a 8873 #define regOTG2_OTG_H_TOTAL_BASE_IDX 2 8874 #define regOTG2_OTG_H_BLANK_START_END 0x1c2b 8875 #define regOTG2_OTG_H_BLANK_START_END_BASE_IDX 2 8876 #define regOTG2_OTG_H_SYNC_A 0x1c2c 8877 #define regOTG2_OTG_H_SYNC_A_BASE_IDX 2 8878 #define regOTG2_OTG_H_SYNC_A_CNTL 0x1c2d 8879 #define regOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX 2 8880 #define regOTG2_OTG_H_TIMING_CNTL 0x1c2e 8881 #define regOTG2_OTG_H_TIMING_CNTL_BASE_IDX 2 8882 #define regOTG2_OTG_V_TOTAL 0x1c2f 8883 #define regOTG2_OTG_V_TOTAL_BASE_IDX 2 8884 #define regOTG2_OTG_V_TOTAL_MIN 0x1c30 8885 #define regOTG2_OTG_V_TOTAL_MIN_BASE_IDX 2 8886 #define regOTG2_OTG_V_TOTAL_MAX 0x1c31 8887 #define regOTG2_OTG_V_TOTAL_MAX_BASE_IDX 2 8888 #define regOTG2_OTG_V_TOTAL_MID 0x1c32 8889 #define regOTG2_OTG_V_TOTAL_MID_BASE_IDX 2 8890 #define regOTG2_OTG_V_TOTAL_CONTROL 0x1c33 8891 #define regOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX 2 8892 #define regOTG2_OTG_V_COUNT_STOP_CONTROL 0x1c34 8893 #define regOTG2_OTG_V_COUNT_STOP_CONTROL_BASE_IDX 2 8894 #define regOTG2_OTG_V_COUNT_STOP_CONTROL2 0x1c35 8895 #define regOTG2_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX 2 8896 #define regOTG2_OTG_V_TOTAL_INT_STATUS 0x1c36 8897 #define regOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 8898 #define regOTG2_OTG_VSYNC_NOM_INT_STATUS 0x1c37 8899 #define regOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 8900 #define regOTG2_OTG_V_BLANK_START_END 0x1c38 8901 #define regOTG2_OTG_V_BLANK_START_END_BASE_IDX 2 8902 #define regOTG2_OTG_V_SYNC_A 0x1c39 8903 #define regOTG2_OTG_V_SYNC_A_BASE_IDX 2 8904 #define regOTG2_OTG_V_SYNC_A_CNTL 0x1c3a 8905 #define regOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX 2 8906 #define regOTG2_OTG_TRIGA_CNTL 0x1c3b 8907 #define regOTG2_OTG_TRIGA_CNTL_BASE_IDX 2 8908 #define regOTG2_OTG_TRIGA_MANUAL_TRIG 0x1c3c 8909 #define regOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 8910 #define regOTG2_OTG_TRIGB_CNTL 0x1c3d 8911 #define regOTG2_OTG_TRIGB_CNTL_BASE_IDX 2 8912 #define regOTG2_OTG_TRIGB_MANUAL_TRIG 0x1c3e 8913 #define regOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 8914 #define regOTG2_OTG_FORCE_COUNT_NOW_CNTL 0x1c3f 8915 #define regOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 8916 #define regOTG2_OTG_STEREO_FORCE_NEXT_EYE 0x1c41 8917 #define regOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 8918 #define regOTG2_OTG_CONTROL 0x1c43 8919 #define regOTG2_OTG_CONTROL_BASE_IDX 2 8920 #define regOTG2_OTG_DLPC_CONTROL 0x1c44 8921 #define regOTG2_OTG_DLPC_CONTROL_BASE_IDX 2 8922 #define regOTG2_OTG_INTERLACE_CONTROL 0x1c45 8923 #define regOTG2_OTG_INTERLACE_CONTROL_BASE_IDX 2 8924 #define regOTG2_OTG_INTERLACE_STATUS 0x1c46 8925 #define regOTG2_OTG_INTERLACE_STATUS_BASE_IDX 2 8926 #define regOTG2_OTG_PIXEL_DATA_READBACK0 0x1c47 8927 #define regOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 8928 #define regOTG2_OTG_PIXEL_DATA_READBACK1 0x1c48 8929 #define regOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 8930 #define regOTG2_OTG_STATUS 0x1c49 8931 #define regOTG2_OTG_STATUS_BASE_IDX 2 8932 #define regOTG2_OTG_STATUS_POSITION 0x1c4a 8933 #define regOTG2_OTG_STATUS_POSITION_BASE_IDX 2 8934 #define regOTG2_OTG_LONG_VBLANK_STATUS 0x1c4b 8935 #define regOTG2_OTG_LONG_VBLANK_STATUS_BASE_IDX 2 8936 #define regOTG2_OTG_NOM_VERT_POSITION 0x1c4c 8937 #define regOTG2_OTG_NOM_VERT_POSITION_BASE_IDX 2 8938 #define regOTG2_OTG_STATUS_FRAME_COUNT 0x1c4d 8939 #define regOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 8940 #define regOTG2_OTG_STATUS_VF_COUNT 0x1c4e 8941 #define regOTG2_OTG_STATUS_VF_COUNT_BASE_IDX 2 8942 #define regOTG2_OTG_STATUS_HV_COUNT 0x1c4f 8943 #define regOTG2_OTG_STATUS_HV_COUNT_BASE_IDX 2 8944 #define regOTG2_OTG_COUNT_CONTROL 0x1c50 8945 #define regOTG2_OTG_COUNT_CONTROL_BASE_IDX 2 8946 #define regOTG2_OTG_COUNT_RESET 0x1c51 8947 #define regOTG2_OTG_COUNT_RESET_BASE_IDX 2 8948 #define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1c52 8949 #define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 8950 #define regOTG2_OTG_VERT_SYNC_CONTROL 0x1c53 8951 #define regOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 8952 #define regOTG2_OTG_STEREO_STATUS 0x1c54 8953 #define regOTG2_OTG_STEREO_STATUS_BASE_IDX 2 8954 #define regOTG2_OTG_STEREO_CONTROL 0x1c55 8955 #define regOTG2_OTG_STEREO_CONTROL_BASE_IDX 2 8956 #define regOTG2_OTG_SNAPSHOT_STATUS 0x1c56 8957 #define regOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX 2 8958 #define regOTG2_OTG_SNAPSHOT_CONTROL 0x1c57 8959 #define regOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 8960 #define regOTG2_OTG_SNAPSHOT_POSITION 0x1c58 8961 #define regOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX 2 8962 #define regOTG2_OTG_SNAPSHOT_FRAME 0x1c59 8963 #define regOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX 2 8964 #define regOTG2_OTG_INTERRUPT_CONTROL 0x1c5a 8965 #define regOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX 2 8966 #define regOTG2_OTG_UPDATE_LOCK 0x1c5b 8967 #define regOTG2_OTG_UPDATE_LOCK_BASE_IDX 2 8968 #define regOTG2_OTG_DOUBLE_BUFFER_CONTROL 0x1c5c 8969 #define regOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 8970 #define regOTG2_OTG_MASTER_EN 0x1c5d 8971 #define regOTG2_OTG_MASTER_EN_BASE_IDX 2 8972 #define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0x1c5f 8973 #define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 8974 #define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1c60 8975 #define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 8976 #define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0x1c61 8977 #define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 8978 #define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1c62 8979 #define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 8980 #define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0x1c63 8981 #define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 8982 #define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1c64 8983 #define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 8984 #define regOTG2_OTG_CRC_CNTL 0x1c65 8985 #define regOTG2_OTG_CRC_CNTL_BASE_IDX 2 8986 #define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0x1c66 8987 #define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 8988 #define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0x1c67 8989 #define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 8990 #define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0x1c68 8991 #define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 8992 #define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0x1c69 8993 #define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 8994 #define regOTG2_OTG_CRC0_DATA_RG 0x1c6a 8995 #define regOTG2_OTG_CRC0_DATA_RG_BASE_IDX 2 8996 #define regOTG2_OTG_CRC0_DATA_B 0x1c6b 8997 #define regOTG2_OTG_CRC0_DATA_B_BASE_IDX 2 8998 #define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0x1c6c 8999 #define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 9000 #define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0x1c6d 9001 #define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 9002 #define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0x1c6e 9003 #define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 9004 #define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0x1c6f 9005 #define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 9006 #define regOTG2_OTG_CRC1_DATA_RG 0x1c70 9007 #define regOTG2_OTG_CRC1_DATA_RG_BASE_IDX 2 9008 #define regOTG2_OTG_CRC1_DATA_B 0x1c71 9009 #define regOTG2_OTG_CRC1_DATA_B_BASE_IDX 2 9010 #define regOTG2_OTG_CRC2_DATA_RG 0x1c72 9011 #define regOTG2_OTG_CRC2_DATA_RG_BASE_IDX 2 9012 #define regOTG2_OTG_CRC2_DATA_B 0x1c73 9013 #define regOTG2_OTG_CRC2_DATA_B_BASE_IDX 2 9014 #define regOTG2_OTG_CRC3_DATA_RG 0x1c74 9015 #define regOTG2_OTG_CRC3_DATA_RG_BASE_IDX 2 9016 #define regOTG2_OTG_CRC3_DATA_B 0x1c75 9017 #define regOTG2_OTG_CRC3_DATA_B_BASE_IDX 2 9018 #define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0x1c76 9019 #define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 9020 #define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c77 9021 #define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 9022 #define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK 0x1c78 9023 #define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 9024 #define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK 0x1c79 9025 #define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 9026 #define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK 0x1c7a 9027 #define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 9028 #define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK 0x1c7b 9029 #define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 9030 #define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK 0x1c7c 9031 #define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 9032 #define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK 0x1c7d 9033 #define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 9034 #define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK 0x1c7e 9035 #define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 9036 #define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK 0x1c7f 9037 #define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 9038 #define regOTG2_OTG_STATIC_SCREEN_CONTROL 0x1c80 9039 #define regOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 9040 #define regOTG2_OTG_3D_STRUCTURE_CONTROL 0x1c81 9041 #define regOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 9042 #define regOTG2_OTG_GSL_VSYNC_GAP 0x1c82 9043 #define regOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX 2 9044 #define regOTG2_OTG_MASTER_UPDATE_MODE 0x1c83 9045 #define regOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 9046 #define regOTG2_OTG_CLOCK_CONTROL 0x1c84 9047 #define regOTG2_OTG_CLOCK_CONTROL_BASE_IDX 2 9048 #define regOTG2_OTG_VSTARTUP_PARAM 0x1c85 9049 #define regOTG2_OTG_VSTARTUP_PARAM_BASE_IDX 2 9050 #define regOTG2_OTG_VUPDATE_PARAM 0x1c86 9051 #define regOTG2_OTG_VUPDATE_PARAM_BASE_IDX 2 9052 #define regOTG2_OTG_VREADY_PARAM 0x1c87 9053 #define regOTG2_OTG_VREADY_PARAM_BASE_IDX 2 9054 #define regOTG2_OTG_GLOBAL_SYNC_STATUS 0x1c88 9055 #define regOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 9056 #define regOTG2_OTG_MASTER_UPDATE_LOCK 0x1c89 9057 #define regOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 9058 #define regOTG2_OTG_GSL_CONTROL 0x1c8a 9059 #define regOTG2_OTG_GSL_CONTROL_BASE_IDX 2 9060 #define regOTG2_OTG_GSL_WINDOW_X 0x1c8b 9061 #define regOTG2_OTG_GSL_WINDOW_X_BASE_IDX 2 9062 #define regOTG2_OTG_GSL_WINDOW_Y 0x1c8c 9063 #define regOTG2_OTG_GSL_WINDOW_Y_BASE_IDX 2 9064 #define regOTG2_OTG_VUPDATE_KEEPOUT 0x1c8d 9065 #define regOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 9066 #define regOTG2_OTG_GLOBAL_CONTROL0 0x1c8e 9067 #define regOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX 2 9068 #define regOTG2_OTG_GLOBAL_CONTROL1 0x1c8f 9069 #define regOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX 2 9070 #define regOTG2_OTG_GLOBAL_CONTROL2 0x1c90 9071 #define regOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX 2 9072 #define regOTG2_OTG_GLOBAL_CONTROL3 0x1c91 9073 #define regOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX 2 9074 #define regOTG2_OTG_GLOBAL_CONTROL4 0x1c92 9075 #define regOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX 2 9076 #define regOTG2_OTG_TRIG_MANUAL_CONTROL 0x1c93 9077 #define regOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 9078 #define regOTG2_OTG_DRR_TIMING_INT_STATUS 0x1c95 9079 #define regOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 9080 #define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c96 9081 #define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 9082 #define regOTG2_OTG_DRR_V_TOTAL_CHANGE 0x1c97 9083 #define regOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 9084 #define regOTG2_OTG_DRR_TRIGGER_WINDOW 0x1c98 9085 #define regOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 9086 #define regOTG2_OTG_DRR_CONTROL 0x1c99 9087 #define regOTG2_OTG_DRR_CONTROL_BASE_IDX 2 9088 #define regOTG2_OTG_DRR_CONTOL2 0x1c9a 9089 #define regOTG2_OTG_DRR_CONTOL2_BASE_IDX 2 9090 #define regOTG2_OTG_M_CONST_DTO0 0x1c9b 9091 #define regOTG2_OTG_M_CONST_DTO0_BASE_IDX 2 9092 #define regOTG2_OTG_M_CONST_DTO1 0x1c9c 9093 #define regOTG2_OTG_M_CONST_DTO1_BASE_IDX 2 9094 #define regOTG2_OTG_REQUEST_CONTROL 0x1c9d 9095 #define regOTG2_OTG_REQUEST_CONTROL_BASE_IDX 2 9096 #define regOTG2_OTG_DSC_START_POSITION 0x1c9e 9097 #define regOTG2_OTG_DSC_START_POSITION_BASE_IDX 2 9098 #define regOTG2_OTG_PIPE_UPDATE_STATUS 0x1c9f 9099 #define regOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 9100 #define regOTG2_OTG_SPARE_REGISTER 0x1ca0 9101 #define regOTG2_OTG_SPARE_REGISTER_BASE_IDX 2 9102 9103 9104 // addressBlock: dce_dc_optc_otg3_dispdec 9105 // base address: 0x600 9106 #define regOTG3_OTG_H_TOTAL 0x1caa 9107 #define regOTG3_OTG_H_TOTAL_BASE_IDX 2 9108 #define regOTG3_OTG_H_BLANK_START_END 0x1cab 9109 #define regOTG3_OTG_H_BLANK_START_END_BASE_IDX 2 9110 #define regOTG3_OTG_H_SYNC_A 0x1cac 9111 #define regOTG3_OTG_H_SYNC_A_BASE_IDX 2 9112 #define regOTG3_OTG_H_SYNC_A_CNTL 0x1cad 9113 #define regOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX 2 9114 #define regOTG3_OTG_H_TIMING_CNTL 0x1cae 9115 #define regOTG3_OTG_H_TIMING_CNTL_BASE_IDX 2 9116 #define regOTG3_OTG_V_TOTAL 0x1caf 9117 #define regOTG3_OTG_V_TOTAL_BASE_IDX 2 9118 #define regOTG3_OTG_V_TOTAL_MIN 0x1cb0 9119 #define regOTG3_OTG_V_TOTAL_MIN_BASE_IDX 2 9120 #define regOTG3_OTG_V_TOTAL_MAX 0x1cb1 9121 #define regOTG3_OTG_V_TOTAL_MAX_BASE_IDX 2 9122 #define regOTG3_OTG_V_TOTAL_MID 0x1cb2 9123 #define regOTG3_OTG_V_TOTAL_MID_BASE_IDX 2 9124 #define regOTG3_OTG_V_TOTAL_CONTROL 0x1cb3 9125 #define regOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX 2 9126 #define regOTG3_OTG_V_COUNT_STOP_CONTROL 0x1cb4 9127 #define regOTG3_OTG_V_COUNT_STOP_CONTROL_BASE_IDX 2 9128 #define regOTG3_OTG_V_COUNT_STOP_CONTROL2 0x1cb5 9129 #define regOTG3_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX 2 9130 #define regOTG3_OTG_V_TOTAL_INT_STATUS 0x1cb6 9131 #define regOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 9132 #define regOTG3_OTG_VSYNC_NOM_INT_STATUS 0x1cb7 9133 #define regOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 9134 #define regOTG3_OTG_V_BLANK_START_END 0x1cb8 9135 #define regOTG3_OTG_V_BLANK_START_END_BASE_IDX 2 9136 #define regOTG3_OTG_V_SYNC_A 0x1cb9 9137 #define regOTG3_OTG_V_SYNC_A_BASE_IDX 2 9138 #define regOTG3_OTG_V_SYNC_A_CNTL 0x1cba 9139 #define regOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX 2 9140 #define regOTG3_OTG_TRIGA_CNTL 0x1cbb 9141 #define regOTG3_OTG_TRIGA_CNTL_BASE_IDX 2 9142 #define regOTG3_OTG_TRIGA_MANUAL_TRIG 0x1cbc 9143 #define regOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 9144 #define regOTG3_OTG_TRIGB_CNTL 0x1cbd 9145 #define regOTG3_OTG_TRIGB_CNTL_BASE_IDX 2 9146 #define regOTG3_OTG_TRIGB_MANUAL_TRIG 0x1cbe 9147 #define regOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 9148 #define regOTG3_OTG_FORCE_COUNT_NOW_CNTL 0x1cbf 9149 #define regOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 9150 #define regOTG3_OTG_STEREO_FORCE_NEXT_EYE 0x1cc1 9151 #define regOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 9152 #define regOTG3_OTG_CONTROL 0x1cc3 9153 #define regOTG3_OTG_CONTROL_BASE_IDX 2 9154 #define regOTG3_OTG_DLPC_CONTROL 0x1cc4 9155 #define regOTG3_OTG_DLPC_CONTROL_BASE_IDX 2 9156 #define regOTG3_OTG_INTERLACE_CONTROL 0x1cc5 9157 #define regOTG3_OTG_INTERLACE_CONTROL_BASE_IDX 2 9158 #define regOTG3_OTG_INTERLACE_STATUS 0x1cc6 9159 #define regOTG3_OTG_INTERLACE_STATUS_BASE_IDX 2 9160 #define regOTG3_OTG_PIXEL_DATA_READBACK0 0x1cc7 9161 #define regOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 9162 #define regOTG3_OTG_PIXEL_DATA_READBACK1 0x1cc8 9163 #define regOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 9164 #define regOTG3_OTG_STATUS 0x1cc9 9165 #define regOTG3_OTG_STATUS_BASE_IDX 2 9166 #define regOTG3_OTG_STATUS_POSITION 0x1cca 9167 #define regOTG3_OTG_STATUS_POSITION_BASE_IDX 2 9168 #define regOTG3_OTG_LONG_VBLANK_STATUS 0x1ccb 9169 #define regOTG3_OTG_LONG_VBLANK_STATUS_BASE_IDX 2 9170 #define regOTG3_OTG_NOM_VERT_POSITION 0x1ccc 9171 #define regOTG3_OTG_NOM_VERT_POSITION_BASE_IDX 2 9172 #define regOTG3_OTG_STATUS_FRAME_COUNT 0x1ccd 9173 #define regOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 9174 #define regOTG3_OTG_STATUS_VF_COUNT 0x1cce 9175 #define regOTG3_OTG_STATUS_VF_COUNT_BASE_IDX 2 9176 #define regOTG3_OTG_STATUS_HV_COUNT 0x1ccf 9177 #define regOTG3_OTG_STATUS_HV_COUNT_BASE_IDX 2 9178 #define regOTG3_OTG_COUNT_CONTROL 0x1cd0 9179 #define regOTG3_OTG_COUNT_CONTROL_BASE_IDX 2 9180 #define regOTG3_OTG_COUNT_RESET 0x1cd1 9181 #define regOTG3_OTG_COUNT_RESET_BASE_IDX 2 9182 #define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1cd2 9183 #define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 9184 #define regOTG3_OTG_VERT_SYNC_CONTROL 0x1cd3 9185 #define regOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 9186 #define regOTG3_OTG_STEREO_STATUS 0x1cd4 9187 #define regOTG3_OTG_STEREO_STATUS_BASE_IDX 2 9188 #define regOTG3_OTG_STEREO_CONTROL 0x1cd5 9189 #define regOTG3_OTG_STEREO_CONTROL_BASE_IDX 2 9190 #define regOTG3_OTG_SNAPSHOT_STATUS 0x1cd6 9191 #define regOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX 2 9192 #define regOTG3_OTG_SNAPSHOT_CONTROL 0x1cd7 9193 #define regOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 9194 #define regOTG3_OTG_SNAPSHOT_POSITION 0x1cd8 9195 #define regOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX 2 9196 #define regOTG3_OTG_SNAPSHOT_FRAME 0x1cd9 9197 #define regOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX 2 9198 #define regOTG3_OTG_INTERRUPT_CONTROL 0x1cda 9199 #define regOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX 2 9200 #define regOTG3_OTG_UPDATE_LOCK 0x1cdb 9201 #define regOTG3_OTG_UPDATE_LOCK_BASE_IDX 2 9202 #define regOTG3_OTG_DOUBLE_BUFFER_CONTROL 0x1cdc 9203 #define regOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 9204 #define regOTG3_OTG_MASTER_EN 0x1cdd 9205 #define regOTG3_OTG_MASTER_EN_BASE_IDX 2 9206 #define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0x1cdf 9207 #define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 9208 #define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1ce0 9209 #define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 9210 #define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0x1ce1 9211 #define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 9212 #define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1ce2 9213 #define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 9214 #define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0x1ce3 9215 #define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 9216 #define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1ce4 9217 #define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 9218 #define regOTG3_OTG_CRC_CNTL 0x1ce5 9219 #define regOTG3_OTG_CRC_CNTL_BASE_IDX 2 9220 #define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0x1ce6 9221 #define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 9222 #define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0x1ce7 9223 #define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 9224 #define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0x1ce8 9225 #define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 9226 #define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0x1ce9 9227 #define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 9228 #define regOTG3_OTG_CRC0_DATA_RG 0x1cea 9229 #define regOTG3_OTG_CRC0_DATA_RG_BASE_IDX 2 9230 #define regOTG3_OTG_CRC0_DATA_B 0x1ceb 9231 #define regOTG3_OTG_CRC0_DATA_B_BASE_IDX 2 9232 #define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0x1cec 9233 #define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 9234 #define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0x1ced 9235 #define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 9236 #define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0x1cee 9237 #define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 9238 #define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0x1cef 9239 #define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 9240 #define regOTG3_OTG_CRC1_DATA_RG 0x1cf0 9241 #define regOTG3_OTG_CRC1_DATA_RG_BASE_IDX 2 9242 #define regOTG3_OTG_CRC1_DATA_B 0x1cf1 9243 #define regOTG3_OTG_CRC1_DATA_B_BASE_IDX 2 9244 #define regOTG3_OTG_CRC2_DATA_RG 0x1cf2 9245 #define regOTG3_OTG_CRC2_DATA_RG_BASE_IDX 2 9246 #define regOTG3_OTG_CRC2_DATA_B 0x1cf3 9247 #define regOTG3_OTG_CRC2_DATA_B_BASE_IDX 2 9248 #define regOTG3_OTG_CRC3_DATA_RG 0x1cf4 9249 #define regOTG3_OTG_CRC3_DATA_RG_BASE_IDX 2 9250 #define regOTG3_OTG_CRC3_DATA_B 0x1cf5 9251 #define regOTG3_OTG_CRC3_DATA_B_BASE_IDX 2 9252 #define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0x1cf6 9253 #define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 9254 #define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1cf7 9255 #define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 9256 #define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK 0x1cf8 9257 #define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 9258 #define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK 0x1cf9 9259 #define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 9260 #define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK 0x1cfa 9261 #define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 9262 #define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK 0x1cfb 9263 #define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 9264 #define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK 0x1cfc 9265 #define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 9266 #define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK 0x1cfd 9267 #define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 9268 #define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK 0x1cfe 9269 #define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 9270 #define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK 0x1cff 9271 #define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 9272 #define regOTG3_OTG_STATIC_SCREEN_CONTROL 0x1d00 9273 #define regOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 9274 #define regOTG3_OTG_3D_STRUCTURE_CONTROL 0x1d01 9275 #define regOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 9276 #define regOTG3_OTG_GSL_VSYNC_GAP 0x1d02 9277 #define regOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX 2 9278 #define regOTG3_OTG_MASTER_UPDATE_MODE 0x1d03 9279 #define regOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 9280 #define regOTG3_OTG_CLOCK_CONTROL 0x1d04 9281 #define regOTG3_OTG_CLOCK_CONTROL_BASE_IDX 2 9282 #define regOTG3_OTG_VSTARTUP_PARAM 0x1d05 9283 #define regOTG3_OTG_VSTARTUP_PARAM_BASE_IDX 2 9284 #define regOTG3_OTG_VUPDATE_PARAM 0x1d06 9285 #define regOTG3_OTG_VUPDATE_PARAM_BASE_IDX 2 9286 #define regOTG3_OTG_VREADY_PARAM 0x1d07 9287 #define regOTG3_OTG_VREADY_PARAM_BASE_IDX 2 9288 #define regOTG3_OTG_GLOBAL_SYNC_STATUS 0x1d08 9289 #define regOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 9290 #define regOTG3_OTG_MASTER_UPDATE_LOCK 0x1d09 9291 #define regOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 9292 #define regOTG3_OTG_GSL_CONTROL 0x1d0a 9293 #define regOTG3_OTG_GSL_CONTROL_BASE_IDX 2 9294 #define regOTG3_OTG_GSL_WINDOW_X 0x1d0b 9295 #define regOTG3_OTG_GSL_WINDOW_X_BASE_IDX 2 9296 #define regOTG3_OTG_GSL_WINDOW_Y 0x1d0c 9297 #define regOTG3_OTG_GSL_WINDOW_Y_BASE_IDX 2 9298 #define regOTG3_OTG_VUPDATE_KEEPOUT 0x1d0d 9299 #define regOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 9300 #define regOTG3_OTG_GLOBAL_CONTROL0 0x1d0e 9301 #define regOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX 2 9302 #define regOTG3_OTG_GLOBAL_CONTROL1 0x1d0f 9303 #define regOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX 2 9304 #define regOTG3_OTG_GLOBAL_CONTROL2 0x1d10 9305 #define regOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX 2 9306 #define regOTG3_OTG_GLOBAL_CONTROL3 0x1d11 9307 #define regOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX 2 9308 #define regOTG3_OTG_GLOBAL_CONTROL4 0x1d12 9309 #define regOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX 2 9310 #define regOTG3_OTG_TRIG_MANUAL_CONTROL 0x1d13 9311 #define regOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 9312 #define regOTG3_OTG_DRR_TIMING_INT_STATUS 0x1d15 9313 #define regOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 9314 #define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE 0x1d16 9315 #define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 9316 #define regOTG3_OTG_DRR_V_TOTAL_CHANGE 0x1d17 9317 #define regOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 9318 #define regOTG3_OTG_DRR_TRIGGER_WINDOW 0x1d18 9319 #define regOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 9320 #define regOTG3_OTG_DRR_CONTROL 0x1d19 9321 #define regOTG3_OTG_DRR_CONTROL_BASE_IDX 2 9322 #define regOTG3_OTG_DRR_CONTOL2 0x1d1a 9323 #define regOTG3_OTG_DRR_CONTOL2_BASE_IDX 2 9324 #define regOTG3_OTG_M_CONST_DTO0 0x1d1b 9325 #define regOTG3_OTG_M_CONST_DTO0_BASE_IDX 2 9326 #define regOTG3_OTG_M_CONST_DTO1 0x1d1c 9327 #define regOTG3_OTG_M_CONST_DTO1_BASE_IDX 2 9328 #define regOTG3_OTG_REQUEST_CONTROL 0x1d1d 9329 #define regOTG3_OTG_REQUEST_CONTROL_BASE_IDX 2 9330 #define regOTG3_OTG_DSC_START_POSITION 0x1d1e 9331 #define regOTG3_OTG_DSC_START_POSITION_BASE_IDX 2 9332 #define regOTG3_OTG_PIPE_UPDATE_STATUS 0x1d1f 9333 #define regOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 9334 #define regOTG3_OTG_SPARE_REGISTER 0x1d20 9335 #define regOTG3_OTG_SPARE_REGISTER_BASE_IDX 2 9336 9337 9338 // addressBlock: dce_dc_optc_otg_crc320_dispdec 9339 // base address: 0x0 9340 #define regOTG_CRC320_OTG_CRC0_DATA_R32 0x1dd2 9341 #define regOTG_CRC320_OTG_CRC0_DATA_R32_BASE_IDX 2 9342 #define regOTG_CRC320_OTG_CRC0_DATA_G32 0x1dd3 9343 #define regOTG_CRC320_OTG_CRC0_DATA_G32_BASE_IDX 2 9344 #define regOTG_CRC320_OTG_CRC0_DATA_B32 0x1dd4 9345 #define regOTG_CRC320_OTG_CRC0_DATA_B32_BASE_IDX 2 9346 #define regOTG_CRC320_OTG_CRC0_DATA_C32 0x1dd5 9347 #define regOTG_CRC320_OTG_CRC0_DATA_C32_BASE_IDX 2 9348 #define regOTG_CRC320_OTG_CRC0_DATA_AES 0x1dd6 9349 #define regOTG_CRC320_OTG_CRC0_DATA_AES_BASE_IDX 2 9350 #define regOTG_CRC320_OTG_CRC1_DATA_R32 0x1dd7 9351 #define regOTG_CRC320_OTG_CRC1_DATA_R32_BASE_IDX 2 9352 #define regOTG_CRC320_OTG_CRC1_DATA_G32 0x1dd8 9353 #define regOTG_CRC320_OTG_CRC1_DATA_G32_BASE_IDX 2 9354 #define regOTG_CRC320_OTG_CRC1_DATA_B32 0x1dd9 9355 #define regOTG_CRC320_OTG_CRC1_DATA_B32_BASE_IDX 2 9356 #define regOTG_CRC320_OTG_CRC1_DATA_C32 0x1dda 9357 #define regOTG_CRC320_OTG_CRC1_DATA_C32_BASE_IDX 2 9358 #define regOTG_CRC320_OTG_CRC2_DATA_R32 0x1ddb 9359 #define regOTG_CRC320_OTG_CRC2_DATA_R32_BASE_IDX 2 9360 #define regOTG_CRC320_OTG_CRC2_DATA_G32 0x1ddc 9361 #define regOTG_CRC320_OTG_CRC2_DATA_G32_BASE_IDX 2 9362 #define regOTG_CRC320_OTG_CRC2_DATA_B32 0x1ddd 9363 #define regOTG_CRC320_OTG_CRC2_DATA_B32_BASE_IDX 2 9364 #define regOTG_CRC320_OTG_CRC2_DATA_C32 0x1dde 9365 #define regOTG_CRC320_OTG_CRC2_DATA_C32_BASE_IDX 2 9366 #define regOTG_CRC320_OTG_CRC3_DATA_R32 0x1ddf 9367 #define regOTG_CRC320_OTG_CRC3_DATA_R32_BASE_IDX 2 9368 #define regOTG_CRC320_OTG_CRC3_DATA_G32 0x1de0 9369 #define regOTG_CRC320_OTG_CRC3_DATA_G32_BASE_IDX 2 9370 #define regOTG_CRC320_OTG_CRC3_DATA_B32 0x1de1 9371 #define regOTG_CRC320_OTG_CRC3_DATA_B32_BASE_IDX 2 9372 #define regOTG_CRC320_OTG_CRC3_DATA_C32 0x1de2 9373 #define regOTG_CRC320_OTG_CRC3_DATA_C32_BASE_IDX 2 9374 9375 9376 // addressBlock: dce_dc_optc_otg_crc321_dispdec 9377 // base address: 0x50 9378 #define regOTG_CRC321_OTG_CRC0_DATA_R32 0x1de6 9379 #define regOTG_CRC321_OTG_CRC0_DATA_R32_BASE_IDX 2 9380 #define regOTG_CRC321_OTG_CRC0_DATA_G32 0x1de7 9381 #define regOTG_CRC321_OTG_CRC0_DATA_G32_BASE_IDX 2 9382 #define regOTG_CRC321_OTG_CRC0_DATA_B32 0x1de8 9383 #define regOTG_CRC321_OTG_CRC0_DATA_B32_BASE_IDX 2 9384 #define regOTG_CRC321_OTG_CRC0_DATA_C32 0x1de9 9385 #define regOTG_CRC321_OTG_CRC0_DATA_C32_BASE_IDX 2 9386 #define regOTG_CRC321_OTG_CRC0_DATA_AES 0x1dea 9387 #define regOTG_CRC321_OTG_CRC0_DATA_AES_BASE_IDX 2 9388 #define regOTG_CRC321_OTG_CRC1_DATA_R32 0x1deb 9389 #define regOTG_CRC321_OTG_CRC1_DATA_R32_BASE_IDX 2 9390 #define regOTG_CRC321_OTG_CRC1_DATA_G32 0x1dec 9391 #define regOTG_CRC321_OTG_CRC1_DATA_G32_BASE_IDX 2 9392 #define regOTG_CRC321_OTG_CRC1_DATA_B32 0x1ded 9393 #define regOTG_CRC321_OTG_CRC1_DATA_B32_BASE_IDX 2 9394 #define regOTG_CRC321_OTG_CRC1_DATA_C32 0x1dee 9395 #define regOTG_CRC321_OTG_CRC1_DATA_C32_BASE_IDX 2 9396 #define regOTG_CRC321_OTG_CRC2_DATA_R32 0x1def 9397 #define regOTG_CRC321_OTG_CRC2_DATA_R32_BASE_IDX 2 9398 #define regOTG_CRC321_OTG_CRC2_DATA_G32 0x1df0 9399 #define regOTG_CRC321_OTG_CRC2_DATA_G32_BASE_IDX 2 9400 #define regOTG_CRC321_OTG_CRC2_DATA_B32 0x1df1 9401 #define regOTG_CRC321_OTG_CRC2_DATA_B32_BASE_IDX 2 9402 #define regOTG_CRC321_OTG_CRC2_DATA_C32 0x1df2 9403 #define regOTG_CRC321_OTG_CRC2_DATA_C32_BASE_IDX 2 9404 #define regOTG_CRC321_OTG_CRC3_DATA_R32 0x1df3 9405 #define regOTG_CRC321_OTG_CRC3_DATA_R32_BASE_IDX 2 9406 #define regOTG_CRC321_OTG_CRC3_DATA_G32 0x1df4 9407 #define regOTG_CRC321_OTG_CRC3_DATA_G32_BASE_IDX 2 9408 #define regOTG_CRC321_OTG_CRC3_DATA_B32 0x1df5 9409 #define regOTG_CRC321_OTG_CRC3_DATA_B32_BASE_IDX 2 9410 #define regOTG_CRC321_OTG_CRC3_DATA_C32 0x1df6 9411 #define regOTG_CRC321_OTG_CRC3_DATA_C32_BASE_IDX 2 9412 9413 9414 // addressBlock: dce_dc_optc_otg_crc322_dispdec 9415 // base address: 0xa0 9416 #define regOTG_CRC322_OTG_CRC0_DATA_R32 0x1dfa 9417 #define regOTG_CRC322_OTG_CRC0_DATA_R32_BASE_IDX 2 9418 #define regOTG_CRC322_OTG_CRC0_DATA_G32 0x1dfb 9419 #define regOTG_CRC322_OTG_CRC0_DATA_G32_BASE_IDX 2 9420 #define regOTG_CRC322_OTG_CRC0_DATA_B32 0x1dfc 9421 #define regOTG_CRC322_OTG_CRC0_DATA_B32_BASE_IDX 2 9422 #define regOTG_CRC322_OTG_CRC0_DATA_C32 0x1dfd 9423 #define regOTG_CRC322_OTG_CRC0_DATA_C32_BASE_IDX 2 9424 #define regOTG_CRC322_OTG_CRC0_DATA_AES 0x1dfe 9425 #define regOTG_CRC322_OTG_CRC0_DATA_AES_BASE_IDX 2 9426 #define regOTG_CRC322_OTG_CRC1_DATA_R32 0x1dff 9427 #define regOTG_CRC322_OTG_CRC1_DATA_R32_BASE_IDX 2 9428 #define regOTG_CRC322_OTG_CRC1_DATA_G32 0x1e00 9429 #define regOTG_CRC322_OTG_CRC1_DATA_G32_BASE_IDX 2 9430 #define regOTG_CRC322_OTG_CRC1_DATA_B32 0x1e01 9431 #define regOTG_CRC322_OTG_CRC1_DATA_B32_BASE_IDX 2 9432 #define regOTG_CRC322_OTG_CRC1_DATA_C32 0x1e02 9433 #define regOTG_CRC322_OTG_CRC1_DATA_C32_BASE_IDX 2 9434 #define regOTG_CRC322_OTG_CRC2_DATA_R32 0x1e03 9435 #define regOTG_CRC322_OTG_CRC2_DATA_R32_BASE_IDX 2 9436 #define regOTG_CRC322_OTG_CRC2_DATA_G32 0x1e04 9437 #define regOTG_CRC322_OTG_CRC2_DATA_G32_BASE_IDX 2 9438 #define regOTG_CRC322_OTG_CRC2_DATA_B32 0x1e05 9439 #define regOTG_CRC322_OTG_CRC2_DATA_B32_BASE_IDX 2 9440 #define regOTG_CRC322_OTG_CRC2_DATA_C32 0x1e06 9441 #define regOTG_CRC322_OTG_CRC2_DATA_C32_BASE_IDX 2 9442 #define regOTG_CRC322_OTG_CRC3_DATA_R32 0x1e07 9443 #define regOTG_CRC322_OTG_CRC3_DATA_R32_BASE_IDX 2 9444 #define regOTG_CRC322_OTG_CRC3_DATA_G32 0x1e08 9445 #define regOTG_CRC322_OTG_CRC3_DATA_G32_BASE_IDX 2 9446 #define regOTG_CRC322_OTG_CRC3_DATA_B32 0x1e09 9447 #define regOTG_CRC322_OTG_CRC3_DATA_B32_BASE_IDX 2 9448 #define regOTG_CRC322_OTG_CRC3_DATA_C32 0x1e0a 9449 #define regOTG_CRC322_OTG_CRC3_DATA_C32_BASE_IDX 2 9450 9451 9452 // addressBlock: dce_dc_optc_otg_crc323_dispdec 9453 // base address: 0xf0 9454 #define regOTG_CRC323_OTG_CRC0_DATA_R32 0x1e0e 9455 #define regOTG_CRC323_OTG_CRC0_DATA_R32_BASE_IDX 2 9456 #define regOTG_CRC323_OTG_CRC0_DATA_G32 0x1e0f 9457 #define regOTG_CRC323_OTG_CRC0_DATA_G32_BASE_IDX 2 9458 #define regOTG_CRC323_OTG_CRC0_DATA_B32 0x1e10 9459 #define regOTG_CRC323_OTG_CRC0_DATA_B32_BASE_IDX 2 9460 #define regOTG_CRC323_OTG_CRC0_DATA_C32 0x1e11 9461 #define regOTG_CRC323_OTG_CRC0_DATA_C32_BASE_IDX 2 9462 #define regOTG_CRC323_OTG_CRC0_DATA_AES 0x1e12 9463 #define regOTG_CRC323_OTG_CRC0_DATA_AES_BASE_IDX 2 9464 #define regOTG_CRC323_OTG_CRC1_DATA_R32 0x1e13 9465 #define regOTG_CRC323_OTG_CRC1_DATA_R32_BASE_IDX 2 9466 #define regOTG_CRC323_OTG_CRC1_DATA_G32 0x1e14 9467 #define regOTG_CRC323_OTG_CRC1_DATA_G32_BASE_IDX 2 9468 #define regOTG_CRC323_OTG_CRC1_DATA_B32 0x1e15 9469 #define regOTG_CRC323_OTG_CRC1_DATA_B32_BASE_IDX 2 9470 #define regOTG_CRC323_OTG_CRC1_DATA_C32 0x1e16 9471 #define regOTG_CRC323_OTG_CRC1_DATA_C32_BASE_IDX 2 9472 #define regOTG_CRC323_OTG_CRC2_DATA_R32 0x1e17 9473 #define regOTG_CRC323_OTG_CRC2_DATA_R32_BASE_IDX 2 9474 #define regOTG_CRC323_OTG_CRC2_DATA_G32 0x1e18 9475 #define regOTG_CRC323_OTG_CRC2_DATA_G32_BASE_IDX 2 9476 #define regOTG_CRC323_OTG_CRC2_DATA_B32 0x1e19 9477 #define regOTG_CRC323_OTG_CRC2_DATA_B32_BASE_IDX 2 9478 #define regOTG_CRC323_OTG_CRC2_DATA_C32 0x1e1a 9479 #define regOTG_CRC323_OTG_CRC2_DATA_C32_BASE_IDX 2 9480 #define regOTG_CRC323_OTG_CRC3_DATA_R32 0x1e1b 9481 #define regOTG_CRC323_OTG_CRC3_DATA_R32_BASE_IDX 2 9482 #define regOTG_CRC323_OTG_CRC3_DATA_G32 0x1e1c 9483 #define regOTG_CRC323_OTG_CRC3_DATA_G32_BASE_IDX 2 9484 #define regOTG_CRC323_OTG_CRC3_DATA_B32 0x1e1d 9485 #define regOTG_CRC323_OTG_CRC3_DATA_B32_BASE_IDX 2 9486 #define regOTG_CRC323_OTG_CRC3_DATA_C32 0x1e1e 9487 #define regOTG_CRC323_OTG_CRC3_DATA_C32_BASE_IDX 2 9488 9489 9490 // addressBlock: dce_dc_optc_optc_misc_dispdec 9491 // base address: 0x0 9492 #define regGSL_SOURCE_SELECT 0x1e2b 9493 #define regGSL_SOURCE_SELECT_BASE_IDX 2 9494 #define regOPTC_DLPC_CONTROL 0x1e2c 9495 #define regOPTC_DLPC_CONTROL_BASE_IDX 2 9496 #define regOPTC_CLOCK_CONTROL 0x1e2d 9497 #define regOPTC_CLOCK_CONTROL_BASE_IDX 2 9498 #define regODM_MEM_PWR_CTRL 0x1e2e 9499 #define regODM_MEM_PWR_CTRL_BASE_IDX 2 9500 #define regODM_MEM_PWR_CTRL3 0x1e30 9501 #define regODM_MEM_PWR_CTRL3_BASE_IDX 2 9502 #define regODM_MEM_PWR_STATUS 0x1e31 9503 #define regODM_MEM_PWR_STATUS_BASE_IDX 2 9504 #define regOPTC_MISC_SPARE_REGISTER 0x1e32 9505 #define regOPTC_MISC_SPARE_REGISTER_BASE_IDX 2 9506 9507 9508 // addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec 9509 // base address: 0x79a8 9510 #define regDC_PERFMON17_PERFCOUNTER_CNTL 0x1e6a 9511 #define regDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX 2 9512 #define regDC_PERFMON17_PERFCOUNTER_CNTL2 0x1e6b 9513 #define regDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX 2 9514 #define regDC_PERFMON17_PERFCOUNTER_STATE 0x1e6c 9515 #define regDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX 2 9516 #define regDC_PERFMON17_PERFMON_CNTL 0x1e6d 9517 #define regDC_PERFMON17_PERFMON_CNTL_BASE_IDX 2 9518 #define regDC_PERFMON17_PERFMON_CNTL2 0x1e6e 9519 #define regDC_PERFMON17_PERFMON_CNTL2_BASE_IDX 2 9520 #define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC 0x1e6f 9521 #define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 9522 #define regDC_PERFMON17_PERFMON_CVALUE_LOW 0x1e70 9523 #define regDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX 2 9524 #define regDC_PERFMON17_PERFMON_HI 0x1e71 9525 #define regDC_PERFMON17_PERFMON_HI_BASE_IDX 2 9526 #define regDC_PERFMON17_PERFMON_LOW 0x1e72 9527 #define regDC_PERFMON17_PERFMON_LOW_BASE_IDX 2 9528 9529 9530 // addressBlock: dce_dc_dio_hpd0_dispdec 9531 // base address: 0x0 9532 #define regHPD0_DC_HPD_INT_STATUS 0x1f14 9533 #define regHPD0_DC_HPD_INT_STATUS_BASE_IDX 2 9534 #define regHPD0_DC_HPD_INT_CONTROL 0x1f15 9535 #define regHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2 9536 #define regHPD0_DC_HPD_CONTROL 0x1f16 9537 #define regHPD0_DC_HPD_CONTROL_BASE_IDX 2 9538 #define regHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1f17 9539 #define regHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 9540 #define regHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1f18 9541 #define regHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 9542 9543 9544 // addressBlock: dce_dc_dio_hpd1_dispdec 9545 // base address: 0x20 9546 #define regHPD1_DC_HPD_INT_STATUS 0x1f1c 9547 #define regHPD1_DC_HPD_INT_STATUS_BASE_IDX 2 9548 #define regHPD1_DC_HPD_INT_CONTROL 0x1f1d 9549 #define regHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2 9550 #define regHPD1_DC_HPD_CONTROL 0x1f1e 9551 #define regHPD1_DC_HPD_CONTROL_BASE_IDX 2 9552 #define regHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1f1f 9553 #define regHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 9554 #define regHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1f20 9555 #define regHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 9556 9557 9558 // addressBlock: dce_dc_dio_hpd2_dispdec 9559 // base address: 0x40 9560 #define regHPD2_DC_HPD_INT_STATUS 0x1f24 9561 #define regHPD2_DC_HPD_INT_STATUS_BASE_IDX 2 9562 #define regHPD2_DC_HPD_INT_CONTROL 0x1f25 9563 #define regHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2 9564 #define regHPD2_DC_HPD_CONTROL 0x1f26 9565 #define regHPD2_DC_HPD_CONTROL_BASE_IDX 2 9566 #define regHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1f27 9567 #define regHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 9568 #define regHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1f28 9569 #define regHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 9570 9571 9572 // addressBlock: dce_dc_dio_hpd3_dispdec 9573 // base address: 0x60 9574 #define regHPD3_DC_HPD_INT_STATUS 0x1f2c 9575 #define regHPD3_DC_HPD_INT_STATUS_BASE_IDX 2 9576 #define regHPD3_DC_HPD_INT_CONTROL 0x1f2d 9577 #define regHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2 9578 #define regHPD3_DC_HPD_CONTROL 0x1f2e 9579 #define regHPD3_DC_HPD_CONTROL_BASE_IDX 2 9580 #define regHPD3_DC_HPD_FAST_TRAIN_CNTL 0x1f2f 9581 #define regHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 9582 #define regHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x1f30 9583 #define regHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 9584 9585 9586 // addressBlock: dce_dc_dio_hpd4_dispdec 9587 // base address: 0x80 9588 #define regHPD4_DC_HPD_INT_STATUS 0x1f34 9589 #define regHPD4_DC_HPD_INT_STATUS_BASE_IDX 2 9590 #define regHPD4_DC_HPD_INT_CONTROL 0x1f35 9591 #define regHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2 9592 #define regHPD4_DC_HPD_CONTROL 0x1f36 9593 #define regHPD4_DC_HPD_CONTROL_BASE_IDX 2 9594 #define regHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1f37 9595 #define regHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 9596 #define regHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1f38 9597 #define regHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 9598 9599 9600 // addressBlock: dce_dc_dio_dp0_dispdec 9601 // base address: 0x0 9602 #define regDP0_DP_LINK_CNTL 0x211e 9603 #define regDP0_DP_LINK_CNTL_BASE_IDX 2 9604 #define regDP0_DP_PIXEL_FORMAT 0x211f 9605 #define regDP0_DP_PIXEL_FORMAT_BASE_IDX 2 9606 #define regDP0_DP_MSA_COLORIMETRY 0x2120 9607 #define regDP0_DP_MSA_COLORIMETRY_BASE_IDX 2 9608 #define regDP0_DP_CONFIG 0x2121 9609 #define regDP0_DP_CONFIG_BASE_IDX 2 9610 #define regDP0_DP_VID_STREAM_CNTL 0x2122 9611 #define regDP0_DP_VID_STREAM_CNTL_BASE_IDX 2 9612 #define regDP0_DP_STEER_FIFO 0x2123 9613 #define regDP0_DP_STEER_FIFO_BASE_IDX 2 9614 #define regDP0_DP_MSA_MISC 0x2124 9615 #define regDP0_DP_MSA_MISC_BASE_IDX 2 9616 #define regDP0_DP_DPHY_INTERNAL_CTRL 0x2125 9617 #define regDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 9618 #define regDP0_DP_VID_TIMING 0x2126 9619 #define regDP0_DP_VID_TIMING_BASE_IDX 2 9620 #define regDP0_DP_VID_N 0x2127 9621 #define regDP0_DP_VID_N_BASE_IDX 2 9622 #define regDP0_DP_VID_M 0x2128 9623 #define regDP0_DP_VID_M_BASE_IDX 2 9624 #define regDP0_DP_LINK_FRAMING_CNTL 0x2129 9625 #define regDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2 9626 #define regDP0_DP_HBR2_EYE_PATTERN 0x212a 9627 #define regDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2 9628 #define regDP0_DP_VID_MSA_VBID 0x212b 9629 #define regDP0_DP_VID_MSA_VBID_BASE_IDX 2 9630 #define regDP0_DP_VID_INTERRUPT_CNTL 0x212c 9631 #define regDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 9632 #define regDP0_DP_DPHY_CNTL 0x212d 9633 #define regDP0_DP_DPHY_CNTL_BASE_IDX 2 9634 #define regDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x212e 9635 #define regDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 9636 #define regDP0_DP_DPHY_SYM0 0x212f 9637 #define regDP0_DP_DPHY_SYM0_BASE_IDX 2 9638 #define regDP0_DP_DPHY_SYM1 0x2130 9639 #define regDP0_DP_DPHY_SYM1_BASE_IDX 2 9640 #define regDP0_DP_DPHY_SYM2 0x2131 9641 #define regDP0_DP_DPHY_SYM2_BASE_IDX 2 9642 #define regDP0_DP_DPHY_8B10B_CNTL 0x2132 9643 #define regDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2 9644 #define regDP0_DP_DPHY_PRBS_CNTL 0x2133 9645 #define regDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2 9646 #define regDP0_DP_DPHY_SCRAM_CNTL 0x2134 9647 #define regDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 9648 #define regDP0_DP_DPHY_CRC_CONTROL0 0x2135 9649 #define regDP0_DP_DPHY_CRC_CONTROL0_BASE_IDX 2 9650 #define regDP0_DP_DPHY_CRC_CONTROL1 0x2136 9651 #define regDP0_DP_DPHY_CRC_CONTROL1_BASE_IDX 2 9652 #define regDP0_DP_DPHY_CRC_RESULT0 0x2137 9653 #define regDP0_DP_DPHY_CRC_RESULT0_BASE_IDX 2 9654 #define regDP0_DP_DPHY_CRC_RESULT1 0x2138 9655 #define regDP0_DP_DPHY_CRC_RESULT1_BASE_IDX 2 9656 #define regDP0_DP_DPHY_CRC_STATUS 0x2139 9657 #define regDP0_DP_DPHY_CRC_STATUS_BASE_IDX 2 9658 #define regDP0_DP_DPHY_FAST_TRAINING 0x213a 9659 #define regDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2 9660 #define regDP0_DP_DPHY_FAST_TRAINING_STATUS 0x213b 9661 #define regDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 9662 #define regDP0_DP_DPHY_CRC_RESULT2 0x213c 9663 #define regDP0_DP_DPHY_CRC_RESULT2_BASE_IDX 2 9664 #define regDP0_DP_DPHY_CRC_RESULT3 0x213d 9665 #define regDP0_DP_DPHY_CRC_RESULT3_BASE_IDX 2 9666 #define regDP0_DP_SEC_CNTL 0x2141 9667 #define regDP0_DP_SEC_CNTL_BASE_IDX 2 9668 #define regDP0_DP_SEC_CNTL1 0x2142 9669 #define regDP0_DP_SEC_CNTL1_BASE_IDX 2 9670 #define regDP0_DP_SEC_FRAMING1 0x2143 9671 #define regDP0_DP_SEC_FRAMING1_BASE_IDX 2 9672 #define regDP0_DP_SEC_FRAMING2 0x2144 9673 #define regDP0_DP_SEC_FRAMING2_BASE_IDX 2 9674 #define regDP0_DP_SEC_FRAMING3 0x2145 9675 #define regDP0_DP_SEC_FRAMING3_BASE_IDX 2 9676 #define regDP0_DP_SEC_FRAMING4 0x2146 9677 #define regDP0_DP_SEC_FRAMING4_BASE_IDX 2 9678 #define regDP0_DP_SEC_AUD_N 0x2147 9679 #define regDP0_DP_SEC_AUD_N_BASE_IDX 2 9680 #define regDP0_DP_SEC_AUD_N_READBACK 0x2148 9681 #define regDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2 9682 #define regDP0_DP_SEC_AUD_M 0x2149 9683 #define regDP0_DP_SEC_AUD_M_BASE_IDX 2 9684 #define regDP0_DP_SEC_AUD_M_READBACK 0x214a 9685 #define regDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2 9686 #define regDP0_DP_SEC_TIMESTAMP 0x214b 9687 #define regDP0_DP_SEC_TIMESTAMP_BASE_IDX 2 9688 #define regDP0_DP_SEC_PACKET_CNTL 0x214c 9689 #define regDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2 9690 #define regDP0_DP_MSE_RATE_CNTL 0x214d 9691 #define regDP0_DP_MSE_RATE_CNTL_BASE_IDX 2 9692 #define regDP0_DP_MSE_RATE_UPDATE 0x214f 9693 #define regDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2 9694 #define regDP0_DP_MSE_SAT0 0x2150 9695 #define regDP0_DP_MSE_SAT0_BASE_IDX 2 9696 #define regDP0_DP_MSE_SAT1 0x2151 9697 #define regDP0_DP_MSE_SAT1_BASE_IDX 2 9698 #define regDP0_DP_MSE_SAT2 0x2152 9699 #define regDP0_DP_MSE_SAT2_BASE_IDX 2 9700 #define regDP0_DP_MSE_SAT_UPDATE 0x2153 9701 #define regDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2 9702 #define regDP0_DP_MSE_LINK_TIMING 0x2154 9703 #define regDP0_DP_MSE_LINK_TIMING_BASE_IDX 2 9704 #define regDP0_DP_MSE_MISC_CNTL 0x2155 9705 #define regDP0_DP_MSE_MISC_CNTL_BASE_IDX 2 9706 #define regDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x215a 9707 #define regDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 9708 #define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x215b 9709 #define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 9710 #define regDP0_DP_MSE_SAT0_STATUS 0x215d 9711 #define regDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2 9712 #define regDP0_DP_MSE_SAT1_STATUS 0x215e 9713 #define regDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2 9714 #define regDP0_DP_MSE_SAT2_STATUS 0x215f 9715 #define regDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2 9716 #define regDP0_DP_DPIA_SPARE 0x2160 9717 #define regDP0_DP_DPIA_SPARE_BASE_IDX 2 9718 #define regDP0_DP_MSA_TIMING_PARAM1 0x2162 9719 #define regDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2 9720 #define regDP0_DP_MSA_TIMING_PARAM2 0x2163 9721 #define regDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2 9722 #define regDP0_DP_MSA_TIMING_PARAM3 0x2164 9723 #define regDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2 9724 #define regDP0_DP_MSA_TIMING_PARAM4 0x2165 9725 #define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2 9726 #define regDP0_DP_MSO_CNTL 0x2166 9727 #define regDP0_DP_MSO_CNTL_BASE_IDX 2 9728 #define regDP0_DP_MSO_CNTL1 0x2167 9729 #define regDP0_DP_MSO_CNTL1_BASE_IDX 2 9730 #define regDP0_DP_DSC_CNTL 0x2168 9731 #define regDP0_DP_DSC_CNTL_BASE_IDX 2 9732 #define regDP0_DP_SEC_CNTL2 0x2169 9733 #define regDP0_DP_SEC_CNTL2_BASE_IDX 2 9734 #define regDP0_DP_SEC_CNTL3 0x216a 9735 #define regDP0_DP_SEC_CNTL3_BASE_IDX 2 9736 #define regDP0_DP_SEC_CNTL4 0x216b 9737 #define regDP0_DP_SEC_CNTL4_BASE_IDX 2 9738 #define regDP0_DP_SEC_CNTL5 0x216c 9739 #define regDP0_DP_SEC_CNTL5_BASE_IDX 2 9740 #define regDP0_DP_SEC_CNTL6 0x216d 9741 #define regDP0_DP_SEC_CNTL6_BASE_IDX 2 9742 #define regDP0_DP_SEC_CNTL7 0x216e 9743 #define regDP0_DP_SEC_CNTL7_BASE_IDX 2 9744 #define regDP0_DP_DB_CNTL 0x216f 9745 #define regDP0_DP_DB_CNTL_BASE_IDX 2 9746 #define regDP0_DP_MSA_VBID_MISC 0x2170 9747 #define regDP0_DP_MSA_VBID_MISC_BASE_IDX 2 9748 #define regDP0_DP_SEC_METADATA_TRANSMISSION 0x2171 9749 #define regDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 9750 #define regDP0_DP_ALPM_CNTL 0x2173 9751 #define regDP0_DP_ALPM_CNTL_BASE_IDX 2 9752 #define regDP0_DP_GSP8_CNTL 0x2174 9753 #define regDP0_DP_GSP8_CNTL_BASE_IDX 2 9754 #define regDP0_DP_GSP9_CNTL 0x2175 9755 #define regDP0_DP_GSP9_CNTL_BASE_IDX 2 9756 #define regDP0_DP_GSP10_CNTL 0x2176 9757 #define regDP0_DP_GSP10_CNTL_BASE_IDX 2 9758 #define regDP0_DP_GSP11_CNTL 0x2177 9759 #define regDP0_DP_GSP11_CNTL_BASE_IDX 2 9760 #define regDP0_DP_GSP_EN_DB_STATUS 0x2178 9761 #define regDP0_DP_GSP_EN_DB_STATUS_BASE_IDX 2 9762 #define regDP0_DP_AUXLESS_ALPM_CNTL1 0x2179 9763 #define regDP0_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 9764 #define regDP0_DP_AUXLESS_ALPM_CNTL2 0x217a 9765 #define regDP0_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 9766 #define regDP0_DP_AUXLESS_ALPM_CNTL3 0x217b 9767 #define regDP0_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 9768 #define regDP0_DP_AUXLESS_ALPM_CNTL4 0x217c 9769 #define regDP0_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 9770 #define regDP0_DP_AUXLESS_ALPM_CNTL5 0x217d 9771 #define regDP0_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 9772 #define regDP0_DP_STREAM_SYMBOL_COUNT_STATUS 0x217e 9773 #define regDP0_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2 9774 #define regDP0_DP_STREAM_SYMBOL_COUNT_CONTROL 0x217f 9775 #define regDP0_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2 9776 #define regDP0_DP_LINK_SYMBOL_COUNT_STATUS0 0x2180 9777 #define regDP0_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2 9778 #define regDP0_DP_LINK_SYMBOL_COUNT_STATUS1 0x2181 9779 #define regDP0_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2 9780 #define regDP0_DP_LINK_SYMBOL_COUNT_CONTROL 0x2182 9781 #define regDP0_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2 9782 9783 9784 // addressBlock: dce_dc_dio_dig0_dispdec 9785 // base address: 0x0 9786 #define regDIG0_DIG_FE_CNTL 0x2093 9787 #define regDIG0_DIG_FE_CNTL_BASE_IDX 2 9788 #define regDIG0_DIG_FE_CLK_CNTL 0x2094 9789 #define regDIG0_DIG_FE_CLK_CNTL_BASE_IDX 2 9790 #define regDIG0_DIG_FE_EN_CNTL 0x2095 9791 #define regDIG0_DIG_FE_EN_CNTL_BASE_IDX 2 9792 #define regDIG0_DIG_OUTPUT_CRC_CNTL 0x2096 9793 #define regDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 9794 #define regDIG0_DIG_OUTPUT_CRC_RESULT 0x2097 9795 #define regDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 9796 #define regDIG0_DIG_CLOCK_PATTERN 0x2098 9797 #define regDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2 9798 #define regDIG0_DIG_TEST_PATTERN 0x2099 9799 #define regDIG0_DIG_TEST_PATTERN_BASE_IDX 2 9800 #define regDIG0_DIG_RANDOM_PATTERN_SEED 0x209a 9801 #define regDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 9802 #define regDIG0_DIG_FIFO_CTRL0 0x209b 9803 #define regDIG0_DIG_FIFO_CTRL0_BASE_IDX 2 9804 #define regDIG0_DIG_FIFO_CTRL1 0x209c 9805 #define regDIG0_DIG_FIFO_CTRL1_BASE_IDX 2 9806 #define regDIG0_HDMI_METADATA_PACKET_CONTROL 0x209d 9807 #define regDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 9808 #define regDIG0_HDMI_CONTROL 0x209e 9809 #define regDIG0_HDMI_CONTROL_BASE_IDX 2 9810 #define regDIG0_HDMI_STATUS 0x209f 9811 #define regDIG0_HDMI_STATUS_BASE_IDX 2 9812 #define regDIG0_HDMI_AUDIO_PACKET_CONTROL 0x20a0 9813 #define regDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 9814 #define regDIG0_HDMI_ACR_PACKET_CONTROL 0x20a1 9815 #define regDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 9816 #define regDIG0_HDMI_VBI_PACKET_CONTROL 0x20a2 9817 #define regDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 9818 #define regDIG0_HDMI_INFOFRAME_CONTROL0 0x20a3 9819 #define regDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 9820 #define regDIG0_HDMI_INFOFRAME_CONTROL1 0x20a4 9821 #define regDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 9822 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x20a5 9823 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 9824 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL6 0x20a6 9825 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 9826 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL5 0x20a7 9827 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 9828 #define regDIG0_HDMI_GC 0x20a8 9829 #define regDIG0_HDMI_GC_BASE_IDX 2 9830 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x20a9 9831 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 9832 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x20aa 9833 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 9834 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x20ab 9835 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 9836 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL4 0x20ac 9837 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 9838 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL7 0x20ad 9839 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 9840 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL8 0x20ae 9841 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 9842 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL9 0x20af 9843 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 9844 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL10 0x20b0 9845 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 9846 #define regDIG0_HDMI_DB_CONTROL 0x20b1 9847 #define regDIG0_HDMI_DB_CONTROL_BASE_IDX 2 9848 #define regDIG0_HDMI_ACR_32_0 0x20b2 9849 #define regDIG0_HDMI_ACR_32_0_BASE_IDX 2 9850 #define regDIG0_HDMI_ACR_32_1 0x20b3 9851 #define regDIG0_HDMI_ACR_32_1_BASE_IDX 2 9852 #define regDIG0_HDMI_ACR_44_0 0x20b4 9853 #define regDIG0_HDMI_ACR_44_0_BASE_IDX 2 9854 #define regDIG0_HDMI_ACR_44_1 0x20b5 9855 #define regDIG0_HDMI_ACR_44_1_BASE_IDX 2 9856 #define regDIG0_HDMI_ACR_48_0 0x20b6 9857 #define regDIG0_HDMI_ACR_48_0_BASE_IDX 2 9858 #define regDIG0_HDMI_ACR_48_1 0x20b7 9859 #define regDIG0_HDMI_ACR_48_1_BASE_IDX 2 9860 #define regDIG0_HDMI_ACR_STATUS_0 0x20b8 9861 #define regDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2 9862 #define regDIG0_HDMI_ACR_STATUS_1 0x20b9 9863 #define regDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2 9864 #define regDIG0_AFMT_CNTL 0x20ba 9865 #define regDIG0_AFMT_CNTL_BASE_IDX 2 9866 #define regDIG0_DIG_BE_CLK_CNTL 0x20bb 9867 #define regDIG0_DIG_BE_CLK_CNTL_BASE_IDX 2 9868 #define regDIG0_DIG_BE_CNTL 0x20bc 9869 #define regDIG0_DIG_BE_CNTL_BASE_IDX 2 9870 #define regDIG0_DIG_BE_EN_CNTL 0x20bd 9871 #define regDIG0_DIG_BE_EN_CNTL_BASE_IDX 2 9872 #define regDIG0_TMDS_CNTL 0x20e4 9873 #define regDIG0_TMDS_CNTL_BASE_IDX 2 9874 #define regDIG0_TMDS_CONTROL_CHAR 0x20e5 9875 #define regDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2 9876 #define regDIG0_TMDS_CONTROL0_FEEDBACK 0x20e6 9877 #define regDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 9878 #define regDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20e7 9879 #define regDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 9880 #define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20e8 9881 #define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 9882 #define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20e9 9883 #define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 9884 #define regDIG0_TMDS_CTL_BITS 0x20eb 9885 #define regDIG0_TMDS_CTL_BITS_BASE_IDX 2 9886 #define regDIG0_TMDS_DCBALANCER_CONTROL 0x20ec 9887 #define regDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 9888 #define regDIG0_TMDS_SYNC_DCBALANCE_CHAR 0x20ed 9889 #define regDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 9890 #define regDIG0_TMDS_CTL0_1_GEN_CNTL 0x20ee 9891 #define regDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 9892 #define regDIG0_TMDS_CTL2_3_GEN_CNTL 0x20ef 9893 #define regDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 9894 #define regDIG0_DIG_VERSION 0x20f1 9895 #define regDIG0_DIG_VERSION_BASE_IDX 2 9896 9897 9898 // addressBlock: dce_dc_dio_dp1_dispdec 9899 // base address: 0x490 9900 #define regDP1_DP_LINK_CNTL 0x2242 9901 #define regDP1_DP_LINK_CNTL_BASE_IDX 2 9902 #define regDP1_DP_PIXEL_FORMAT 0x2243 9903 #define regDP1_DP_PIXEL_FORMAT_BASE_IDX 2 9904 #define regDP1_DP_MSA_COLORIMETRY 0x2244 9905 #define regDP1_DP_MSA_COLORIMETRY_BASE_IDX 2 9906 #define regDP1_DP_CONFIG 0x2245 9907 #define regDP1_DP_CONFIG_BASE_IDX 2 9908 #define regDP1_DP_VID_STREAM_CNTL 0x2246 9909 #define regDP1_DP_VID_STREAM_CNTL_BASE_IDX 2 9910 #define regDP1_DP_STEER_FIFO 0x2247 9911 #define regDP1_DP_STEER_FIFO_BASE_IDX 2 9912 #define regDP1_DP_MSA_MISC 0x2248 9913 #define regDP1_DP_MSA_MISC_BASE_IDX 2 9914 #define regDP1_DP_DPHY_INTERNAL_CTRL 0x2249 9915 #define regDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 9916 #define regDP1_DP_VID_TIMING 0x224a 9917 #define regDP1_DP_VID_TIMING_BASE_IDX 2 9918 #define regDP1_DP_VID_N 0x224b 9919 #define regDP1_DP_VID_N_BASE_IDX 2 9920 #define regDP1_DP_VID_M 0x224c 9921 #define regDP1_DP_VID_M_BASE_IDX 2 9922 #define regDP1_DP_LINK_FRAMING_CNTL 0x224d 9923 #define regDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2 9924 #define regDP1_DP_HBR2_EYE_PATTERN 0x224e 9925 #define regDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2 9926 #define regDP1_DP_VID_MSA_VBID 0x224f 9927 #define regDP1_DP_VID_MSA_VBID_BASE_IDX 2 9928 #define regDP1_DP_VID_INTERRUPT_CNTL 0x2250 9929 #define regDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 9930 #define regDP1_DP_DPHY_CNTL 0x2251 9931 #define regDP1_DP_DPHY_CNTL_BASE_IDX 2 9932 #define regDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2252 9933 #define regDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 9934 #define regDP1_DP_DPHY_SYM0 0x2253 9935 #define regDP1_DP_DPHY_SYM0_BASE_IDX 2 9936 #define regDP1_DP_DPHY_SYM1 0x2254 9937 #define regDP1_DP_DPHY_SYM1_BASE_IDX 2 9938 #define regDP1_DP_DPHY_SYM2 0x2255 9939 #define regDP1_DP_DPHY_SYM2_BASE_IDX 2 9940 #define regDP1_DP_DPHY_8B10B_CNTL 0x2256 9941 #define regDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2 9942 #define regDP1_DP_DPHY_PRBS_CNTL 0x2257 9943 #define regDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2 9944 #define regDP1_DP_DPHY_SCRAM_CNTL 0x2258 9945 #define regDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 9946 #define regDP1_DP_DPHY_CRC_CONTROL0 0x2259 9947 #define regDP1_DP_DPHY_CRC_CONTROL0_BASE_IDX 2 9948 #define regDP1_DP_DPHY_CRC_CONTROL1 0x225a 9949 #define regDP1_DP_DPHY_CRC_CONTROL1_BASE_IDX 2 9950 #define regDP1_DP_DPHY_CRC_RESULT0 0x225b 9951 #define regDP1_DP_DPHY_CRC_RESULT0_BASE_IDX 2 9952 #define regDP1_DP_DPHY_CRC_RESULT1 0x225c 9953 #define regDP1_DP_DPHY_CRC_RESULT1_BASE_IDX 2 9954 #define regDP1_DP_DPHY_CRC_STATUS 0x225d 9955 #define regDP1_DP_DPHY_CRC_STATUS_BASE_IDX 2 9956 #define regDP1_DP_DPHY_FAST_TRAINING 0x225e 9957 #define regDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2 9958 #define regDP1_DP_DPHY_FAST_TRAINING_STATUS 0x225f 9959 #define regDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 9960 #define regDP1_DP_DPHY_CRC_RESULT2 0x2260 9961 #define regDP1_DP_DPHY_CRC_RESULT2_BASE_IDX 2 9962 #define regDP1_DP_DPHY_CRC_RESULT3 0x2261 9963 #define regDP1_DP_DPHY_CRC_RESULT3_BASE_IDX 2 9964 #define regDP1_DP_SEC_CNTL 0x2265 9965 #define regDP1_DP_SEC_CNTL_BASE_IDX 2 9966 #define regDP1_DP_SEC_CNTL1 0x2266 9967 #define regDP1_DP_SEC_CNTL1_BASE_IDX 2 9968 #define regDP1_DP_SEC_FRAMING1 0x2267 9969 #define regDP1_DP_SEC_FRAMING1_BASE_IDX 2 9970 #define regDP1_DP_SEC_FRAMING2 0x2268 9971 #define regDP1_DP_SEC_FRAMING2_BASE_IDX 2 9972 #define regDP1_DP_SEC_FRAMING3 0x2269 9973 #define regDP1_DP_SEC_FRAMING3_BASE_IDX 2 9974 #define regDP1_DP_SEC_FRAMING4 0x226a 9975 #define regDP1_DP_SEC_FRAMING4_BASE_IDX 2 9976 #define regDP1_DP_SEC_AUD_N 0x226b 9977 #define regDP1_DP_SEC_AUD_N_BASE_IDX 2 9978 #define regDP1_DP_SEC_AUD_N_READBACK 0x226c 9979 #define regDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2 9980 #define regDP1_DP_SEC_AUD_M 0x226d 9981 #define regDP1_DP_SEC_AUD_M_BASE_IDX 2 9982 #define regDP1_DP_SEC_AUD_M_READBACK 0x226e 9983 #define regDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2 9984 #define regDP1_DP_SEC_TIMESTAMP 0x226f 9985 #define regDP1_DP_SEC_TIMESTAMP_BASE_IDX 2 9986 #define regDP1_DP_SEC_PACKET_CNTL 0x2270 9987 #define regDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2 9988 #define regDP1_DP_MSE_RATE_CNTL 0x2271 9989 #define regDP1_DP_MSE_RATE_CNTL_BASE_IDX 2 9990 #define regDP1_DP_MSE_RATE_UPDATE 0x2273 9991 #define regDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2 9992 #define regDP1_DP_MSE_SAT0 0x2274 9993 #define regDP1_DP_MSE_SAT0_BASE_IDX 2 9994 #define regDP1_DP_MSE_SAT1 0x2275 9995 #define regDP1_DP_MSE_SAT1_BASE_IDX 2 9996 #define regDP1_DP_MSE_SAT2 0x2276 9997 #define regDP1_DP_MSE_SAT2_BASE_IDX 2 9998 #define regDP1_DP_MSE_SAT_UPDATE 0x2277 9999 #define regDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2 10000 #define regDP1_DP_MSE_LINK_TIMING 0x2278 10001 #define regDP1_DP_MSE_LINK_TIMING_BASE_IDX 2 10002 #define regDP1_DP_MSE_MISC_CNTL 0x2279 10003 #define regDP1_DP_MSE_MISC_CNTL_BASE_IDX 2 10004 #define regDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x227e 10005 #define regDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 10006 #define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x227f 10007 #define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 10008 #define regDP1_DP_MSE_SAT0_STATUS 0x2281 10009 #define regDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2 10010 #define regDP1_DP_MSE_SAT1_STATUS 0x2282 10011 #define regDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2 10012 #define regDP1_DP_MSE_SAT2_STATUS 0x2283 10013 #define regDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2 10014 #define regDP1_DP_DPIA_SPARE 0x2284 10015 #define regDP1_DP_DPIA_SPARE_BASE_IDX 2 10016 #define regDP1_DP_MSA_TIMING_PARAM1 0x2286 10017 #define regDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2 10018 #define regDP1_DP_MSA_TIMING_PARAM2 0x2287 10019 #define regDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2 10020 #define regDP1_DP_MSA_TIMING_PARAM3 0x2288 10021 #define regDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2 10022 #define regDP1_DP_MSA_TIMING_PARAM4 0x2289 10023 #define regDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2 10024 #define regDP1_DP_MSO_CNTL 0x228a 10025 #define regDP1_DP_MSO_CNTL_BASE_IDX 2 10026 #define regDP1_DP_MSO_CNTL1 0x228b 10027 #define regDP1_DP_MSO_CNTL1_BASE_IDX 2 10028 #define regDP1_DP_DSC_CNTL 0x228c 10029 #define regDP1_DP_DSC_CNTL_BASE_IDX 2 10030 #define regDP1_DP_SEC_CNTL2 0x228d 10031 #define regDP1_DP_SEC_CNTL2_BASE_IDX 2 10032 #define regDP1_DP_SEC_CNTL3 0x228e 10033 #define regDP1_DP_SEC_CNTL3_BASE_IDX 2 10034 #define regDP1_DP_SEC_CNTL4 0x228f 10035 #define regDP1_DP_SEC_CNTL4_BASE_IDX 2 10036 #define regDP1_DP_SEC_CNTL5 0x2290 10037 #define regDP1_DP_SEC_CNTL5_BASE_IDX 2 10038 #define regDP1_DP_SEC_CNTL6 0x2291 10039 #define regDP1_DP_SEC_CNTL6_BASE_IDX 2 10040 #define regDP1_DP_SEC_CNTL7 0x2292 10041 #define regDP1_DP_SEC_CNTL7_BASE_IDX 2 10042 #define regDP1_DP_DB_CNTL 0x2293 10043 #define regDP1_DP_DB_CNTL_BASE_IDX 2 10044 #define regDP1_DP_MSA_VBID_MISC 0x2294 10045 #define regDP1_DP_MSA_VBID_MISC_BASE_IDX 2 10046 #define regDP1_DP_SEC_METADATA_TRANSMISSION 0x2295 10047 #define regDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 10048 #define regDP1_DP_ALPM_CNTL 0x2297 10049 #define regDP1_DP_ALPM_CNTL_BASE_IDX 2 10050 #define regDP1_DP_GSP8_CNTL 0x2298 10051 #define regDP1_DP_GSP8_CNTL_BASE_IDX 2 10052 #define regDP1_DP_GSP9_CNTL 0x2299 10053 #define regDP1_DP_GSP9_CNTL_BASE_IDX 2 10054 #define regDP1_DP_GSP10_CNTL 0x229a 10055 #define regDP1_DP_GSP10_CNTL_BASE_IDX 2 10056 #define regDP1_DP_GSP11_CNTL 0x229b 10057 #define regDP1_DP_GSP11_CNTL_BASE_IDX 2 10058 #define regDP1_DP_GSP_EN_DB_STATUS 0x229c 10059 #define regDP1_DP_GSP_EN_DB_STATUS_BASE_IDX 2 10060 #define regDP1_DP_AUXLESS_ALPM_CNTL1 0x229d 10061 #define regDP1_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 10062 #define regDP1_DP_AUXLESS_ALPM_CNTL2 0x229e 10063 #define regDP1_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 10064 #define regDP1_DP_AUXLESS_ALPM_CNTL3 0x229f 10065 #define regDP1_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 10066 #define regDP1_DP_AUXLESS_ALPM_CNTL4 0x22a0 10067 #define regDP1_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 10068 #define regDP1_DP_AUXLESS_ALPM_CNTL5 0x22a1 10069 #define regDP1_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 10070 #define regDP1_DP_STREAM_SYMBOL_COUNT_STATUS 0x22a2 10071 #define regDP1_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2 10072 #define regDP1_DP_STREAM_SYMBOL_COUNT_CONTROL 0x22a3 10073 #define regDP1_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2 10074 #define regDP1_DP_LINK_SYMBOL_COUNT_STATUS0 0x22a4 10075 #define regDP1_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2 10076 #define regDP1_DP_LINK_SYMBOL_COUNT_STATUS1 0x22a5 10077 #define regDP1_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2 10078 #define regDP1_DP_LINK_SYMBOL_COUNT_CONTROL 0x22a6 10079 #define regDP1_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2 10080 10081 10082 // addressBlock: dce_dc_dio_dig1_dispdec 10083 // base address: 0x490 10084 #define regDIG1_DIG_FE_CNTL 0x21b7 10085 #define regDIG1_DIG_FE_CNTL_BASE_IDX 2 10086 #define regDIG1_DIG_FE_CLK_CNTL 0x21b8 10087 #define regDIG1_DIG_FE_CLK_CNTL_BASE_IDX 2 10088 #define regDIG1_DIG_FE_EN_CNTL 0x21b9 10089 #define regDIG1_DIG_FE_EN_CNTL_BASE_IDX 2 10090 #define regDIG1_DIG_OUTPUT_CRC_CNTL 0x21ba 10091 #define regDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 10092 #define regDIG1_DIG_OUTPUT_CRC_RESULT 0x21bb 10093 #define regDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 10094 #define regDIG1_DIG_CLOCK_PATTERN 0x21bc 10095 #define regDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2 10096 #define regDIG1_DIG_TEST_PATTERN 0x21bd 10097 #define regDIG1_DIG_TEST_PATTERN_BASE_IDX 2 10098 #define regDIG1_DIG_RANDOM_PATTERN_SEED 0x21be 10099 #define regDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 10100 #define regDIG1_DIG_FIFO_CTRL0 0x21bf 10101 #define regDIG1_DIG_FIFO_CTRL0_BASE_IDX 2 10102 #define regDIG1_DIG_FIFO_CTRL1 0x21c0 10103 #define regDIG1_DIG_FIFO_CTRL1_BASE_IDX 2 10104 #define regDIG1_HDMI_METADATA_PACKET_CONTROL 0x21c1 10105 #define regDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 10106 #define regDIG1_HDMI_CONTROL 0x21c2 10107 #define regDIG1_HDMI_CONTROL_BASE_IDX 2 10108 #define regDIG1_HDMI_STATUS 0x21c3 10109 #define regDIG1_HDMI_STATUS_BASE_IDX 2 10110 #define regDIG1_HDMI_AUDIO_PACKET_CONTROL 0x21c4 10111 #define regDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 10112 #define regDIG1_HDMI_ACR_PACKET_CONTROL 0x21c5 10113 #define regDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 10114 #define regDIG1_HDMI_VBI_PACKET_CONTROL 0x21c6 10115 #define regDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 10116 #define regDIG1_HDMI_INFOFRAME_CONTROL0 0x21c7 10117 #define regDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 10118 #define regDIG1_HDMI_INFOFRAME_CONTROL1 0x21c8 10119 #define regDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 10120 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x21c9 10121 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 10122 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL6 0x21ca 10123 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 10124 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL5 0x21cb 10125 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 10126 #define regDIG1_HDMI_GC 0x21cc 10127 #define regDIG1_HDMI_GC_BASE_IDX 2 10128 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x21cd 10129 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 10130 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x21ce 10131 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 10132 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x21cf 10133 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 10134 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL4 0x21d0 10135 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 10136 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL7 0x21d1 10137 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 10138 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL8 0x21d2 10139 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 10140 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL9 0x21d3 10141 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 10142 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL10 0x21d4 10143 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 10144 #define regDIG1_HDMI_DB_CONTROL 0x21d5 10145 #define regDIG1_HDMI_DB_CONTROL_BASE_IDX 2 10146 #define regDIG1_HDMI_ACR_32_0 0x21d6 10147 #define regDIG1_HDMI_ACR_32_0_BASE_IDX 2 10148 #define regDIG1_HDMI_ACR_32_1 0x21d7 10149 #define regDIG1_HDMI_ACR_32_1_BASE_IDX 2 10150 #define regDIG1_HDMI_ACR_44_0 0x21d8 10151 #define regDIG1_HDMI_ACR_44_0_BASE_IDX 2 10152 #define regDIG1_HDMI_ACR_44_1 0x21d9 10153 #define regDIG1_HDMI_ACR_44_1_BASE_IDX 2 10154 #define regDIG1_HDMI_ACR_48_0 0x21da 10155 #define regDIG1_HDMI_ACR_48_0_BASE_IDX 2 10156 #define regDIG1_HDMI_ACR_48_1 0x21db 10157 #define regDIG1_HDMI_ACR_48_1_BASE_IDX 2 10158 #define regDIG1_HDMI_ACR_STATUS_0 0x21dc 10159 #define regDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2 10160 #define regDIG1_HDMI_ACR_STATUS_1 0x21dd 10161 #define regDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2 10162 #define regDIG1_AFMT_CNTL 0x21de 10163 #define regDIG1_AFMT_CNTL_BASE_IDX 2 10164 #define regDIG1_DIG_BE_CLK_CNTL 0x21df 10165 #define regDIG1_DIG_BE_CLK_CNTL_BASE_IDX 2 10166 #define regDIG1_DIG_BE_CNTL 0x21e0 10167 #define regDIG1_DIG_BE_CNTL_BASE_IDX 2 10168 #define regDIG1_DIG_BE_EN_CNTL 0x21e1 10169 #define regDIG1_DIG_BE_EN_CNTL_BASE_IDX 2 10170 #define regDIG1_TMDS_CNTL 0x2208 10171 #define regDIG1_TMDS_CNTL_BASE_IDX 2 10172 #define regDIG1_TMDS_CONTROL_CHAR 0x2209 10173 #define regDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2 10174 #define regDIG1_TMDS_CONTROL0_FEEDBACK 0x220a 10175 #define regDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 10176 #define regDIG1_TMDS_STEREOSYNC_CTL_SEL 0x220b 10177 #define regDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 10178 #define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x220c 10179 #define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 10180 #define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x220d 10181 #define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 10182 #define regDIG1_TMDS_CTL_BITS 0x220f 10183 #define regDIG1_TMDS_CTL_BITS_BASE_IDX 2 10184 #define regDIG1_TMDS_DCBALANCER_CONTROL 0x2210 10185 #define regDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 10186 #define regDIG1_TMDS_SYNC_DCBALANCE_CHAR 0x2211 10187 #define regDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 10188 #define regDIG1_TMDS_CTL0_1_GEN_CNTL 0x2212 10189 #define regDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 10190 #define regDIG1_TMDS_CTL2_3_GEN_CNTL 0x2213 10191 #define regDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 10192 #define regDIG1_DIG_VERSION 0x2215 10193 #define regDIG1_DIG_VERSION_BASE_IDX 2 10194 10195 10196 // addressBlock: dce_dc_dio_dp2_dispdec 10197 // base address: 0x920 10198 #define regDP2_DP_LINK_CNTL 0x2366 10199 #define regDP2_DP_LINK_CNTL_BASE_IDX 2 10200 #define regDP2_DP_PIXEL_FORMAT 0x2367 10201 #define regDP2_DP_PIXEL_FORMAT_BASE_IDX 2 10202 #define regDP2_DP_MSA_COLORIMETRY 0x2368 10203 #define regDP2_DP_MSA_COLORIMETRY_BASE_IDX 2 10204 #define regDP2_DP_CONFIG 0x2369 10205 #define regDP2_DP_CONFIG_BASE_IDX 2 10206 #define regDP2_DP_VID_STREAM_CNTL 0x236a 10207 #define regDP2_DP_VID_STREAM_CNTL_BASE_IDX 2 10208 #define regDP2_DP_STEER_FIFO 0x236b 10209 #define regDP2_DP_STEER_FIFO_BASE_IDX 2 10210 #define regDP2_DP_MSA_MISC 0x236c 10211 #define regDP2_DP_MSA_MISC_BASE_IDX 2 10212 #define regDP2_DP_DPHY_INTERNAL_CTRL 0x236d 10213 #define regDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 10214 #define regDP2_DP_VID_TIMING 0x236e 10215 #define regDP2_DP_VID_TIMING_BASE_IDX 2 10216 #define regDP2_DP_VID_N 0x236f 10217 #define regDP2_DP_VID_N_BASE_IDX 2 10218 #define regDP2_DP_VID_M 0x2370 10219 #define regDP2_DP_VID_M_BASE_IDX 2 10220 #define regDP2_DP_LINK_FRAMING_CNTL 0x2371 10221 #define regDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2 10222 #define regDP2_DP_HBR2_EYE_PATTERN 0x2372 10223 #define regDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2 10224 #define regDP2_DP_VID_MSA_VBID 0x2373 10225 #define regDP2_DP_VID_MSA_VBID_BASE_IDX 2 10226 #define regDP2_DP_VID_INTERRUPT_CNTL 0x2374 10227 #define regDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 10228 #define regDP2_DP_DPHY_CNTL 0x2375 10229 #define regDP2_DP_DPHY_CNTL_BASE_IDX 2 10230 #define regDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x2376 10231 #define regDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 10232 #define regDP2_DP_DPHY_SYM0 0x2377 10233 #define regDP2_DP_DPHY_SYM0_BASE_IDX 2 10234 #define regDP2_DP_DPHY_SYM1 0x2378 10235 #define regDP2_DP_DPHY_SYM1_BASE_IDX 2 10236 #define regDP2_DP_DPHY_SYM2 0x2379 10237 #define regDP2_DP_DPHY_SYM2_BASE_IDX 2 10238 #define regDP2_DP_DPHY_8B10B_CNTL 0x237a 10239 #define regDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2 10240 #define regDP2_DP_DPHY_PRBS_CNTL 0x237b 10241 #define regDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2 10242 #define regDP2_DP_DPHY_SCRAM_CNTL 0x237c 10243 #define regDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 10244 #define regDP2_DP_DPHY_CRC_CONTROL0 0x237d 10245 #define regDP2_DP_DPHY_CRC_CONTROL0_BASE_IDX 2 10246 #define regDP2_DP_DPHY_CRC_CONTROL1 0x237e 10247 #define regDP2_DP_DPHY_CRC_CONTROL1_BASE_IDX 2 10248 #define regDP2_DP_DPHY_CRC_RESULT0 0x237f 10249 #define regDP2_DP_DPHY_CRC_RESULT0_BASE_IDX 2 10250 #define regDP2_DP_DPHY_CRC_RESULT1 0x2380 10251 #define regDP2_DP_DPHY_CRC_RESULT1_BASE_IDX 2 10252 #define regDP2_DP_DPHY_CRC_STATUS 0x2381 10253 #define regDP2_DP_DPHY_CRC_STATUS_BASE_IDX 2 10254 #define regDP2_DP_DPHY_FAST_TRAINING 0x2382 10255 #define regDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2 10256 #define regDP2_DP_DPHY_FAST_TRAINING_STATUS 0x2383 10257 #define regDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 10258 #define regDP2_DP_DPHY_CRC_RESULT2 0x2384 10259 #define regDP2_DP_DPHY_CRC_RESULT2_BASE_IDX 2 10260 #define regDP2_DP_DPHY_CRC_RESULT3 0x2385 10261 #define regDP2_DP_DPHY_CRC_RESULT3_BASE_IDX 2 10262 #define regDP2_DP_SEC_CNTL 0x2389 10263 #define regDP2_DP_SEC_CNTL_BASE_IDX 2 10264 #define regDP2_DP_SEC_CNTL1 0x238a 10265 #define regDP2_DP_SEC_CNTL1_BASE_IDX 2 10266 #define regDP2_DP_SEC_FRAMING1 0x238b 10267 #define regDP2_DP_SEC_FRAMING1_BASE_IDX 2 10268 #define regDP2_DP_SEC_FRAMING2 0x238c 10269 #define regDP2_DP_SEC_FRAMING2_BASE_IDX 2 10270 #define regDP2_DP_SEC_FRAMING3 0x238d 10271 #define regDP2_DP_SEC_FRAMING3_BASE_IDX 2 10272 #define regDP2_DP_SEC_FRAMING4 0x238e 10273 #define regDP2_DP_SEC_FRAMING4_BASE_IDX 2 10274 #define regDP2_DP_SEC_AUD_N 0x238f 10275 #define regDP2_DP_SEC_AUD_N_BASE_IDX 2 10276 #define regDP2_DP_SEC_AUD_N_READBACK 0x2390 10277 #define regDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2 10278 #define regDP2_DP_SEC_AUD_M 0x2391 10279 #define regDP2_DP_SEC_AUD_M_BASE_IDX 2 10280 #define regDP2_DP_SEC_AUD_M_READBACK 0x2392 10281 #define regDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2 10282 #define regDP2_DP_SEC_TIMESTAMP 0x2393 10283 #define regDP2_DP_SEC_TIMESTAMP_BASE_IDX 2 10284 #define regDP2_DP_SEC_PACKET_CNTL 0x2394 10285 #define regDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2 10286 #define regDP2_DP_MSE_RATE_CNTL 0x2395 10287 #define regDP2_DP_MSE_RATE_CNTL_BASE_IDX 2 10288 #define regDP2_DP_MSE_RATE_UPDATE 0x2397 10289 #define regDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2 10290 #define regDP2_DP_MSE_SAT0 0x2398 10291 #define regDP2_DP_MSE_SAT0_BASE_IDX 2 10292 #define regDP2_DP_MSE_SAT1 0x2399 10293 #define regDP2_DP_MSE_SAT1_BASE_IDX 2 10294 #define regDP2_DP_MSE_SAT2 0x239a 10295 #define regDP2_DP_MSE_SAT2_BASE_IDX 2 10296 #define regDP2_DP_MSE_SAT_UPDATE 0x239b 10297 #define regDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2 10298 #define regDP2_DP_MSE_LINK_TIMING 0x239c 10299 #define regDP2_DP_MSE_LINK_TIMING_BASE_IDX 2 10300 #define regDP2_DP_MSE_MISC_CNTL 0x239d 10301 #define regDP2_DP_MSE_MISC_CNTL_BASE_IDX 2 10302 #define regDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x23a2 10303 #define regDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 10304 #define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x23a3 10305 #define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 10306 #define regDP2_DP_MSE_SAT0_STATUS 0x23a5 10307 #define regDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2 10308 #define regDP2_DP_MSE_SAT1_STATUS 0x23a6 10309 #define regDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2 10310 #define regDP2_DP_MSE_SAT2_STATUS 0x23a7 10311 #define regDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2 10312 #define regDP2_DP_DPIA_SPARE 0x23a8 10313 #define regDP2_DP_DPIA_SPARE_BASE_IDX 2 10314 #define regDP2_DP_MSA_TIMING_PARAM1 0x23aa 10315 #define regDP2_DP_MSA_TIMING_PARAM1_BASE_IDX 2 10316 #define regDP2_DP_MSA_TIMING_PARAM2 0x23ab 10317 #define regDP2_DP_MSA_TIMING_PARAM2_BASE_IDX 2 10318 #define regDP2_DP_MSA_TIMING_PARAM3 0x23ac 10319 #define regDP2_DP_MSA_TIMING_PARAM3_BASE_IDX 2 10320 #define regDP2_DP_MSA_TIMING_PARAM4 0x23ad 10321 #define regDP2_DP_MSA_TIMING_PARAM4_BASE_IDX 2 10322 #define regDP2_DP_MSO_CNTL 0x23ae 10323 #define regDP2_DP_MSO_CNTL_BASE_IDX 2 10324 #define regDP2_DP_MSO_CNTL1 0x23af 10325 #define regDP2_DP_MSO_CNTL1_BASE_IDX 2 10326 #define regDP2_DP_DSC_CNTL 0x23b0 10327 #define regDP2_DP_DSC_CNTL_BASE_IDX 2 10328 #define regDP2_DP_SEC_CNTL2 0x23b1 10329 #define regDP2_DP_SEC_CNTL2_BASE_IDX 2 10330 #define regDP2_DP_SEC_CNTL3 0x23b2 10331 #define regDP2_DP_SEC_CNTL3_BASE_IDX 2 10332 #define regDP2_DP_SEC_CNTL4 0x23b3 10333 #define regDP2_DP_SEC_CNTL4_BASE_IDX 2 10334 #define regDP2_DP_SEC_CNTL5 0x23b4 10335 #define regDP2_DP_SEC_CNTL5_BASE_IDX 2 10336 #define regDP2_DP_SEC_CNTL6 0x23b5 10337 #define regDP2_DP_SEC_CNTL6_BASE_IDX 2 10338 #define regDP2_DP_SEC_CNTL7 0x23b6 10339 #define regDP2_DP_SEC_CNTL7_BASE_IDX 2 10340 #define regDP2_DP_DB_CNTL 0x23b7 10341 #define regDP2_DP_DB_CNTL_BASE_IDX 2 10342 #define regDP2_DP_MSA_VBID_MISC 0x23b8 10343 #define regDP2_DP_MSA_VBID_MISC_BASE_IDX 2 10344 #define regDP2_DP_SEC_METADATA_TRANSMISSION 0x23b9 10345 #define regDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 10346 #define regDP2_DP_ALPM_CNTL 0x23bb 10347 #define regDP2_DP_ALPM_CNTL_BASE_IDX 2 10348 #define regDP2_DP_GSP8_CNTL 0x23bc 10349 #define regDP2_DP_GSP8_CNTL_BASE_IDX 2 10350 #define regDP2_DP_GSP9_CNTL 0x23bd 10351 #define regDP2_DP_GSP9_CNTL_BASE_IDX 2 10352 #define regDP2_DP_GSP10_CNTL 0x23be 10353 #define regDP2_DP_GSP10_CNTL_BASE_IDX 2 10354 #define regDP2_DP_GSP11_CNTL 0x23bf 10355 #define regDP2_DP_GSP11_CNTL_BASE_IDX 2 10356 #define regDP2_DP_GSP_EN_DB_STATUS 0x23c0 10357 #define regDP2_DP_GSP_EN_DB_STATUS_BASE_IDX 2 10358 #define regDP2_DP_AUXLESS_ALPM_CNTL1 0x23c1 10359 #define regDP2_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 10360 #define regDP2_DP_AUXLESS_ALPM_CNTL2 0x23c2 10361 #define regDP2_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 10362 #define regDP2_DP_AUXLESS_ALPM_CNTL3 0x23c3 10363 #define regDP2_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 10364 #define regDP2_DP_AUXLESS_ALPM_CNTL4 0x23c4 10365 #define regDP2_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 10366 #define regDP2_DP_AUXLESS_ALPM_CNTL5 0x23c5 10367 #define regDP2_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 10368 #define regDP2_DP_STREAM_SYMBOL_COUNT_STATUS 0x23c6 10369 #define regDP2_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2 10370 #define regDP2_DP_STREAM_SYMBOL_COUNT_CONTROL 0x23c7 10371 #define regDP2_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2 10372 #define regDP2_DP_LINK_SYMBOL_COUNT_STATUS0 0x23c8 10373 #define regDP2_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2 10374 #define regDP2_DP_LINK_SYMBOL_COUNT_STATUS1 0x23c9 10375 #define regDP2_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2 10376 #define regDP2_DP_LINK_SYMBOL_COUNT_CONTROL 0x23ca 10377 #define regDP2_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2 10378 10379 10380 // addressBlock: dce_dc_dio_dig2_dispdec 10381 // base address: 0x920 10382 #define regDIG2_DIG_FE_CNTL 0x22db 10383 #define regDIG2_DIG_FE_CNTL_BASE_IDX 2 10384 #define regDIG2_DIG_FE_CLK_CNTL 0x22dc 10385 #define regDIG2_DIG_FE_CLK_CNTL_BASE_IDX 2 10386 #define regDIG2_DIG_FE_EN_CNTL 0x22dd 10387 #define regDIG2_DIG_FE_EN_CNTL_BASE_IDX 2 10388 #define regDIG2_DIG_OUTPUT_CRC_CNTL 0x22de 10389 #define regDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 10390 #define regDIG2_DIG_OUTPUT_CRC_RESULT 0x22df 10391 #define regDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 10392 #define regDIG2_DIG_CLOCK_PATTERN 0x22e0 10393 #define regDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2 10394 #define regDIG2_DIG_TEST_PATTERN 0x22e1 10395 #define regDIG2_DIG_TEST_PATTERN_BASE_IDX 2 10396 #define regDIG2_DIG_RANDOM_PATTERN_SEED 0x22e2 10397 #define regDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 10398 #define regDIG2_DIG_FIFO_CTRL0 0x22e3 10399 #define regDIG2_DIG_FIFO_CTRL0_BASE_IDX 2 10400 #define regDIG2_DIG_FIFO_CTRL1 0x22e4 10401 #define regDIG2_DIG_FIFO_CTRL1_BASE_IDX 2 10402 #define regDIG2_HDMI_METADATA_PACKET_CONTROL 0x22e5 10403 #define regDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 10404 #define regDIG2_HDMI_CONTROL 0x22e6 10405 #define regDIG2_HDMI_CONTROL_BASE_IDX 2 10406 #define regDIG2_HDMI_STATUS 0x22e7 10407 #define regDIG2_HDMI_STATUS_BASE_IDX 2 10408 #define regDIG2_HDMI_AUDIO_PACKET_CONTROL 0x22e8 10409 #define regDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 10410 #define regDIG2_HDMI_ACR_PACKET_CONTROL 0x22e9 10411 #define regDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 10412 #define regDIG2_HDMI_VBI_PACKET_CONTROL 0x22ea 10413 #define regDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 10414 #define regDIG2_HDMI_INFOFRAME_CONTROL0 0x22eb 10415 #define regDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 10416 #define regDIG2_HDMI_INFOFRAME_CONTROL1 0x22ec 10417 #define regDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 10418 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x22ed 10419 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 10420 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL6 0x22ee 10421 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 10422 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL5 0x22ef 10423 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 10424 #define regDIG2_HDMI_GC 0x22f0 10425 #define regDIG2_HDMI_GC_BASE_IDX 2 10426 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x22f1 10427 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 10428 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL2 0x22f2 10429 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 10430 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL3 0x22f3 10431 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 10432 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL4 0x22f4 10433 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 10434 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL7 0x22f5 10435 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 10436 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL8 0x22f6 10437 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 10438 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL9 0x22f7 10439 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 10440 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL10 0x22f8 10441 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 10442 #define regDIG2_HDMI_DB_CONTROL 0x22f9 10443 #define regDIG2_HDMI_DB_CONTROL_BASE_IDX 2 10444 #define regDIG2_HDMI_ACR_32_0 0x22fa 10445 #define regDIG2_HDMI_ACR_32_0_BASE_IDX 2 10446 #define regDIG2_HDMI_ACR_32_1 0x22fb 10447 #define regDIG2_HDMI_ACR_32_1_BASE_IDX 2 10448 #define regDIG2_HDMI_ACR_44_0 0x22fc 10449 #define regDIG2_HDMI_ACR_44_0_BASE_IDX 2 10450 #define regDIG2_HDMI_ACR_44_1 0x22fd 10451 #define regDIG2_HDMI_ACR_44_1_BASE_IDX 2 10452 #define regDIG2_HDMI_ACR_48_0 0x22fe 10453 #define regDIG2_HDMI_ACR_48_0_BASE_IDX 2 10454 #define regDIG2_HDMI_ACR_48_1 0x22ff 10455 #define regDIG2_HDMI_ACR_48_1_BASE_IDX 2 10456 #define regDIG2_HDMI_ACR_STATUS_0 0x2300 10457 #define regDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2 10458 #define regDIG2_HDMI_ACR_STATUS_1 0x2301 10459 #define regDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2 10460 #define regDIG2_AFMT_CNTL 0x2302 10461 #define regDIG2_AFMT_CNTL_BASE_IDX 2 10462 #define regDIG2_DIG_BE_CLK_CNTL 0x2303 10463 #define regDIG2_DIG_BE_CLK_CNTL_BASE_IDX 2 10464 #define regDIG2_DIG_BE_CNTL 0x2304 10465 #define regDIG2_DIG_BE_CNTL_BASE_IDX 2 10466 #define regDIG2_DIG_BE_EN_CNTL 0x2305 10467 #define regDIG2_DIG_BE_EN_CNTL_BASE_IDX 2 10468 #define regDIG2_TMDS_CNTL 0x232c 10469 #define regDIG2_TMDS_CNTL_BASE_IDX 2 10470 #define regDIG2_TMDS_CONTROL_CHAR 0x232d 10471 #define regDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2 10472 #define regDIG2_TMDS_CONTROL0_FEEDBACK 0x232e 10473 #define regDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 10474 #define regDIG2_TMDS_STEREOSYNC_CTL_SEL 0x232f 10475 #define regDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 10476 #define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x2330 10477 #define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 10478 #define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x2331 10479 #define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 10480 #define regDIG2_TMDS_CTL_BITS 0x2333 10481 #define regDIG2_TMDS_CTL_BITS_BASE_IDX 2 10482 #define regDIG2_TMDS_DCBALANCER_CONTROL 0x2334 10483 #define regDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 10484 #define regDIG2_TMDS_SYNC_DCBALANCE_CHAR 0x2335 10485 #define regDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 10486 #define regDIG2_TMDS_CTL0_1_GEN_CNTL 0x2336 10487 #define regDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 10488 #define regDIG2_TMDS_CTL2_3_GEN_CNTL 0x2337 10489 #define regDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 10490 #define regDIG2_DIG_VERSION 0x2339 10491 #define regDIG2_DIG_VERSION_BASE_IDX 2 10492 10493 10494 // addressBlock: dce_dc_dio_dp3_dispdec 10495 // base address: 0xdb0 10496 #define regDP3_DP_LINK_CNTL 0x248a 10497 #define regDP3_DP_LINK_CNTL_BASE_IDX 2 10498 #define regDP3_DP_PIXEL_FORMAT 0x248b 10499 #define regDP3_DP_PIXEL_FORMAT_BASE_IDX 2 10500 #define regDP3_DP_MSA_COLORIMETRY 0x248c 10501 #define regDP3_DP_MSA_COLORIMETRY_BASE_IDX 2 10502 #define regDP3_DP_CONFIG 0x248d 10503 #define regDP3_DP_CONFIG_BASE_IDX 2 10504 #define regDP3_DP_VID_STREAM_CNTL 0x248e 10505 #define regDP3_DP_VID_STREAM_CNTL_BASE_IDX 2 10506 #define regDP3_DP_STEER_FIFO 0x248f 10507 #define regDP3_DP_STEER_FIFO_BASE_IDX 2 10508 #define regDP3_DP_MSA_MISC 0x2490 10509 #define regDP3_DP_MSA_MISC_BASE_IDX 2 10510 #define regDP3_DP_DPHY_INTERNAL_CTRL 0x2491 10511 #define regDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 10512 #define regDP3_DP_VID_TIMING 0x2492 10513 #define regDP3_DP_VID_TIMING_BASE_IDX 2 10514 #define regDP3_DP_VID_N 0x2493 10515 #define regDP3_DP_VID_N_BASE_IDX 2 10516 #define regDP3_DP_VID_M 0x2494 10517 #define regDP3_DP_VID_M_BASE_IDX 2 10518 #define regDP3_DP_LINK_FRAMING_CNTL 0x2495 10519 #define regDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2 10520 #define regDP3_DP_HBR2_EYE_PATTERN 0x2496 10521 #define regDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2 10522 #define regDP3_DP_VID_MSA_VBID 0x2497 10523 #define regDP3_DP_VID_MSA_VBID_BASE_IDX 2 10524 #define regDP3_DP_VID_INTERRUPT_CNTL 0x2498 10525 #define regDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 10526 #define regDP3_DP_DPHY_CNTL 0x2499 10527 #define regDP3_DP_DPHY_CNTL_BASE_IDX 2 10528 #define regDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x249a 10529 #define regDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 10530 #define regDP3_DP_DPHY_SYM0 0x249b 10531 #define regDP3_DP_DPHY_SYM0_BASE_IDX 2 10532 #define regDP3_DP_DPHY_SYM1 0x249c 10533 #define regDP3_DP_DPHY_SYM1_BASE_IDX 2 10534 #define regDP3_DP_DPHY_SYM2 0x249d 10535 #define regDP3_DP_DPHY_SYM2_BASE_IDX 2 10536 #define regDP3_DP_DPHY_8B10B_CNTL 0x249e 10537 #define regDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2 10538 #define regDP3_DP_DPHY_PRBS_CNTL 0x249f 10539 #define regDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2 10540 #define regDP3_DP_DPHY_SCRAM_CNTL 0x24a0 10541 #define regDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 10542 #define regDP3_DP_DPHY_CRC_CONTROL0 0x24a1 10543 #define regDP3_DP_DPHY_CRC_CONTROL0_BASE_IDX 2 10544 #define regDP3_DP_DPHY_CRC_CONTROL1 0x24a2 10545 #define regDP3_DP_DPHY_CRC_CONTROL1_BASE_IDX 2 10546 #define regDP3_DP_DPHY_CRC_RESULT0 0x24a3 10547 #define regDP3_DP_DPHY_CRC_RESULT0_BASE_IDX 2 10548 #define regDP3_DP_DPHY_CRC_RESULT1 0x24a4 10549 #define regDP3_DP_DPHY_CRC_RESULT1_BASE_IDX 2 10550 #define regDP3_DP_DPHY_CRC_STATUS 0x24a5 10551 #define regDP3_DP_DPHY_CRC_STATUS_BASE_IDX 2 10552 #define regDP3_DP_DPHY_FAST_TRAINING 0x24a6 10553 #define regDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2 10554 #define regDP3_DP_DPHY_FAST_TRAINING_STATUS 0x24a7 10555 #define regDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 10556 #define regDP3_DP_DPHY_CRC_RESULT2 0x24a8 10557 #define regDP3_DP_DPHY_CRC_RESULT2_BASE_IDX 2 10558 #define regDP3_DP_DPHY_CRC_RESULT3 0x24a9 10559 #define regDP3_DP_DPHY_CRC_RESULT3_BASE_IDX 2 10560 #define regDP3_DP_SEC_CNTL 0x24ad 10561 #define regDP3_DP_SEC_CNTL_BASE_IDX 2 10562 #define regDP3_DP_SEC_CNTL1 0x24ae 10563 #define regDP3_DP_SEC_CNTL1_BASE_IDX 2 10564 #define regDP3_DP_SEC_FRAMING1 0x24af 10565 #define regDP3_DP_SEC_FRAMING1_BASE_IDX 2 10566 #define regDP3_DP_SEC_FRAMING2 0x24b0 10567 #define regDP3_DP_SEC_FRAMING2_BASE_IDX 2 10568 #define regDP3_DP_SEC_FRAMING3 0x24b1 10569 #define regDP3_DP_SEC_FRAMING3_BASE_IDX 2 10570 #define regDP3_DP_SEC_FRAMING4 0x24b2 10571 #define regDP3_DP_SEC_FRAMING4_BASE_IDX 2 10572 #define regDP3_DP_SEC_AUD_N 0x24b3 10573 #define regDP3_DP_SEC_AUD_N_BASE_IDX 2 10574 #define regDP3_DP_SEC_AUD_N_READBACK 0x24b4 10575 #define regDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2 10576 #define regDP3_DP_SEC_AUD_M 0x24b5 10577 #define regDP3_DP_SEC_AUD_M_BASE_IDX 2 10578 #define regDP3_DP_SEC_AUD_M_READBACK 0x24b6 10579 #define regDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2 10580 #define regDP3_DP_SEC_TIMESTAMP 0x24b7 10581 #define regDP3_DP_SEC_TIMESTAMP_BASE_IDX 2 10582 #define regDP3_DP_SEC_PACKET_CNTL 0x24b8 10583 #define regDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2 10584 #define regDP3_DP_MSE_RATE_CNTL 0x24b9 10585 #define regDP3_DP_MSE_RATE_CNTL_BASE_IDX 2 10586 #define regDP3_DP_MSE_RATE_UPDATE 0x24bb 10587 #define regDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2 10588 #define regDP3_DP_MSE_SAT0 0x24bc 10589 #define regDP3_DP_MSE_SAT0_BASE_IDX 2 10590 #define regDP3_DP_MSE_SAT1 0x24bd 10591 #define regDP3_DP_MSE_SAT1_BASE_IDX 2 10592 #define regDP3_DP_MSE_SAT2 0x24be 10593 #define regDP3_DP_MSE_SAT2_BASE_IDX 2 10594 #define regDP3_DP_MSE_SAT_UPDATE 0x24bf 10595 #define regDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2 10596 #define regDP3_DP_MSE_LINK_TIMING 0x24c0 10597 #define regDP3_DP_MSE_LINK_TIMING_BASE_IDX 2 10598 #define regDP3_DP_MSE_MISC_CNTL 0x24c1 10599 #define regDP3_DP_MSE_MISC_CNTL_BASE_IDX 2 10600 #define regDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x24c6 10601 #define regDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 10602 #define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x24c7 10603 #define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 10604 #define regDP3_DP_MSE_SAT0_STATUS 0x24c9 10605 #define regDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2 10606 #define regDP3_DP_MSE_SAT1_STATUS 0x24ca 10607 #define regDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2 10608 #define regDP3_DP_MSE_SAT2_STATUS 0x24cb 10609 #define regDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2 10610 #define regDP3_DP_DPIA_SPARE 0x24cc 10611 #define regDP3_DP_DPIA_SPARE_BASE_IDX 2 10612 #define regDP3_DP_MSA_TIMING_PARAM1 0x24ce 10613 #define regDP3_DP_MSA_TIMING_PARAM1_BASE_IDX 2 10614 #define regDP3_DP_MSA_TIMING_PARAM2 0x24cf 10615 #define regDP3_DP_MSA_TIMING_PARAM2_BASE_IDX 2 10616 #define regDP3_DP_MSA_TIMING_PARAM3 0x24d0 10617 #define regDP3_DP_MSA_TIMING_PARAM3_BASE_IDX 2 10618 #define regDP3_DP_MSA_TIMING_PARAM4 0x24d1 10619 #define regDP3_DP_MSA_TIMING_PARAM4_BASE_IDX 2 10620 #define regDP3_DP_MSO_CNTL 0x24d2 10621 #define regDP3_DP_MSO_CNTL_BASE_IDX 2 10622 #define regDP3_DP_MSO_CNTL1 0x24d3 10623 #define regDP3_DP_MSO_CNTL1_BASE_IDX 2 10624 #define regDP3_DP_DSC_CNTL 0x24d4 10625 #define regDP3_DP_DSC_CNTL_BASE_IDX 2 10626 #define regDP3_DP_SEC_CNTL2 0x24d5 10627 #define regDP3_DP_SEC_CNTL2_BASE_IDX 2 10628 #define regDP3_DP_SEC_CNTL3 0x24d6 10629 #define regDP3_DP_SEC_CNTL3_BASE_IDX 2 10630 #define regDP3_DP_SEC_CNTL4 0x24d7 10631 #define regDP3_DP_SEC_CNTL4_BASE_IDX 2 10632 #define regDP3_DP_SEC_CNTL5 0x24d8 10633 #define regDP3_DP_SEC_CNTL5_BASE_IDX 2 10634 #define regDP3_DP_SEC_CNTL6 0x24d9 10635 #define regDP3_DP_SEC_CNTL6_BASE_IDX 2 10636 #define regDP3_DP_SEC_CNTL7 0x24da 10637 #define regDP3_DP_SEC_CNTL7_BASE_IDX 2 10638 #define regDP3_DP_DB_CNTL 0x24db 10639 #define regDP3_DP_DB_CNTL_BASE_IDX 2 10640 #define regDP3_DP_MSA_VBID_MISC 0x24dc 10641 #define regDP3_DP_MSA_VBID_MISC_BASE_IDX 2 10642 #define regDP3_DP_SEC_METADATA_TRANSMISSION 0x24dd 10643 #define regDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 10644 #define regDP3_DP_ALPM_CNTL 0x24df 10645 #define regDP3_DP_ALPM_CNTL_BASE_IDX 2 10646 #define regDP3_DP_GSP8_CNTL 0x24e0 10647 #define regDP3_DP_GSP8_CNTL_BASE_IDX 2 10648 #define regDP3_DP_GSP9_CNTL 0x24e1 10649 #define regDP3_DP_GSP9_CNTL_BASE_IDX 2 10650 #define regDP3_DP_GSP10_CNTL 0x24e2 10651 #define regDP3_DP_GSP10_CNTL_BASE_IDX 2 10652 #define regDP3_DP_GSP11_CNTL 0x24e3 10653 #define regDP3_DP_GSP11_CNTL_BASE_IDX 2 10654 #define regDP3_DP_GSP_EN_DB_STATUS 0x24e4 10655 #define regDP3_DP_GSP_EN_DB_STATUS_BASE_IDX 2 10656 #define regDP3_DP_AUXLESS_ALPM_CNTL1 0x24e5 10657 #define regDP3_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 10658 #define regDP3_DP_AUXLESS_ALPM_CNTL2 0x24e6 10659 #define regDP3_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 10660 #define regDP3_DP_AUXLESS_ALPM_CNTL3 0x24e7 10661 #define regDP3_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 10662 #define regDP3_DP_AUXLESS_ALPM_CNTL4 0x24e8 10663 #define regDP3_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 10664 #define regDP3_DP_AUXLESS_ALPM_CNTL5 0x24e9 10665 #define regDP3_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 10666 #define regDP3_DP_STREAM_SYMBOL_COUNT_STATUS 0x24ea 10667 #define regDP3_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2 10668 #define regDP3_DP_STREAM_SYMBOL_COUNT_CONTROL 0x24eb 10669 #define regDP3_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2 10670 #define regDP3_DP_LINK_SYMBOL_COUNT_STATUS0 0x24ec 10671 #define regDP3_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2 10672 #define regDP3_DP_LINK_SYMBOL_COUNT_STATUS1 0x24ed 10673 #define regDP3_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2 10674 #define regDP3_DP_LINK_SYMBOL_COUNT_CONTROL 0x24ee 10675 #define regDP3_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2 10676 10677 10678 // addressBlock: dce_dc_dio_dig3_dispdec 10679 // base address: 0xdb0 10680 #define regDIG3_DIG_FE_CNTL 0x23ff 10681 #define regDIG3_DIG_FE_CNTL_BASE_IDX 2 10682 #define regDIG3_DIG_FE_CLK_CNTL 0x2400 10683 #define regDIG3_DIG_FE_CLK_CNTL_BASE_IDX 2 10684 #define regDIG3_DIG_FE_EN_CNTL 0x2401 10685 #define regDIG3_DIG_FE_EN_CNTL_BASE_IDX 2 10686 #define regDIG3_DIG_OUTPUT_CRC_CNTL 0x2402 10687 #define regDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 10688 #define regDIG3_DIG_OUTPUT_CRC_RESULT 0x2403 10689 #define regDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 10690 #define regDIG3_DIG_CLOCK_PATTERN 0x2404 10691 #define regDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2 10692 #define regDIG3_DIG_TEST_PATTERN 0x2405 10693 #define regDIG3_DIG_TEST_PATTERN_BASE_IDX 2 10694 #define regDIG3_DIG_RANDOM_PATTERN_SEED 0x2406 10695 #define regDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 10696 #define regDIG3_DIG_FIFO_CTRL0 0x2407 10697 #define regDIG3_DIG_FIFO_CTRL0_BASE_IDX 2 10698 #define regDIG3_DIG_FIFO_CTRL1 0x2408 10699 #define regDIG3_DIG_FIFO_CTRL1_BASE_IDX 2 10700 #define regDIG3_HDMI_METADATA_PACKET_CONTROL 0x2409 10701 #define regDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 10702 #define regDIG3_HDMI_CONTROL 0x240a 10703 #define regDIG3_HDMI_CONTROL_BASE_IDX 2 10704 #define regDIG3_HDMI_STATUS 0x240b 10705 #define regDIG3_HDMI_STATUS_BASE_IDX 2 10706 #define regDIG3_HDMI_AUDIO_PACKET_CONTROL 0x240c 10707 #define regDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 10708 #define regDIG3_HDMI_ACR_PACKET_CONTROL 0x240d 10709 #define regDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 10710 #define regDIG3_HDMI_VBI_PACKET_CONTROL 0x240e 10711 #define regDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 10712 #define regDIG3_HDMI_INFOFRAME_CONTROL0 0x240f 10713 #define regDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 10714 #define regDIG3_HDMI_INFOFRAME_CONTROL1 0x2410 10715 #define regDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 10716 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x2411 10717 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 10718 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL6 0x2412 10719 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 10720 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL5 0x2413 10721 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 10722 #define regDIG3_HDMI_GC 0x2414 10723 #define regDIG3_HDMI_GC_BASE_IDX 2 10724 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x2415 10725 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 10726 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL2 0x2416 10727 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 10728 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL3 0x2417 10729 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 10730 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL4 0x2418 10731 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 10732 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL7 0x2419 10733 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 10734 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL8 0x241a 10735 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 10736 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL9 0x241b 10737 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 10738 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL10 0x241c 10739 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 10740 #define regDIG3_HDMI_DB_CONTROL 0x241d 10741 #define regDIG3_HDMI_DB_CONTROL_BASE_IDX 2 10742 #define regDIG3_HDMI_ACR_32_0 0x241e 10743 #define regDIG3_HDMI_ACR_32_0_BASE_IDX 2 10744 #define regDIG3_HDMI_ACR_32_1 0x241f 10745 #define regDIG3_HDMI_ACR_32_1_BASE_IDX 2 10746 #define regDIG3_HDMI_ACR_44_0 0x2420 10747 #define regDIG3_HDMI_ACR_44_0_BASE_IDX 2 10748 #define regDIG3_HDMI_ACR_44_1 0x2421 10749 #define regDIG3_HDMI_ACR_44_1_BASE_IDX 2 10750 #define regDIG3_HDMI_ACR_48_0 0x2422 10751 #define regDIG3_HDMI_ACR_48_0_BASE_IDX 2 10752 #define regDIG3_HDMI_ACR_48_1 0x2423 10753 #define regDIG3_HDMI_ACR_48_1_BASE_IDX 2 10754 #define regDIG3_HDMI_ACR_STATUS_0 0x2424 10755 #define regDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2 10756 #define regDIG3_HDMI_ACR_STATUS_1 0x2425 10757 #define regDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2 10758 #define regDIG3_AFMT_CNTL 0x2426 10759 #define regDIG3_AFMT_CNTL_BASE_IDX 2 10760 #define regDIG3_DIG_BE_CLK_CNTL 0x2427 10761 #define regDIG3_DIG_BE_CLK_CNTL_BASE_IDX 2 10762 #define regDIG3_DIG_BE_CNTL 0x2428 10763 #define regDIG3_DIG_BE_CNTL_BASE_IDX 2 10764 #define regDIG3_DIG_BE_EN_CNTL 0x2429 10765 #define regDIG3_DIG_BE_EN_CNTL_BASE_IDX 2 10766 #define regDIG3_TMDS_CNTL 0x2450 10767 #define regDIG3_TMDS_CNTL_BASE_IDX 2 10768 #define regDIG3_TMDS_CONTROL_CHAR 0x2451 10769 #define regDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2 10770 #define regDIG3_TMDS_CONTROL0_FEEDBACK 0x2452 10771 #define regDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 10772 #define regDIG3_TMDS_STEREOSYNC_CTL_SEL 0x2453 10773 #define regDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 10774 #define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x2454 10775 #define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 10776 #define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x2455 10777 #define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 10778 #define regDIG3_TMDS_CTL_BITS 0x2457 10779 #define regDIG3_TMDS_CTL_BITS_BASE_IDX 2 10780 #define regDIG3_TMDS_DCBALANCER_CONTROL 0x2458 10781 #define regDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 10782 #define regDIG3_TMDS_SYNC_DCBALANCE_CHAR 0x2459 10783 #define regDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 10784 #define regDIG3_TMDS_CTL0_1_GEN_CNTL 0x245a 10785 #define regDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 10786 #define regDIG3_TMDS_CTL2_3_GEN_CNTL 0x245b 10787 #define regDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 10788 #define regDIG3_DIG_VERSION 0x245d 10789 #define regDIG3_DIG_VERSION_BASE_IDX 2 10790 10791 10792 // addressBlock: dce_dc_dio_dp4_dispdec 10793 // base address: 0x1240 10794 #define regDP4_DP_LINK_CNTL 0x25ae 10795 #define regDP4_DP_LINK_CNTL_BASE_IDX 2 10796 #define regDP4_DP_PIXEL_FORMAT 0x25af 10797 #define regDP4_DP_PIXEL_FORMAT_BASE_IDX 2 10798 #define regDP4_DP_MSA_COLORIMETRY 0x25b0 10799 #define regDP4_DP_MSA_COLORIMETRY_BASE_IDX 2 10800 #define regDP4_DP_CONFIG 0x25b1 10801 #define regDP4_DP_CONFIG_BASE_IDX 2 10802 #define regDP4_DP_VID_STREAM_CNTL 0x25b2 10803 #define regDP4_DP_VID_STREAM_CNTL_BASE_IDX 2 10804 #define regDP4_DP_STEER_FIFO 0x25b3 10805 #define regDP4_DP_STEER_FIFO_BASE_IDX 2 10806 #define regDP4_DP_MSA_MISC 0x25b4 10807 #define regDP4_DP_MSA_MISC_BASE_IDX 2 10808 #define regDP4_DP_DPHY_INTERNAL_CTRL 0x25b5 10809 #define regDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 10810 #define regDP4_DP_VID_TIMING 0x25b6 10811 #define regDP4_DP_VID_TIMING_BASE_IDX 2 10812 #define regDP4_DP_VID_N 0x25b7 10813 #define regDP4_DP_VID_N_BASE_IDX 2 10814 #define regDP4_DP_VID_M 0x25b8 10815 #define regDP4_DP_VID_M_BASE_IDX 2 10816 #define regDP4_DP_LINK_FRAMING_CNTL 0x25b9 10817 #define regDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2 10818 #define regDP4_DP_HBR2_EYE_PATTERN 0x25ba 10819 #define regDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2 10820 #define regDP4_DP_VID_MSA_VBID 0x25bb 10821 #define regDP4_DP_VID_MSA_VBID_BASE_IDX 2 10822 #define regDP4_DP_VID_INTERRUPT_CNTL 0x25bc 10823 #define regDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 10824 #define regDP4_DP_DPHY_CNTL 0x25bd 10825 #define regDP4_DP_DPHY_CNTL_BASE_IDX 2 10826 #define regDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x25be 10827 #define regDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 10828 #define regDP4_DP_DPHY_SYM0 0x25bf 10829 #define regDP4_DP_DPHY_SYM0_BASE_IDX 2 10830 #define regDP4_DP_DPHY_SYM1 0x25c0 10831 #define regDP4_DP_DPHY_SYM1_BASE_IDX 2 10832 #define regDP4_DP_DPHY_SYM2 0x25c1 10833 #define regDP4_DP_DPHY_SYM2_BASE_IDX 2 10834 #define regDP4_DP_DPHY_8B10B_CNTL 0x25c2 10835 #define regDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2 10836 #define regDP4_DP_DPHY_PRBS_CNTL 0x25c3 10837 #define regDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2 10838 #define regDP4_DP_DPHY_SCRAM_CNTL 0x25c4 10839 #define regDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 10840 #define regDP4_DP_DPHY_CRC_CONTROL0 0x25c5 10841 #define regDP4_DP_DPHY_CRC_CONTROL0_BASE_IDX 2 10842 #define regDP4_DP_DPHY_CRC_CONTROL1 0x25c6 10843 #define regDP4_DP_DPHY_CRC_CONTROL1_BASE_IDX 2 10844 #define regDP4_DP_DPHY_CRC_RESULT0 0x25c7 10845 #define regDP4_DP_DPHY_CRC_RESULT0_BASE_IDX 2 10846 #define regDP4_DP_DPHY_CRC_RESULT1 0x25c8 10847 #define regDP4_DP_DPHY_CRC_RESULT1_BASE_IDX 2 10848 #define regDP4_DP_DPHY_CRC_STATUS 0x25c9 10849 #define regDP4_DP_DPHY_CRC_STATUS_BASE_IDX 2 10850 #define regDP4_DP_DPHY_FAST_TRAINING 0x25ca 10851 #define regDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2 10852 #define regDP4_DP_DPHY_FAST_TRAINING_STATUS 0x25cb 10853 #define regDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 10854 #define regDP4_DP_DPHY_CRC_RESULT2 0x25cc 10855 #define regDP4_DP_DPHY_CRC_RESULT2_BASE_IDX 2 10856 #define regDP4_DP_DPHY_CRC_RESULT3 0x25cd 10857 #define regDP4_DP_DPHY_CRC_RESULT3_BASE_IDX 2 10858 #define regDP4_DP_SEC_CNTL 0x25d1 10859 #define regDP4_DP_SEC_CNTL_BASE_IDX 2 10860 #define regDP4_DP_SEC_CNTL1 0x25d2 10861 #define regDP4_DP_SEC_CNTL1_BASE_IDX 2 10862 #define regDP4_DP_SEC_FRAMING1 0x25d3 10863 #define regDP4_DP_SEC_FRAMING1_BASE_IDX 2 10864 #define regDP4_DP_SEC_FRAMING2 0x25d4 10865 #define regDP4_DP_SEC_FRAMING2_BASE_IDX 2 10866 #define regDP4_DP_SEC_FRAMING3 0x25d5 10867 #define regDP4_DP_SEC_FRAMING3_BASE_IDX 2 10868 #define regDP4_DP_SEC_FRAMING4 0x25d6 10869 #define regDP4_DP_SEC_FRAMING4_BASE_IDX 2 10870 #define regDP4_DP_SEC_AUD_N 0x25d7 10871 #define regDP4_DP_SEC_AUD_N_BASE_IDX 2 10872 #define regDP4_DP_SEC_AUD_N_READBACK 0x25d8 10873 #define regDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2 10874 #define regDP4_DP_SEC_AUD_M 0x25d9 10875 #define regDP4_DP_SEC_AUD_M_BASE_IDX 2 10876 #define regDP4_DP_SEC_AUD_M_READBACK 0x25da 10877 #define regDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2 10878 #define regDP4_DP_SEC_TIMESTAMP 0x25db 10879 #define regDP4_DP_SEC_TIMESTAMP_BASE_IDX 2 10880 #define regDP4_DP_SEC_PACKET_CNTL 0x25dc 10881 #define regDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2 10882 #define regDP4_DP_MSE_RATE_CNTL 0x25dd 10883 #define regDP4_DP_MSE_RATE_CNTL_BASE_IDX 2 10884 #define regDP4_DP_MSE_RATE_UPDATE 0x25df 10885 #define regDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2 10886 #define regDP4_DP_MSE_SAT0 0x25e0 10887 #define regDP4_DP_MSE_SAT0_BASE_IDX 2 10888 #define regDP4_DP_MSE_SAT1 0x25e1 10889 #define regDP4_DP_MSE_SAT1_BASE_IDX 2 10890 #define regDP4_DP_MSE_SAT2 0x25e2 10891 #define regDP4_DP_MSE_SAT2_BASE_IDX 2 10892 #define regDP4_DP_MSE_SAT_UPDATE 0x25e3 10893 #define regDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2 10894 #define regDP4_DP_MSE_LINK_TIMING 0x25e4 10895 #define regDP4_DP_MSE_LINK_TIMING_BASE_IDX 2 10896 #define regDP4_DP_MSE_MISC_CNTL 0x25e5 10897 #define regDP4_DP_MSE_MISC_CNTL_BASE_IDX 2 10898 #define regDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x25ea 10899 #define regDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 10900 #define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x25eb 10901 #define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 10902 #define regDP4_DP_MSE_SAT0_STATUS 0x25ed 10903 #define regDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2 10904 #define regDP4_DP_MSE_SAT1_STATUS 0x25ee 10905 #define regDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2 10906 #define regDP4_DP_MSE_SAT2_STATUS 0x25ef 10907 #define regDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2 10908 #define regDP4_DP_DPIA_SPARE 0x25f0 10909 #define regDP4_DP_DPIA_SPARE_BASE_IDX 2 10910 #define regDP4_DP_MSA_TIMING_PARAM1 0x25f2 10911 #define regDP4_DP_MSA_TIMING_PARAM1_BASE_IDX 2 10912 #define regDP4_DP_MSA_TIMING_PARAM2 0x25f3 10913 #define regDP4_DP_MSA_TIMING_PARAM2_BASE_IDX 2 10914 #define regDP4_DP_MSA_TIMING_PARAM3 0x25f4 10915 #define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 2 10916 #define regDP4_DP_MSA_TIMING_PARAM4 0x25f5 10917 #define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX 2 10918 #define regDP4_DP_MSO_CNTL 0x25f6 10919 #define regDP4_DP_MSO_CNTL_BASE_IDX 2 10920 #define regDP4_DP_MSO_CNTL1 0x25f7 10921 #define regDP4_DP_MSO_CNTL1_BASE_IDX 2 10922 #define regDP4_DP_DSC_CNTL 0x25f8 10923 #define regDP4_DP_DSC_CNTL_BASE_IDX 2 10924 #define regDP4_DP_SEC_CNTL2 0x25f9 10925 #define regDP4_DP_SEC_CNTL2_BASE_IDX 2 10926 #define regDP4_DP_SEC_CNTL3 0x25fa 10927 #define regDP4_DP_SEC_CNTL3_BASE_IDX 2 10928 #define regDP4_DP_SEC_CNTL4 0x25fb 10929 #define regDP4_DP_SEC_CNTL4_BASE_IDX 2 10930 #define regDP4_DP_SEC_CNTL5 0x25fc 10931 #define regDP4_DP_SEC_CNTL5_BASE_IDX 2 10932 #define regDP4_DP_SEC_CNTL6 0x25fd 10933 #define regDP4_DP_SEC_CNTL6_BASE_IDX 2 10934 #define regDP4_DP_SEC_CNTL7 0x25fe 10935 #define regDP4_DP_SEC_CNTL7_BASE_IDX 2 10936 #define regDP4_DP_DB_CNTL 0x25ff 10937 #define regDP4_DP_DB_CNTL_BASE_IDX 2 10938 #define regDP4_DP_MSA_VBID_MISC 0x2600 10939 #define regDP4_DP_MSA_VBID_MISC_BASE_IDX 2 10940 #define regDP4_DP_SEC_METADATA_TRANSMISSION 0x2601 10941 #define regDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 10942 #define regDP4_DP_ALPM_CNTL 0x2603 10943 #define regDP4_DP_ALPM_CNTL_BASE_IDX 2 10944 #define regDP4_DP_GSP8_CNTL 0x2604 10945 #define regDP4_DP_GSP8_CNTL_BASE_IDX 2 10946 #define regDP4_DP_GSP9_CNTL 0x2605 10947 #define regDP4_DP_GSP9_CNTL_BASE_IDX 2 10948 #define regDP4_DP_GSP10_CNTL 0x2606 10949 #define regDP4_DP_GSP10_CNTL_BASE_IDX 2 10950 #define regDP4_DP_GSP11_CNTL 0x2607 10951 #define regDP4_DP_GSP11_CNTL_BASE_IDX 2 10952 #define regDP4_DP_GSP_EN_DB_STATUS 0x2608 10953 #define regDP4_DP_GSP_EN_DB_STATUS_BASE_IDX 2 10954 #define regDP4_DP_AUXLESS_ALPM_CNTL1 0x2609 10955 #define regDP4_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 10956 #define regDP4_DP_AUXLESS_ALPM_CNTL2 0x260a 10957 #define regDP4_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 10958 #define regDP4_DP_AUXLESS_ALPM_CNTL3 0x260b 10959 #define regDP4_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 10960 #define regDP4_DP_AUXLESS_ALPM_CNTL4 0x260c 10961 #define regDP4_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 10962 #define regDP4_DP_AUXLESS_ALPM_CNTL5 0x260d 10963 #define regDP4_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 10964 #define regDP4_DP_STREAM_SYMBOL_COUNT_STATUS 0x260e 10965 #define regDP4_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2 10966 #define regDP4_DP_STREAM_SYMBOL_COUNT_CONTROL 0x260f 10967 #define regDP4_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2 10968 #define regDP4_DP_LINK_SYMBOL_COUNT_STATUS0 0x2610 10969 #define regDP4_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2 10970 #define regDP4_DP_LINK_SYMBOL_COUNT_STATUS1 0x2611 10971 #define regDP4_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2 10972 #define regDP4_DP_LINK_SYMBOL_COUNT_CONTROL 0x2612 10973 #define regDP4_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2 10974 10975 10976 // addressBlock: dce_dc_dio_dig4_dispdec 10977 // base address: 0x1240 10978 #define regDIG4_DIG_FE_CNTL 0x2523 10979 #define regDIG4_DIG_FE_CNTL_BASE_IDX 2 10980 #define regDIG4_DIG_FE_CLK_CNTL 0x2524 10981 #define regDIG4_DIG_FE_CLK_CNTL_BASE_IDX 2 10982 #define regDIG4_DIG_FE_EN_CNTL 0x2525 10983 #define regDIG4_DIG_FE_EN_CNTL_BASE_IDX 2 10984 #define regDIG4_DIG_OUTPUT_CRC_CNTL 0x2526 10985 #define regDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 10986 #define regDIG4_DIG_OUTPUT_CRC_RESULT 0x2527 10987 #define regDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 10988 #define regDIG4_DIG_CLOCK_PATTERN 0x2528 10989 #define regDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2 10990 #define regDIG4_DIG_TEST_PATTERN 0x2529 10991 #define regDIG4_DIG_TEST_PATTERN_BASE_IDX 2 10992 #define regDIG4_DIG_RANDOM_PATTERN_SEED 0x252a 10993 #define regDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 10994 #define regDIG4_DIG_FIFO_CTRL0 0x252b 10995 #define regDIG4_DIG_FIFO_CTRL0_BASE_IDX 2 10996 #define regDIG4_DIG_FIFO_CTRL1 0x252c 10997 #define regDIG4_DIG_FIFO_CTRL1_BASE_IDX 2 10998 #define regDIG4_HDMI_METADATA_PACKET_CONTROL 0x252d 10999 #define regDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 11000 #define regDIG4_HDMI_CONTROL 0x252e 11001 #define regDIG4_HDMI_CONTROL_BASE_IDX 2 11002 #define regDIG4_HDMI_STATUS 0x252f 11003 #define regDIG4_HDMI_STATUS_BASE_IDX 2 11004 #define regDIG4_HDMI_AUDIO_PACKET_CONTROL 0x2530 11005 #define regDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 11006 #define regDIG4_HDMI_ACR_PACKET_CONTROL 0x2531 11007 #define regDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 11008 #define regDIG4_HDMI_VBI_PACKET_CONTROL 0x2532 11009 #define regDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 11010 #define regDIG4_HDMI_INFOFRAME_CONTROL0 0x2533 11011 #define regDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 11012 #define regDIG4_HDMI_INFOFRAME_CONTROL1 0x2534 11013 #define regDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 11014 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x2535 11015 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 11016 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL6 0x2536 11017 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 11018 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL5 0x2537 11019 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 11020 #define regDIG4_HDMI_GC 0x2538 11021 #define regDIG4_HDMI_GC_BASE_IDX 2 11022 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x2539 11023 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 11024 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL2 0x253a 11025 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 11026 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL3 0x253b 11027 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 11028 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL4 0x253c 11029 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 11030 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL7 0x253d 11031 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 11032 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL8 0x253e 11033 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 11034 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL9 0x253f 11035 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 11036 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL10 0x2540 11037 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 11038 #define regDIG4_HDMI_DB_CONTROL 0x2541 11039 #define regDIG4_HDMI_DB_CONTROL_BASE_IDX 2 11040 #define regDIG4_HDMI_ACR_32_0 0x2542 11041 #define regDIG4_HDMI_ACR_32_0_BASE_IDX 2 11042 #define regDIG4_HDMI_ACR_32_1 0x2543 11043 #define regDIG4_HDMI_ACR_32_1_BASE_IDX 2 11044 #define regDIG4_HDMI_ACR_44_0 0x2544 11045 #define regDIG4_HDMI_ACR_44_0_BASE_IDX 2 11046 #define regDIG4_HDMI_ACR_44_1 0x2545 11047 #define regDIG4_HDMI_ACR_44_1_BASE_IDX 2 11048 #define regDIG4_HDMI_ACR_48_0 0x2546 11049 #define regDIG4_HDMI_ACR_48_0_BASE_IDX 2 11050 #define regDIG4_HDMI_ACR_48_1 0x2547 11051 #define regDIG4_HDMI_ACR_48_1_BASE_IDX 2 11052 #define regDIG4_HDMI_ACR_STATUS_0 0x2548 11053 #define regDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2 11054 #define regDIG4_HDMI_ACR_STATUS_1 0x2549 11055 #define regDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2 11056 #define regDIG4_AFMT_CNTL 0x254a 11057 #define regDIG4_AFMT_CNTL_BASE_IDX 2 11058 #define regDIG4_DIG_BE_CLK_CNTL 0x254b 11059 #define regDIG4_DIG_BE_CLK_CNTL_BASE_IDX 2 11060 #define regDIG4_DIG_BE_CNTL 0x254c 11061 #define regDIG4_DIG_BE_CNTL_BASE_IDX 2 11062 #define regDIG4_DIG_BE_EN_CNTL 0x254d 11063 #define regDIG4_DIG_BE_EN_CNTL_BASE_IDX 2 11064 #define regDIG4_TMDS_CNTL 0x2574 11065 #define regDIG4_TMDS_CNTL_BASE_IDX 2 11066 #define regDIG4_TMDS_CONTROL_CHAR 0x2575 11067 #define regDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2 11068 #define regDIG4_TMDS_CONTROL0_FEEDBACK 0x2576 11069 #define regDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 11070 #define regDIG4_TMDS_STEREOSYNC_CTL_SEL 0x2577 11071 #define regDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 11072 #define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x2578 11073 #define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 11074 #define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x2579 11075 #define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 11076 #define regDIG4_TMDS_CTL_BITS 0x257b 11077 #define regDIG4_TMDS_CTL_BITS_BASE_IDX 2 11078 #define regDIG4_TMDS_DCBALANCER_CONTROL 0x257c 11079 #define regDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 11080 #define regDIG4_TMDS_SYNC_DCBALANCE_CHAR 0x257d 11081 #define regDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 11082 #define regDIG4_TMDS_CTL0_1_GEN_CNTL 0x257e 11083 #define regDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 11084 #define regDIG4_TMDS_CTL2_3_GEN_CNTL 0x257f 11085 #define regDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 11086 #define regDIG4_DIG_VERSION 0x2581 11087 #define regDIG4_DIG_VERSION_BASE_IDX 2 11088 11089 11090 // addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec 11091 // base address: 0x154cc 11092 #define regAFMT0_AFMT_ACP 0x2073 11093 #define regAFMT0_AFMT_ACP_BASE_IDX 2 11094 #define regAFMT0_AFMT_VBI_PACKET_CONTROL 0x2074 11095 #define regAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 11096 #define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2 0x2075 11097 #define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 11098 #define regAFMT0_AFMT_AUDIO_INFO0 0x2076 11099 #define regAFMT0_AFMT_AUDIO_INFO0_BASE_IDX 2 11100 #define regAFMT0_AFMT_AUDIO_INFO1 0x2077 11101 #define regAFMT0_AFMT_AUDIO_INFO1_BASE_IDX 2 11102 #define regAFMT0_AFMT_60958_0 0x2078 11103 #define regAFMT0_AFMT_60958_0_BASE_IDX 2 11104 #define regAFMT0_AFMT_60958_1 0x2079 11105 #define regAFMT0_AFMT_60958_1_BASE_IDX 2 11106 #define regAFMT0_AFMT_AUDIO_CRC_CONTROL 0x207a 11107 #define regAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 11108 #define regAFMT0_AFMT_RAMP_CONTROL0 0x207b 11109 #define regAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX 2 11110 #define regAFMT0_AFMT_RAMP_CONTROL1 0x207c 11111 #define regAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX 2 11112 #define regAFMT0_AFMT_RAMP_CONTROL2 0x207d 11113 #define regAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX 2 11114 #define regAFMT0_AFMT_RAMP_CONTROL3 0x207e 11115 #define regAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX 2 11116 #define regAFMT0_AFMT_60958_2 0x207f 11117 #define regAFMT0_AFMT_60958_2_BASE_IDX 2 11118 #define regAFMT0_AFMT_AUDIO_CRC_RESULT 0x2080 11119 #define regAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 11120 #define regAFMT0_AFMT_STATUS 0x2081 11121 #define regAFMT0_AFMT_STATUS_BASE_IDX 2 11122 #define regAFMT0_AFMT_AUDIO_PACKET_CONTROL 0x2082 11123 #define regAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 11124 #define regAFMT0_AFMT_INFOFRAME_CONTROL0 0x2083 11125 #define regAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 11126 #define regAFMT0_AFMT_INTERRUPT_STATUS 0x2084 11127 #define regAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX 2 11128 #define regAFMT0_AFMT_AUDIO_SRC_CONTROL 0x2085 11129 #define regAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 11130 #define regAFMT0_AFMT_MEM_PWR 0x2087 11131 #define regAFMT0_AFMT_MEM_PWR_BASE_IDX 2 11132 11133 11134 // addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec 11135 // base address: 0x1595c 11136 #define regAFMT1_AFMT_ACP 0x2197 11137 #define regAFMT1_AFMT_ACP_BASE_IDX 2 11138 #define regAFMT1_AFMT_VBI_PACKET_CONTROL 0x2198 11139 #define regAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 11140 #define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2 0x2199 11141 #define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 11142 #define regAFMT1_AFMT_AUDIO_INFO0 0x219a 11143 #define regAFMT1_AFMT_AUDIO_INFO0_BASE_IDX 2 11144 #define regAFMT1_AFMT_AUDIO_INFO1 0x219b 11145 #define regAFMT1_AFMT_AUDIO_INFO1_BASE_IDX 2 11146 #define regAFMT1_AFMT_60958_0 0x219c 11147 #define regAFMT1_AFMT_60958_0_BASE_IDX 2 11148 #define regAFMT1_AFMT_60958_1 0x219d 11149 #define regAFMT1_AFMT_60958_1_BASE_IDX 2 11150 #define regAFMT1_AFMT_AUDIO_CRC_CONTROL 0x219e 11151 #define regAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 11152 #define regAFMT1_AFMT_RAMP_CONTROL0 0x219f 11153 #define regAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX 2 11154 #define regAFMT1_AFMT_RAMP_CONTROL1 0x21a0 11155 #define regAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX 2 11156 #define regAFMT1_AFMT_RAMP_CONTROL2 0x21a1 11157 #define regAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX 2 11158 #define regAFMT1_AFMT_RAMP_CONTROL3 0x21a2 11159 #define regAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX 2 11160 #define regAFMT1_AFMT_60958_2 0x21a3 11161 #define regAFMT1_AFMT_60958_2_BASE_IDX 2 11162 #define regAFMT1_AFMT_AUDIO_CRC_RESULT 0x21a4 11163 #define regAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 11164 #define regAFMT1_AFMT_STATUS 0x21a5 11165 #define regAFMT1_AFMT_STATUS_BASE_IDX 2 11166 #define regAFMT1_AFMT_AUDIO_PACKET_CONTROL 0x21a6 11167 #define regAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 11168 #define regAFMT1_AFMT_INFOFRAME_CONTROL0 0x21a7 11169 #define regAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 11170 #define regAFMT1_AFMT_INTERRUPT_STATUS 0x21a8 11171 #define regAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX 2 11172 #define regAFMT1_AFMT_AUDIO_SRC_CONTROL 0x21a9 11173 #define regAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 11174 #define regAFMT1_AFMT_MEM_PWR 0x21ab 11175 #define regAFMT1_AFMT_MEM_PWR_BASE_IDX 2 11176 11177 11178 // addressBlock: dce_dc_dio_dig2_afmt_afmt_dispdec 11179 // base address: 0x15dec 11180 #define regAFMT2_AFMT_ACP 0x22bb 11181 #define regAFMT2_AFMT_ACP_BASE_IDX 2 11182 #define regAFMT2_AFMT_VBI_PACKET_CONTROL 0x22bc 11183 #define regAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 11184 #define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2 0x22bd 11185 #define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 11186 #define regAFMT2_AFMT_AUDIO_INFO0 0x22be 11187 #define regAFMT2_AFMT_AUDIO_INFO0_BASE_IDX 2 11188 #define regAFMT2_AFMT_AUDIO_INFO1 0x22bf 11189 #define regAFMT2_AFMT_AUDIO_INFO1_BASE_IDX 2 11190 #define regAFMT2_AFMT_60958_0 0x22c0 11191 #define regAFMT2_AFMT_60958_0_BASE_IDX 2 11192 #define regAFMT2_AFMT_60958_1 0x22c1 11193 #define regAFMT2_AFMT_60958_1_BASE_IDX 2 11194 #define regAFMT2_AFMT_AUDIO_CRC_CONTROL 0x22c2 11195 #define regAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 11196 #define regAFMT2_AFMT_RAMP_CONTROL0 0x22c3 11197 #define regAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX 2 11198 #define regAFMT2_AFMT_RAMP_CONTROL1 0x22c4 11199 #define regAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX 2 11200 #define regAFMT2_AFMT_RAMP_CONTROL2 0x22c5 11201 #define regAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX 2 11202 #define regAFMT2_AFMT_RAMP_CONTROL3 0x22c6 11203 #define regAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX 2 11204 #define regAFMT2_AFMT_60958_2 0x22c7 11205 #define regAFMT2_AFMT_60958_2_BASE_IDX 2 11206 #define regAFMT2_AFMT_AUDIO_CRC_RESULT 0x22c8 11207 #define regAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 11208 #define regAFMT2_AFMT_STATUS 0x22c9 11209 #define regAFMT2_AFMT_STATUS_BASE_IDX 2 11210 #define regAFMT2_AFMT_AUDIO_PACKET_CONTROL 0x22ca 11211 #define regAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 11212 #define regAFMT2_AFMT_INFOFRAME_CONTROL0 0x22cb 11213 #define regAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 11214 #define regAFMT2_AFMT_INTERRUPT_STATUS 0x22cc 11215 #define regAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX 2 11216 #define regAFMT2_AFMT_AUDIO_SRC_CONTROL 0x22cd 11217 #define regAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 11218 #define regAFMT2_AFMT_MEM_PWR 0x22cf 11219 #define regAFMT2_AFMT_MEM_PWR_BASE_IDX 2 11220 11221 11222 // addressBlock: dce_dc_dio_dig3_afmt_afmt_dispdec 11223 // base address: 0x1627c 11224 #define regAFMT3_AFMT_ACP 0x23df 11225 #define regAFMT3_AFMT_ACP_BASE_IDX 2 11226 #define regAFMT3_AFMT_VBI_PACKET_CONTROL 0x23e0 11227 #define regAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 11228 #define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2 0x23e1 11229 #define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 11230 #define regAFMT3_AFMT_AUDIO_INFO0 0x23e2 11231 #define regAFMT3_AFMT_AUDIO_INFO0_BASE_IDX 2 11232 #define regAFMT3_AFMT_AUDIO_INFO1 0x23e3 11233 #define regAFMT3_AFMT_AUDIO_INFO1_BASE_IDX 2 11234 #define regAFMT3_AFMT_60958_0 0x23e4 11235 #define regAFMT3_AFMT_60958_0_BASE_IDX 2 11236 #define regAFMT3_AFMT_60958_1 0x23e5 11237 #define regAFMT3_AFMT_60958_1_BASE_IDX 2 11238 #define regAFMT3_AFMT_AUDIO_CRC_CONTROL 0x23e6 11239 #define regAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 11240 #define regAFMT3_AFMT_RAMP_CONTROL0 0x23e7 11241 #define regAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX 2 11242 #define regAFMT3_AFMT_RAMP_CONTROL1 0x23e8 11243 #define regAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX 2 11244 #define regAFMT3_AFMT_RAMP_CONTROL2 0x23e9 11245 #define regAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX 2 11246 #define regAFMT3_AFMT_RAMP_CONTROL3 0x23ea 11247 #define regAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX 2 11248 #define regAFMT3_AFMT_60958_2 0x23eb 11249 #define regAFMT3_AFMT_60958_2_BASE_IDX 2 11250 #define regAFMT3_AFMT_AUDIO_CRC_RESULT 0x23ec 11251 #define regAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 11252 #define regAFMT3_AFMT_STATUS 0x23ed 11253 #define regAFMT3_AFMT_STATUS_BASE_IDX 2 11254 #define regAFMT3_AFMT_AUDIO_PACKET_CONTROL 0x23ee 11255 #define regAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 11256 #define regAFMT3_AFMT_INFOFRAME_CONTROL0 0x23ef 11257 #define regAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 11258 #define regAFMT3_AFMT_INTERRUPT_STATUS 0x23f0 11259 #define regAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX 2 11260 #define regAFMT3_AFMT_AUDIO_SRC_CONTROL 0x23f1 11261 #define regAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 11262 #define regAFMT3_AFMT_MEM_PWR 0x23f3 11263 #define regAFMT3_AFMT_MEM_PWR_BASE_IDX 2 11264 11265 11266 // addressBlock: dce_dc_dio_dig4_afmt_afmt_dispdec 11267 // base address: 0x1670c 11268 #define regAFMT4_AFMT_ACP 0x2503 11269 #define regAFMT4_AFMT_ACP_BASE_IDX 2 11270 #define regAFMT4_AFMT_VBI_PACKET_CONTROL 0x2504 11271 #define regAFMT4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 11272 #define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2 0x2505 11273 #define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 11274 #define regAFMT4_AFMT_AUDIO_INFO0 0x2506 11275 #define regAFMT4_AFMT_AUDIO_INFO0_BASE_IDX 2 11276 #define regAFMT4_AFMT_AUDIO_INFO1 0x2507 11277 #define regAFMT4_AFMT_AUDIO_INFO1_BASE_IDX 2 11278 #define regAFMT4_AFMT_60958_0 0x2508 11279 #define regAFMT4_AFMT_60958_0_BASE_IDX 2 11280 #define regAFMT4_AFMT_60958_1 0x2509 11281 #define regAFMT4_AFMT_60958_1_BASE_IDX 2 11282 #define regAFMT4_AFMT_AUDIO_CRC_CONTROL 0x250a 11283 #define regAFMT4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 11284 #define regAFMT4_AFMT_RAMP_CONTROL0 0x250b 11285 #define regAFMT4_AFMT_RAMP_CONTROL0_BASE_IDX 2 11286 #define regAFMT4_AFMT_RAMP_CONTROL1 0x250c 11287 #define regAFMT4_AFMT_RAMP_CONTROL1_BASE_IDX 2 11288 #define regAFMT4_AFMT_RAMP_CONTROL2 0x250d 11289 #define regAFMT4_AFMT_RAMP_CONTROL2_BASE_IDX 2 11290 #define regAFMT4_AFMT_RAMP_CONTROL3 0x250e 11291 #define regAFMT4_AFMT_RAMP_CONTROL3_BASE_IDX 2 11292 #define regAFMT4_AFMT_60958_2 0x250f 11293 #define regAFMT4_AFMT_60958_2_BASE_IDX 2 11294 #define regAFMT4_AFMT_AUDIO_CRC_RESULT 0x2510 11295 #define regAFMT4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 11296 #define regAFMT4_AFMT_STATUS 0x2511 11297 #define regAFMT4_AFMT_STATUS_BASE_IDX 2 11298 #define regAFMT4_AFMT_AUDIO_PACKET_CONTROL 0x2512 11299 #define regAFMT4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 11300 #define regAFMT4_AFMT_INFOFRAME_CONTROL0 0x2513 11301 #define regAFMT4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 11302 #define regAFMT4_AFMT_INTERRUPT_STATUS 0x2514 11303 #define regAFMT4_AFMT_INTERRUPT_STATUS_BASE_IDX 2 11304 #define regAFMT4_AFMT_AUDIO_SRC_CONTROL 0x2515 11305 #define regAFMT4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 11306 #define regAFMT4_AFMT_MEM_PWR 0x2517 11307 #define regAFMT4_AFMT_MEM_PWR_BASE_IDX 2 11308 11309 11310 // addressBlock: dce_dc_dio_dig0_dme_dme_dispdec 11311 // base address: 0x15544 11312 #define regDME0_DME_CONTROL 0x2091 11313 #define regDME0_DME_CONTROL_BASE_IDX 2 11314 #define regDME0_DME_MEMORY_CONTROL 0x2092 11315 #define regDME0_DME_MEMORY_CONTROL_BASE_IDX 2 11316 11317 11318 // addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec 11319 // base address: 0x154a0 11320 #define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2068 11321 #define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11322 #define regVPG0_VPG_GENERIC_PACKET_DATA 0x2069 11323 #define regVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11324 #define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL 0x206a 11325 #define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11326 #define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x206b 11327 #define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11328 #define regVPG0_VPG_GENERIC_STATUS 0x206c 11329 #define regVPG0_VPG_GENERIC_STATUS_BASE_IDX 2 11330 #define regVPG0_VPG_MEM_PWR 0x206d 11331 #define regVPG0_VPG_MEM_PWR_BASE_IDX 2 11332 #define regVPG0_VPG_ISRC1_2_ACCESS_CTRL 0x206e 11333 #define regVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11334 #define regVPG0_VPG_ISRC1_2_DATA 0x206f 11335 #define regVPG0_VPG_ISRC1_2_DATA_BASE_IDX 2 11336 #define regVPG0_VPG_MPEG_INFO0 0x2070 11337 #define regVPG0_VPG_MPEG_INFO0_BASE_IDX 2 11338 #define regVPG0_VPG_MPEG_INFO1 0x2071 11339 #define regVPG0_VPG_MPEG_INFO1_BASE_IDX 2 11340 11341 11342 // addressBlock: dce_dc_dio_dig1_dme_dme_dispdec 11343 // base address: 0x159d4 11344 #define regDME1_DME_CONTROL 0x21b5 11345 #define regDME1_DME_CONTROL_BASE_IDX 2 11346 #define regDME1_DME_MEMORY_CONTROL 0x21b6 11347 #define regDME1_DME_MEMORY_CONTROL_BASE_IDX 2 11348 11349 11350 // addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec 11351 // base address: 0x15930 11352 #define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL 0x218c 11353 #define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11354 #define regVPG1_VPG_GENERIC_PACKET_DATA 0x218d 11355 #define regVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11356 #define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL 0x218e 11357 #define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11358 #define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x218f 11359 #define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11360 #define regVPG1_VPG_GENERIC_STATUS 0x2190 11361 #define regVPG1_VPG_GENERIC_STATUS_BASE_IDX 2 11362 #define regVPG1_VPG_MEM_PWR 0x2191 11363 #define regVPG1_VPG_MEM_PWR_BASE_IDX 2 11364 #define regVPG1_VPG_ISRC1_2_ACCESS_CTRL 0x2192 11365 #define regVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11366 #define regVPG1_VPG_ISRC1_2_DATA 0x2193 11367 #define regVPG1_VPG_ISRC1_2_DATA_BASE_IDX 2 11368 #define regVPG1_VPG_MPEG_INFO0 0x2194 11369 #define regVPG1_VPG_MPEG_INFO0_BASE_IDX 2 11370 #define regVPG1_VPG_MPEG_INFO1 0x2195 11371 #define regVPG1_VPG_MPEG_INFO1_BASE_IDX 2 11372 11373 11374 // addressBlock: dce_dc_dio_dig2_dme_dme_dispdec 11375 // base address: 0x15e64 11376 #define regDME2_DME_CONTROL 0x22d9 11377 #define regDME2_DME_CONTROL_BASE_IDX 2 11378 #define regDME2_DME_MEMORY_CONTROL 0x22da 11379 #define regDME2_DME_MEMORY_CONTROL_BASE_IDX 2 11380 11381 11382 // addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec 11383 // base address: 0x15dc0 11384 #define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL 0x22b0 11385 #define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11386 #define regVPG2_VPG_GENERIC_PACKET_DATA 0x22b1 11387 #define regVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11388 #define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL 0x22b2 11389 #define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11390 #define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x22b3 11391 #define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11392 #define regVPG2_VPG_GENERIC_STATUS 0x22b4 11393 #define regVPG2_VPG_GENERIC_STATUS_BASE_IDX 2 11394 #define regVPG2_VPG_MEM_PWR 0x22b5 11395 #define regVPG2_VPG_MEM_PWR_BASE_IDX 2 11396 #define regVPG2_VPG_ISRC1_2_ACCESS_CTRL 0x22b6 11397 #define regVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11398 #define regVPG2_VPG_ISRC1_2_DATA 0x22b7 11399 #define regVPG2_VPG_ISRC1_2_DATA_BASE_IDX 2 11400 #define regVPG2_VPG_MPEG_INFO0 0x22b8 11401 #define regVPG2_VPG_MPEG_INFO0_BASE_IDX 2 11402 #define regVPG2_VPG_MPEG_INFO1 0x22b9 11403 #define regVPG2_VPG_MPEG_INFO1_BASE_IDX 2 11404 11405 11406 // addressBlock: dce_dc_dio_dig3_dme_dme_dispdec 11407 // base address: 0x162f4 11408 #define regDME3_DME_CONTROL 0x23fd 11409 #define regDME3_DME_CONTROL_BASE_IDX 2 11410 #define regDME3_DME_MEMORY_CONTROL 0x23fe 11411 #define regDME3_DME_MEMORY_CONTROL_BASE_IDX 2 11412 11413 11414 // addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec 11415 // base address: 0x16250 11416 #define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL 0x23d4 11417 #define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11418 #define regVPG3_VPG_GENERIC_PACKET_DATA 0x23d5 11419 #define regVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11420 #define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL 0x23d6 11421 #define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11422 #define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x23d7 11423 #define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11424 #define regVPG3_VPG_GENERIC_STATUS 0x23d8 11425 #define regVPG3_VPG_GENERIC_STATUS_BASE_IDX 2 11426 #define regVPG3_VPG_MEM_PWR 0x23d9 11427 #define regVPG3_VPG_MEM_PWR_BASE_IDX 2 11428 #define regVPG3_VPG_ISRC1_2_ACCESS_CTRL 0x23da 11429 #define regVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11430 #define regVPG3_VPG_ISRC1_2_DATA 0x23db 11431 #define regVPG3_VPG_ISRC1_2_DATA_BASE_IDX 2 11432 #define regVPG3_VPG_MPEG_INFO0 0x23dc 11433 #define regVPG3_VPG_MPEG_INFO0_BASE_IDX 2 11434 #define regVPG3_VPG_MPEG_INFO1 0x23dd 11435 #define regVPG3_VPG_MPEG_INFO1_BASE_IDX 2 11436 11437 11438 // addressBlock: dce_dc_dio_dig4_dme_dme_dispdec 11439 // base address: 0x16784 11440 #define regDME4_DME_CONTROL 0x2521 11441 #define regDME4_DME_CONTROL_BASE_IDX 2 11442 #define regDME4_DME_MEMORY_CONTROL 0x2522 11443 #define regDME4_DME_MEMORY_CONTROL_BASE_IDX 2 11444 11445 11446 // addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec 11447 // base address: 0x166e0 11448 #define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL 0x24f8 11449 #define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11450 #define regVPG4_VPG_GENERIC_PACKET_DATA 0x24f9 11451 #define regVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11452 #define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL 0x24fa 11453 #define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11454 #define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x24fb 11455 #define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11456 #define regVPG4_VPG_GENERIC_STATUS 0x24fc 11457 #define regVPG4_VPG_GENERIC_STATUS_BASE_IDX 2 11458 #define regVPG4_VPG_MEM_PWR 0x24fd 11459 #define regVPG4_VPG_MEM_PWR_BASE_IDX 2 11460 #define regVPG4_VPG_ISRC1_2_ACCESS_CTRL 0x24fe 11461 #define regVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11462 #define regVPG4_VPG_ISRC1_2_DATA 0x24ff 11463 #define regVPG4_VPG_ISRC1_2_DATA_BASE_IDX 2 11464 #define regVPG4_VPG_MPEG_INFO0 0x2500 11465 #define regVPG4_VPG_MPEG_INFO0_BASE_IDX 2 11466 #define regVPG4_VPG_MPEG_INFO1 0x2501 11467 #define regVPG4_VPG_MPEG_INFO1_BASE_IDX 2 11468 11469 11470 // addressBlock: dce_dc_dio_dp_aux0_dispdec 11471 // base address: 0x0 11472 #define regDP_AUX0_AUX_CONTROL 0x1f50 11473 #define regDP_AUX0_AUX_CONTROL_BASE_IDX 2 11474 #define regDP_AUX0_AUX_SW_CONTROL 0x1f51 11475 #define regDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2 11476 #define regDP_AUX0_AUX_ARB_CONTROL 0x1f52 11477 #define regDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2 11478 #define regDP_AUX0_AUX_INTERRUPT_CONTROL 0x1f53 11479 #define regDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2 11480 #define regDP_AUX0_AUX_SW_STATUS 0x1f54 11481 #define regDP_AUX0_AUX_SW_STATUS_BASE_IDX 2 11482 #define regDP_AUX0_AUX_LS_STATUS 0x1f55 11483 #define regDP_AUX0_AUX_LS_STATUS_BASE_IDX 2 11484 #define regDP_AUX0_AUX_SW_DATA 0x1f56 11485 #define regDP_AUX0_AUX_SW_DATA_BASE_IDX 2 11486 #define regDP_AUX0_AUX_LS_DATA 0x1f57 11487 #define regDP_AUX0_AUX_LS_DATA_BASE_IDX 2 11488 #define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1f58 11489 #define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 11490 #define regDP_AUX0_AUX_DPHY_TX_CONTROL 0x1f59 11491 #define regDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2 11492 #define regDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1f5a 11493 #define regDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 11494 #define regDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1f5b 11495 #define regDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 11496 #define regDP_AUX0_AUX_DPHY_TX_STATUS 0x1f5c 11497 #define regDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2 11498 #define regDP_AUX0_AUX_DPHY_RX_STATUS 0x1f5d 11499 #define regDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2 11500 #define regDP_AUX0_AUX_GTC_SYNC_CONTROL 0x1f5e 11501 #define regDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 11502 #define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1f5f 11503 #define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 11504 #define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f60 11505 #define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 11506 #define regDP_AUX0_AUX_GTC_SYNC_STATUS 0x1f61 11507 #define regDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2 11508 #define regDP_AUX0_AUX_PHY_WAKE_CNTL 0x1f66 11509 #define regDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX 2 11510 11511 11512 // addressBlock: dce_dc_dio_dp_aux1_dispdec 11513 // base address: 0x70 11514 #define regDP_AUX1_AUX_CONTROL 0x1f6c 11515 #define regDP_AUX1_AUX_CONTROL_BASE_IDX 2 11516 #define regDP_AUX1_AUX_SW_CONTROL 0x1f6d 11517 #define regDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2 11518 #define regDP_AUX1_AUX_ARB_CONTROL 0x1f6e 11519 #define regDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2 11520 #define regDP_AUX1_AUX_INTERRUPT_CONTROL 0x1f6f 11521 #define regDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2 11522 #define regDP_AUX1_AUX_SW_STATUS 0x1f70 11523 #define regDP_AUX1_AUX_SW_STATUS_BASE_IDX 2 11524 #define regDP_AUX1_AUX_LS_STATUS 0x1f71 11525 #define regDP_AUX1_AUX_LS_STATUS_BASE_IDX 2 11526 #define regDP_AUX1_AUX_SW_DATA 0x1f72 11527 #define regDP_AUX1_AUX_SW_DATA_BASE_IDX 2 11528 #define regDP_AUX1_AUX_LS_DATA 0x1f73 11529 #define regDP_AUX1_AUX_LS_DATA_BASE_IDX 2 11530 #define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x1f74 11531 #define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 11532 #define regDP_AUX1_AUX_DPHY_TX_CONTROL 0x1f75 11533 #define regDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2 11534 #define regDP_AUX1_AUX_DPHY_RX_CONTROL0 0x1f76 11535 #define regDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 11536 #define regDP_AUX1_AUX_DPHY_RX_CONTROL1 0x1f77 11537 #define regDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 11538 #define regDP_AUX1_AUX_DPHY_TX_STATUS 0x1f78 11539 #define regDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2 11540 #define regDP_AUX1_AUX_DPHY_RX_STATUS 0x1f79 11541 #define regDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2 11542 #define regDP_AUX1_AUX_GTC_SYNC_CONTROL 0x1f7a 11543 #define regDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 11544 #define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1f7b 11545 #define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 11546 #define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f7c 11547 #define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 11548 #define regDP_AUX1_AUX_GTC_SYNC_STATUS 0x1f7d 11549 #define regDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2 11550 #define regDP_AUX1_AUX_PHY_WAKE_CNTL 0x1f82 11551 #define regDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX 2 11552 11553 11554 // addressBlock: dce_dc_dio_dp_aux2_dispdec 11555 // base address: 0xe0 11556 #define regDP_AUX2_AUX_CONTROL 0x1f88 11557 #define regDP_AUX2_AUX_CONTROL_BASE_IDX 2 11558 #define regDP_AUX2_AUX_SW_CONTROL 0x1f89 11559 #define regDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2 11560 #define regDP_AUX2_AUX_ARB_CONTROL 0x1f8a 11561 #define regDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2 11562 #define regDP_AUX2_AUX_INTERRUPT_CONTROL 0x1f8b 11563 #define regDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2 11564 #define regDP_AUX2_AUX_SW_STATUS 0x1f8c 11565 #define regDP_AUX2_AUX_SW_STATUS_BASE_IDX 2 11566 #define regDP_AUX2_AUX_LS_STATUS 0x1f8d 11567 #define regDP_AUX2_AUX_LS_STATUS_BASE_IDX 2 11568 #define regDP_AUX2_AUX_SW_DATA 0x1f8e 11569 #define regDP_AUX2_AUX_SW_DATA_BASE_IDX 2 11570 #define regDP_AUX2_AUX_LS_DATA 0x1f8f 11571 #define regDP_AUX2_AUX_LS_DATA_BASE_IDX 2 11572 #define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x1f90 11573 #define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 11574 #define regDP_AUX2_AUX_DPHY_TX_CONTROL 0x1f91 11575 #define regDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2 11576 #define regDP_AUX2_AUX_DPHY_RX_CONTROL0 0x1f92 11577 #define regDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 11578 #define regDP_AUX2_AUX_DPHY_RX_CONTROL1 0x1f93 11579 #define regDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 11580 #define regDP_AUX2_AUX_DPHY_TX_STATUS 0x1f94 11581 #define regDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2 11582 #define regDP_AUX2_AUX_DPHY_RX_STATUS 0x1f95 11583 #define regDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2 11584 #define regDP_AUX2_AUX_GTC_SYNC_CONTROL 0x1f96 11585 #define regDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 11586 #define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x1f97 11587 #define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 11588 #define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f98 11589 #define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 11590 #define regDP_AUX2_AUX_GTC_SYNC_STATUS 0x1f99 11591 #define regDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2 11592 #define regDP_AUX2_AUX_PHY_WAKE_CNTL 0x1f9e 11593 #define regDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX 2 11594 11595 11596 // addressBlock: dce_dc_dio_dp_aux3_dispdec 11597 // base address: 0x150 11598 #define regDP_AUX3_AUX_CONTROL 0x1fa4 11599 #define regDP_AUX3_AUX_CONTROL_BASE_IDX 2 11600 #define regDP_AUX3_AUX_SW_CONTROL 0x1fa5 11601 #define regDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2 11602 #define regDP_AUX3_AUX_ARB_CONTROL 0x1fa6 11603 #define regDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2 11604 #define regDP_AUX3_AUX_INTERRUPT_CONTROL 0x1fa7 11605 #define regDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2 11606 #define regDP_AUX3_AUX_SW_STATUS 0x1fa8 11607 #define regDP_AUX3_AUX_SW_STATUS_BASE_IDX 2 11608 #define regDP_AUX3_AUX_LS_STATUS 0x1fa9 11609 #define regDP_AUX3_AUX_LS_STATUS_BASE_IDX 2 11610 #define regDP_AUX3_AUX_SW_DATA 0x1faa 11611 #define regDP_AUX3_AUX_SW_DATA_BASE_IDX 2 11612 #define regDP_AUX3_AUX_LS_DATA 0x1fab 11613 #define regDP_AUX3_AUX_LS_DATA_BASE_IDX 2 11614 #define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x1fac 11615 #define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 11616 #define regDP_AUX3_AUX_DPHY_TX_CONTROL 0x1fad 11617 #define regDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2 11618 #define regDP_AUX3_AUX_DPHY_RX_CONTROL0 0x1fae 11619 #define regDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 11620 #define regDP_AUX3_AUX_DPHY_RX_CONTROL1 0x1faf 11621 #define regDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 11622 #define regDP_AUX3_AUX_DPHY_TX_STATUS 0x1fb0 11623 #define regDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2 11624 #define regDP_AUX3_AUX_DPHY_RX_STATUS 0x1fb1 11625 #define regDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2 11626 #define regDP_AUX3_AUX_GTC_SYNC_CONTROL 0x1fb2 11627 #define regDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 11628 #define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x1fb3 11629 #define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 11630 #define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fb4 11631 #define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 11632 #define regDP_AUX3_AUX_GTC_SYNC_STATUS 0x1fb5 11633 #define regDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2 11634 #define regDP_AUX3_AUX_PHY_WAKE_CNTL 0x1fba 11635 #define regDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX 2 11636 11637 11638 // addressBlock: dce_dc_dio_dp_aux4_dispdec 11639 // base address: 0x1c0 11640 #define regDP_AUX4_AUX_CONTROL 0x1fc0 11641 #define regDP_AUX4_AUX_CONTROL_BASE_IDX 2 11642 #define regDP_AUX4_AUX_SW_CONTROL 0x1fc1 11643 #define regDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2 11644 #define regDP_AUX4_AUX_ARB_CONTROL 0x1fc2 11645 #define regDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2 11646 #define regDP_AUX4_AUX_INTERRUPT_CONTROL 0x1fc3 11647 #define regDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2 11648 #define regDP_AUX4_AUX_SW_STATUS 0x1fc4 11649 #define regDP_AUX4_AUX_SW_STATUS_BASE_IDX 2 11650 #define regDP_AUX4_AUX_LS_STATUS 0x1fc5 11651 #define regDP_AUX4_AUX_LS_STATUS_BASE_IDX 2 11652 #define regDP_AUX4_AUX_SW_DATA 0x1fc6 11653 #define regDP_AUX4_AUX_SW_DATA_BASE_IDX 2 11654 #define regDP_AUX4_AUX_LS_DATA 0x1fc7 11655 #define regDP_AUX4_AUX_LS_DATA_BASE_IDX 2 11656 #define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x1fc8 11657 #define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 11658 #define regDP_AUX4_AUX_DPHY_TX_CONTROL 0x1fc9 11659 #define regDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2 11660 #define regDP_AUX4_AUX_DPHY_RX_CONTROL0 0x1fca 11661 #define regDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 11662 #define regDP_AUX4_AUX_DPHY_RX_CONTROL1 0x1fcb 11663 #define regDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 11664 #define regDP_AUX4_AUX_DPHY_TX_STATUS 0x1fcc 11665 #define regDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2 11666 #define regDP_AUX4_AUX_DPHY_RX_STATUS 0x1fcd 11667 #define regDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2 11668 #define regDP_AUX4_AUX_GTC_SYNC_CONTROL 0x1fce 11669 #define regDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 11670 #define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x1fcf 11671 #define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 11672 #define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fd0 11673 #define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 11674 #define regDP_AUX4_AUX_GTC_SYNC_STATUS 0x1fd1 11675 #define regDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2 11676 #define regDP_AUX4_AUX_PHY_WAKE_CNTL 0x1fd6 11677 #define regDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX 2 11678 11679 11680 // addressBlock: dce_dc_dio_dio_dpia_mux0_dispdec 11681 // base address: 0x14de0 11682 #define regDIO_DPIA_MUX0_DIO_DPIA_MUX_CONTROL 0x1eb8 11683 #define regDIO_DPIA_MUX0_DIO_DPIA_MUX_CONTROL_BASE_IDX 2 11684 11685 11686 // addressBlock: dce_dc_dio_dio_dpia_mux1_dispdec 11687 // base address: 0x14de4 11688 #define regDIO_DPIA_MUX1_DIO_DPIA_MUX_CONTROL 0x1eb9 11689 #define regDIO_DPIA_MUX1_DIO_DPIA_MUX_CONTROL_BASE_IDX 2 11690 11691 11692 // addressBlock: dce_dc_dio_dio_dpia_mux2_dispdec 11693 // base address: 0x14de8 11694 #define regDIO_DPIA_MUX2_DIO_DPIA_MUX_CONTROL 0x1eba 11695 #define regDIO_DPIA_MUX2_DIO_DPIA_MUX_CONTROL_BASE_IDX 2 11696 11697 11698 // addressBlock: dce_dc_dio_dio_dpia_mux3_dispdec 11699 // base address: 0x14dec 11700 #define regDIO_DPIA_MUX3_DIO_DPIA_MUX_CONTROL 0x1ebb 11701 #define regDIO_DPIA_MUX3_DIO_DPIA_MUX_CONTROL_BASE_IDX 2 11702 11703 11704 // addressBlock: dce_dc_dio_dout_i2c_dispdec 11705 // base address: 0x0 11706 #define regDC_I2C_CONTROL 0x1e98 11707 #define regDC_I2C_CONTROL_BASE_IDX 2 11708 #define regDC_I2C_ARBITRATION 0x1e99 11709 #define regDC_I2C_ARBITRATION_BASE_IDX 2 11710 #define regDC_I2C_INTERRUPT_CONTROL 0x1e9a 11711 #define regDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2 11712 #define regDC_I2C_SW_STATUS 0x1e9b 11713 #define regDC_I2C_SW_STATUS_BASE_IDX 2 11714 #define regDC_I2C_DDC1_HW_STATUS 0x1e9c 11715 #define regDC_I2C_DDC1_HW_STATUS_BASE_IDX 2 11716 #define regDC_I2C_DDC2_HW_STATUS 0x1e9d 11717 #define regDC_I2C_DDC2_HW_STATUS_BASE_IDX 2 11718 #define regDC_I2C_DDC3_HW_STATUS 0x1e9e 11719 #define regDC_I2C_DDC3_HW_STATUS_BASE_IDX 2 11720 #define regDC_I2C_DDC4_HW_STATUS 0x1e9f 11721 #define regDC_I2C_DDC4_HW_STATUS_BASE_IDX 2 11722 #define regDC_I2C_DDC5_HW_STATUS 0x1ea0 11723 #define regDC_I2C_DDC5_HW_STATUS_BASE_IDX 2 11724 #define regDC_I2C_DDC1_SPEED 0x1ea2 11725 #define regDC_I2C_DDC1_SPEED_BASE_IDX 2 11726 #define regDC_I2C_DDC1_SETUP 0x1ea3 11727 #define regDC_I2C_DDC1_SETUP_BASE_IDX 2 11728 #define regDC_I2C_DDC2_SPEED 0x1ea4 11729 #define regDC_I2C_DDC2_SPEED_BASE_IDX 2 11730 #define regDC_I2C_DDC2_SETUP 0x1ea5 11731 #define regDC_I2C_DDC2_SETUP_BASE_IDX 2 11732 #define regDC_I2C_DDC3_SPEED 0x1ea6 11733 #define regDC_I2C_DDC3_SPEED_BASE_IDX 2 11734 #define regDC_I2C_DDC3_SETUP 0x1ea7 11735 #define regDC_I2C_DDC3_SETUP_BASE_IDX 2 11736 #define regDC_I2C_DDC4_SPEED 0x1ea8 11737 #define regDC_I2C_DDC4_SPEED_BASE_IDX 2 11738 #define regDC_I2C_DDC4_SETUP 0x1ea9 11739 #define regDC_I2C_DDC4_SETUP_BASE_IDX 2 11740 #define regDC_I2C_DDC5_SPEED 0x1eaa 11741 #define regDC_I2C_DDC5_SPEED_BASE_IDX 2 11742 #define regDC_I2C_DDC5_SETUP 0x1eab 11743 #define regDC_I2C_DDC5_SETUP_BASE_IDX 2 11744 #define regDC_I2C_TRANSACTION0 0x1eae 11745 #define regDC_I2C_TRANSACTION0_BASE_IDX 2 11746 #define regDC_I2C_TRANSACTION1 0x1eaf 11747 #define regDC_I2C_TRANSACTION1_BASE_IDX 2 11748 #define regDC_I2C_TRANSACTION2 0x1eb0 11749 #define regDC_I2C_TRANSACTION2_BASE_IDX 2 11750 #define regDC_I2C_TRANSACTION3 0x1eb1 11751 #define regDC_I2C_TRANSACTION3_BASE_IDX 2 11752 #define regDC_I2C_DATA 0x1eb2 11753 #define regDC_I2C_DATA_BASE_IDX 2 11754 #define regDC_I2C_EDID_DETECT_CTRL 0x1eb6 11755 #define regDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2 11756 #define regDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7 11757 #define regDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2 11758 11759 11760 // addressBlock: dce_dc_dio_dio_misc_dispdec 11761 // base address: 0x0 11762 #define regDIO_DCN_STATUS 0x1ec3 11763 #define regDIO_DCN_STATUS_BASE_IDX 2 11764 #define regDIO_SCRATCH0 0x1eca 11765 #define regDIO_SCRATCH0_BASE_IDX 2 11766 #define regDIO_SCRATCH1 0x1ecb 11767 #define regDIO_SCRATCH1_BASE_IDX 2 11768 #define regDIO_SCRATCH2 0x1ecc 11769 #define regDIO_SCRATCH2_BASE_IDX 2 11770 #define regDIO_SCRATCH3 0x1ecd 11771 #define regDIO_SCRATCH3_BASE_IDX 2 11772 #define regDIO_SCRATCH4 0x1ece 11773 #define regDIO_SCRATCH4_BASE_IDX 2 11774 #define regDIO_SCRATCH5 0x1ecf 11775 #define regDIO_SCRATCH5_BASE_IDX 2 11776 #define regDIO_SCRATCH6 0x1ed0 11777 #define regDIO_SCRATCH6_BASE_IDX 2 11778 #define regDIO_SCRATCH7 0x1ed1 11779 #define regDIO_SCRATCH7_BASE_IDX 2 11780 #define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS 0x1ed3 11781 #define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS_BASE_IDX 2 11782 #define regDIO_MEM_PWR_STATUS 0x1edd 11783 #define regDIO_MEM_PWR_STATUS_BASE_IDX 2 11784 #define regDIO_MEM_PWR_CTRL 0x1ede 11785 #define regDIO_MEM_PWR_CTRL_BASE_IDX 2 11786 #define regDIO_MEM_PWR_CTRL2 0x1edf 11787 #define regDIO_MEM_PWR_CTRL2_BASE_IDX 2 11788 #define regDIO_CLK_CNTL 0x1ee0 11789 #define regDIO_CLK_CNTL_BASE_IDX 2 11790 #define regDIO_POWER_MANAGEMENT_CNTL 0x1ee4 11791 #define regDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2 11792 #define regDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff 11793 #define regDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2 11794 #define regDIO_PSP_INTERRUPT_STATUS 0x1f00 11795 #define regDIO_PSP_INTERRUPT_STATUS_BASE_IDX 2 11796 #define regDIO_PSP_INTERRUPT_CLEAR 0x1f01 11797 #define regDIO_PSP_INTERRUPT_CLEAR_BASE_IDX 2 11798 #define regDIO_STATUS 0x1f02 11799 #define regDIO_STATUS_BASE_IDX 2 11800 #define regDIO_LINKA_CNTL 0x1f04 11801 #define regDIO_LINKA_CNTL_BASE_IDX 2 11802 #define regDIO_LINKB_CNTL 0x1f05 11803 #define regDIO_LINKB_CNTL_BASE_IDX 2 11804 #define regDIO_LINKC_CNTL 0x1f06 11805 #define regDIO_LINKC_CNTL_BASE_IDX 2 11806 #define regDIO_LINKD_CNTL 0x1f07 11807 #define regDIO_LINKD_CNTL_BASE_IDX 2 11808 #define regDIO_LINKE_CNTL 0x1f08 11809 #define regDIO_LINKE_CNTL_BASE_IDX 2 11810 #define regDIO_LINKF_CNTL 0x1f09 11811 #define regDIO_LINKF_CNTL_BASE_IDX 2 11812 11813 11814 // addressBlock: dce_dc_dio_dig_stream_mapper_dispdec 11815 // base address: 0x0 11816 #define regDIG0_STREAM_MAPPER_CONTROL 0x1f0d 11817 #define regDIG0_STREAM_MAPPER_CONTROL_BASE_IDX 2 11818 #define regDIG1_STREAM_MAPPER_CONTROL 0x1f0e 11819 #define regDIG1_STREAM_MAPPER_CONTROL_BASE_IDX 2 11820 #define regDIG2_STREAM_MAPPER_CONTROL 0x1f0f 11821 #define regDIG2_STREAM_MAPPER_CONTROL_BASE_IDX 2 11822 #define regDIG3_STREAM_MAPPER_CONTROL 0x1f10 11823 #define regDIG3_STREAM_MAPPER_CONTROL_BASE_IDX 2 11824 #define regDIG4_STREAM_MAPPER_CONTROL 0x1f11 11825 #define regDIG4_STREAM_MAPPER_CONTROL_BASE_IDX 2 11826 11827 11828 // addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec 11829 // base address: 0x7d10 11830 #define regDC_PERFMON18_PERFCOUNTER_CNTL 0x1f44 11831 #define regDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX 2 11832 #define regDC_PERFMON18_PERFCOUNTER_CNTL2 0x1f45 11833 #define regDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX 2 11834 #define regDC_PERFMON18_PERFCOUNTER_STATE 0x1f46 11835 #define regDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX 2 11836 #define regDC_PERFMON18_PERFMON_CNTL 0x1f47 11837 #define regDC_PERFMON18_PERFMON_CNTL_BASE_IDX 2 11838 #define regDC_PERFMON18_PERFMON_CNTL2 0x1f48 11839 #define regDC_PERFMON18_PERFMON_CNTL2_BASE_IDX 2 11840 #define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC 0x1f49 11841 #define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 11842 #define regDC_PERFMON18_PERFMON_CVALUE_LOW 0x1f4a 11843 #define regDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX 2 11844 #define regDC_PERFMON18_PERFMON_HI 0x1f4b 11845 #define regDC_PERFMON18_PERFMON_HI_BASE_IDX 2 11846 #define regDC_PERFMON18_PERFMON_LOW 0x1f4c 11847 #define regDC_PERFMON18_PERFMON_LOW_BASE_IDX 2 11848 11849 11850 // addressBlock: dce_dc_dcio_dcio_dispdec 11851 // base address: 0x0 11852 #define regDC_GENERICA 0x2868 11853 #define regDC_GENERICA_BASE_IDX 2 11854 #define regDC_GENERICB 0x2869 11855 #define regDC_GENERICB_BASE_IDX 2 11856 #define regDCIO_CLOCK_CNTL 0x286a 11857 #define regDCIO_CLOCK_CNTL_BASE_IDX 2 11858 #define regDC_REF_CLK_CNTL 0x286b 11859 #define regDC_REF_CLK_CNTL_BASE_IDX 2 11860 #define regUNIPHYA_LINK_CNTL 0x286d 11861 #define regUNIPHYA_LINK_CNTL_BASE_IDX 2 11862 #define regUNIPHYA_CHANNEL_XBAR_CNTL 0x286e 11863 #define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2 11864 #define regUNIPHYB_LINK_CNTL 0x286f 11865 #define regUNIPHYB_LINK_CNTL_BASE_IDX 2 11866 #define regUNIPHYB_CHANNEL_XBAR_CNTL 0x2870 11867 #define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2 11868 #define regUNIPHYC_LINK_CNTL 0x2871 11869 #define regUNIPHYC_LINK_CNTL_BASE_IDX 2 11870 #define regUNIPHYC_CHANNEL_XBAR_CNTL 0x2872 11871 #define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2 11872 #define regUNIPHYD_CHANNEL_XBAR_CNTL 0x2874 11873 #define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2 11874 #define regUNIPHYE_CHANNEL_XBAR_CNTL 0x2876 11875 #define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2 11876 #define regDCIO_WRCMD_DELAY 0x287e 11877 #define regDCIO_WRCMD_DELAY_BASE_IDX 2 11878 #define regDC_PINSTRAPS 0x2880 11879 #define regDC_PINSTRAPS_BASE_IDX 2 11880 #define regDCIO_SPARE 0x2882 11881 #define regDCIO_SPARE_BASE_IDX 2 11882 #define regINTERCEPT_STATE 0x2884 11883 #define regINTERCEPT_STATE_BASE_IDX 2 11884 #define regDCIO_PATTERN_GEN_PAT 0x2886 11885 #define regDCIO_PATTERN_GEN_PAT_BASE_IDX 2 11886 #define regDCIO_PATTERN_GEN_EN 0x2887 11887 #define regDCIO_PATTERN_GEN_EN_BASE_IDX 2 11888 #define regDCIO_BL_PWM_FRAME_START_DISP_SEL 0x288b 11889 #define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX 2 11890 #define regDCIO_GSL_GENLK_PAD_CNTL 0x288c 11891 #define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2 11892 #define regDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d 11893 #define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2 11894 #define regDCIO_SOFT_RESET 0x289e 11895 #define regDCIO_SOFT_RESET_BASE_IDX 2 11896 11897 11898 // addressBlock: dce_dc_dcio_dcio_chip_dispdec 11899 // base address: 0x0 11900 #define regDC_GPIO_GENERIC_MASK 0x28c8 11901 #define regDC_GPIO_GENERIC_MASK_BASE_IDX 2 11902 #define regDC_GPIO_GENERIC_A 0x28c9 11903 #define regDC_GPIO_GENERIC_A_BASE_IDX 2 11904 #define regDC_GPIO_GENERIC_EN 0x28ca 11905 #define regDC_GPIO_GENERIC_EN_BASE_IDX 2 11906 #define regDC_GPIO_GENERIC_Y 0x28cb 11907 #define regDC_GPIO_GENERIC_Y_BASE_IDX 2 11908 #define regDC_GPIO_DDC1_MASK 0x28d0 11909 #define regDC_GPIO_DDC1_MASK_BASE_IDX 2 11910 #define regDC_GPIO_DDC1_A 0x28d1 11911 #define regDC_GPIO_DDC1_A_BASE_IDX 2 11912 #define regDC_GPIO_DDC1_EN 0x28d2 11913 #define regDC_GPIO_DDC1_EN_BASE_IDX 2 11914 #define regDC_GPIO_DDC1_Y 0x28d3 11915 #define regDC_GPIO_DDC1_Y_BASE_IDX 2 11916 #define regDC_GPIO_DDC2_MASK 0x28d4 11917 #define regDC_GPIO_DDC2_MASK_BASE_IDX 2 11918 #define regDC_GPIO_DDC2_A 0x28d5 11919 #define regDC_GPIO_DDC2_A_BASE_IDX 2 11920 #define regDC_GPIO_DDC2_EN 0x28d6 11921 #define regDC_GPIO_DDC2_EN_BASE_IDX 2 11922 #define regDC_GPIO_DDC2_Y 0x28d7 11923 #define regDC_GPIO_DDC2_Y_BASE_IDX 2 11924 #define regDC_GPIO_DDC3_MASK 0x28d8 11925 #define regDC_GPIO_DDC3_MASK_BASE_IDX 2 11926 #define regDC_GPIO_DDC3_A 0x28d9 11927 #define regDC_GPIO_DDC3_A_BASE_IDX 2 11928 #define regDC_GPIO_DDC3_EN 0x28da 11929 #define regDC_GPIO_DDC3_EN_BASE_IDX 2 11930 #define regDC_GPIO_DDC3_Y 0x28db 11931 #define regDC_GPIO_DDC3_Y_BASE_IDX 2 11932 #define regDC_GPIO_DDC4_MASK 0x28dc 11933 #define regDC_GPIO_DDC4_MASK_BASE_IDX 2 11934 #define regDC_GPIO_DDC4_A 0x28dd 11935 #define regDC_GPIO_DDC4_A_BASE_IDX 2 11936 #define regDC_GPIO_DDC4_EN 0x28de 11937 #define regDC_GPIO_DDC4_EN_BASE_IDX 2 11938 #define regDC_GPIO_DDC4_Y 0x28df 11939 #define regDC_GPIO_DDC4_Y_BASE_IDX 2 11940 #define regDC_GPIO_DDC5_MASK 0x28e0 11941 #define regDC_GPIO_DDC5_MASK_BASE_IDX 2 11942 #define regDC_GPIO_DDC5_A 0x28e1 11943 #define regDC_GPIO_DDC5_A_BASE_IDX 2 11944 #define regDC_GPIO_DDC5_EN 0x28e2 11945 #define regDC_GPIO_DDC5_EN_BASE_IDX 2 11946 #define regDC_GPIO_DDC5_Y 0x28e3 11947 #define regDC_GPIO_DDC5_Y_BASE_IDX 2 11948 #define regDC_GPIO_DDCVGA_MASK 0x28e8 11949 #define regDC_GPIO_DDCVGA_MASK_BASE_IDX 2 11950 #define regDC_GPIO_DDCVGA_A 0x28e9 11951 #define regDC_GPIO_DDCVGA_A_BASE_IDX 2 11952 #define regDC_GPIO_DDCVGA_EN 0x28ea 11953 #define regDC_GPIO_DDCVGA_EN_BASE_IDX 2 11954 #define regDC_GPIO_DDCVGA_Y 0x28eb 11955 #define regDC_GPIO_DDCVGA_Y_BASE_IDX 2 11956 #define regDC_GPIO_GENLK_MASK 0x28f0 11957 #define regDC_GPIO_GENLK_MASK_BASE_IDX 2 11958 #define regDC_GPIO_GENLK_A 0x28f1 11959 #define regDC_GPIO_GENLK_A_BASE_IDX 2 11960 #define regDC_GPIO_GENLK_EN 0x28f2 11961 #define regDC_GPIO_GENLK_EN_BASE_IDX 2 11962 #define regDC_GPIO_GENLK_Y 0x28f3 11963 #define regDC_GPIO_GENLK_Y_BASE_IDX 2 11964 #define regDC_GPIO_HPD_MASK 0x28f4 11965 #define regDC_GPIO_HPD_MASK_BASE_IDX 2 11966 #define regDC_GPIO_HPD_A 0x28f5 11967 #define regDC_GPIO_HPD_A_BASE_IDX 2 11968 #define regDC_GPIO_HPD_EN 0x28f6 11969 #define regDC_GPIO_HPD_EN_BASE_IDX 2 11970 #define regDC_GPIO_HPD_Y 0x28f7 11971 #define regDC_GPIO_HPD_Y_BASE_IDX 2 11972 #define regDC_GPIO_DRIVE_STRENGTH_S0 0x28f8 11973 #define regDC_GPIO_DRIVE_STRENGTH_S0_BASE_IDX 2 11974 #define regDC_GPIO_DRIVE_STRENGTH_S1 0x28f9 11975 #define regDC_GPIO_DRIVE_STRENGTH_S1_BASE_IDX 2 11976 #define regDC_GPIO_PWRSEQ0_EN 0x28fa 11977 #define regDC_GPIO_PWRSEQ0_EN_BASE_IDX 2 11978 #define regDC_GPIO_PAD_STRENGTH_1 0x28fc 11979 #define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2 11980 #define regDC_GPIO_PAD_STRENGTH_2 0x28fd 11981 #define regDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2 11982 #define regPHY_AUX_CNTL 0x28ff 11983 #define regPHY_AUX_CNTL_BASE_IDX 2 11984 #define regDC_GPIO_DRIVE_TXIMPSEL 0x2900 11985 #define regDC_GPIO_DRIVE_TXIMPSEL_BASE_IDX 2 11986 #define regDC_GPIO_PWRSEQ1_EN 0x2902 11987 #define regDC_GPIO_PWRSEQ1_EN_BASE_IDX 2 11988 #define regDC_GPIO_TX12_EN 0x2915 11989 #define regDC_GPIO_TX12_EN_BASE_IDX 2 11990 #define regDC_GPIO_AUX_CTRL_0 0x2916 11991 #define regDC_GPIO_AUX_CTRL_0_BASE_IDX 2 11992 #define regDC_GPIO_AUX_CTRL_1 0x2917 11993 #define regDC_GPIO_AUX_CTRL_1_BASE_IDX 2 11994 #define regDC_GPIO_AUX_CTRL_2 0x2918 11995 #define regDC_GPIO_AUX_CTRL_2_BASE_IDX 2 11996 #define regDC_GPIO_RXEN 0x2919 11997 #define regDC_GPIO_RXEN_BASE_IDX 2 11998 #define regDC_GPIO_PULLUPEN 0x291a 11999 #define regDC_GPIO_PULLUPEN_BASE_IDX 2 12000 #define regDC_GPIO_AUX_CTRL_3 0x291b 12001 #define regDC_GPIO_AUX_CTRL_3_BASE_IDX 2 12002 #define regDC_GPIO_AUX_CTRL_4 0x291c 12003 #define regDC_GPIO_AUX_CTRL_4_BASE_IDX 2 12004 #define regDC_GPIO_AUX_CTRL_5 0x291d 12005 #define regDC_GPIO_AUX_CTRL_5_BASE_IDX 2 12006 #define regAUXI2C_PAD_ALL_PWR_OK 0x291e 12007 #define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2 12008 12009 12010 // addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec 12011 // base address: 0x360 12012 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2a00 12013 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 12014 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2a01 12015 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 12016 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2a02 12017 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 12018 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2a03 12019 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 12020 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x2a04 12021 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 12022 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x2a05 12023 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 12024 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x2a06 12025 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 12026 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x2a07 12027 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 12028 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x2a08 12029 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 12030 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x2a09 12031 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 12032 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2a0a 12033 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 12034 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2a0b 12035 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 12036 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2a0c 12037 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 12038 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2a0d 12039 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 12040 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2a0e 12041 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 12042 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2a0f 12043 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 12044 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2a10 12045 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 12046 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2a11 12047 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 12048 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2a12 12049 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 12050 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2a13 12051 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 12052 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x2a14 12053 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 12054 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x2a15 12055 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 12056 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x2a16 12057 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 12058 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x2a17 12059 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 12060 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x2a18 12061 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 12062 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x2a19 12063 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 12064 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2a1a 12065 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 12066 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2a1b 12067 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 12068 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2a1c 12069 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 12070 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2a1d 12071 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 12072 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2a1e 12073 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 12074 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2a1f 12075 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 12076 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2a20 12077 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 12078 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2a21 12079 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 12080 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2a22 12081 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 12082 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2a23 12083 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 12084 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x2a24 12085 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 12086 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x2a25 12087 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 12088 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x2a26 12089 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 12090 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x2a27 12091 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 12092 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x2a28 12093 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 12094 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x2a29 12095 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 12096 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2a2a 12097 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 12098 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2a2b 12099 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 12100 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2a2c 12101 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 12102 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2a2d 12103 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 12104 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2a2e 12105 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 12106 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2a2f 12107 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 12108 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x2a30 12109 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 12110 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x2a31 12111 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 12112 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x2a32 12113 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 12114 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x2a33 12115 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 12116 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x2a34 12117 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 12118 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x2a35 12119 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 12120 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x2a36 12121 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 12122 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x2a37 12123 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 12124 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x2a38 12125 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 12126 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x2a39 12127 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 12128 12129 12130 // addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec 12131 // base address: 0x6c0 12132 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x2ad8 12133 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 12134 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x2ad9 12135 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 12136 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x2ada 12137 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 12138 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x2adb 12139 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 12140 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x2adc 12141 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 12142 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x2add 12143 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 12144 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x2ade 12145 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 12146 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x2adf 12147 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 12148 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x2ae0 12149 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 12150 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x2ae1 12151 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 12152 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x2ae2 12153 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 12154 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x2ae3 12155 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 12156 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x2ae4 12157 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 12158 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x2ae5 12159 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 12160 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x2ae6 12161 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 12162 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x2ae7 12163 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 12164 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x2ae8 12165 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 12166 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x2ae9 12167 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 12168 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x2aea 12169 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 12170 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x2aeb 12171 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 12172 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x2aec 12173 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 12174 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x2aed 12175 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 12176 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x2aee 12177 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 12178 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x2aef 12179 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 12180 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x2af0 12181 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 12182 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x2af1 12183 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 12184 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x2af2 12185 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 12186 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x2af3 12187 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 12188 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x2af4 12189 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 12190 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x2af5 12191 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 12192 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x2af6 12193 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 12194 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x2af7 12195 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 12196 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x2af8 12197 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 12198 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x2af9 12199 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 12200 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x2afa 12201 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 12202 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x2afb 12203 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 12204 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x2afc 12205 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 12206 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x2afd 12207 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 12208 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x2afe 12209 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 12210 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x2aff 12211 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 12212 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x2b00 12213 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 12214 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x2b01 12215 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 12216 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x2b02 12217 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 12218 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x2b03 12219 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 12220 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x2b04 12221 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 12222 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x2b05 12223 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 12224 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x2b06 12225 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 12226 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x2b07 12227 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 12228 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x2b08 12229 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 12230 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x2b09 12231 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 12232 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x2b0a 12233 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 12234 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x2b0b 12235 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 12236 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x2b0c 12237 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 12238 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x2b0d 12239 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 12240 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x2b0e 12241 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 12242 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x2b0f 12243 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 12244 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x2b10 12245 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 12246 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x2b11 12247 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 12248 12249 12250 // addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec 12251 // base address: 0xa20 12252 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2bb0 12253 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 12254 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2bb1 12255 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 12256 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2bb2 12257 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 12258 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2bb3 12259 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 12260 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x2bb4 12261 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 12262 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x2bb5 12263 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 12264 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x2bb6 12265 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 12266 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x2bb7 12267 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 12268 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x2bb8 12269 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 12270 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x2bb9 12271 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 12272 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x2bba 12273 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 12274 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x2bbb 12275 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 12276 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x2bbc 12277 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 12278 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x2bbd 12279 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 12280 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x2bbe 12281 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 12282 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x2bbf 12283 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 12284 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x2bc0 12285 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 12286 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x2bc1 12287 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 12288 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x2bc2 12289 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 12290 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x2bc3 12291 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 12292 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x2bc4 12293 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 12294 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x2bc5 12295 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 12296 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x2bc6 12297 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 12298 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x2bc7 12299 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 12300 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x2bc8 12301 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 12302 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x2bc9 12303 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 12304 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x2bca 12305 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 12306 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x2bcb 12307 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 12308 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x2bcc 12309 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 12310 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x2bcd 12311 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 12312 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x2bce 12313 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 12314 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x2bcf 12315 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 12316 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x2bd0 12317 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 12318 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x2bd1 12319 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 12320 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x2bd2 12321 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 12322 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x2bd3 12323 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 12324 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x2bd4 12325 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 12326 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x2bd5 12327 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 12328 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x2bd6 12329 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 12330 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x2bd7 12331 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 12332 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x2bd8 12333 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 12334 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x2bd9 12335 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 12336 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x2bda 12337 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 12338 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x2bdb 12339 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 12340 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x2bdc 12341 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 12342 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x2bdd 12343 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 12344 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x2bde 12345 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 12346 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x2bdf 12347 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 12348 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x2be0 12349 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 12350 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x2be1 12351 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 12352 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x2be2 12353 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 12354 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x2be3 12355 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 12356 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x2be4 12357 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 12358 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x2be5 12359 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 12360 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x2be6 12361 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 12362 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x2be7 12363 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 12364 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x2be8 12365 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 12366 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x2be9 12367 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 12368 12369 12370 // addressBlock: dce_dc_dcio_dcio_uniphy4_dispdec 12371 // base address: 0xd80 12372 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x2c88 12373 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 12374 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x2c89 12375 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 12376 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x2c8a 12377 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 12378 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x2c8b 12379 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 12380 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x2c8c 12381 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 12382 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x2c8d 12383 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 12384 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x2c8e 12385 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 12386 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x2c8f 12387 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 12388 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x2c90 12389 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 12390 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x2c91 12391 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 12392 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x2c92 12393 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 12394 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x2c93 12395 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 12396 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x2c94 12397 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 12398 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x2c95 12399 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 12400 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x2c96 12401 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 12402 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x2c97 12403 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 12404 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x2c98 12405 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 12406 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x2c99 12407 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 12408 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x2c9a 12409 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 12410 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x2c9b 12411 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 12412 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x2c9c 12413 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 12414 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x2c9d 12415 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 12416 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x2c9e 12417 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 12418 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x2c9f 12419 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 12420 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x2ca0 12421 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 12422 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x2ca1 12423 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 12424 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x2ca2 12425 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 12426 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x2ca3 12427 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 12428 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x2ca4 12429 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 12430 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x2ca5 12431 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 12432 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x2ca6 12433 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 12434 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x2ca7 12435 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 12436 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 0x2ca8 12437 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 12438 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 0x2ca9 12439 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 12440 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 0x2caa 12441 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 12442 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 0x2cab 12443 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 12444 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 0x2cac 12445 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 12446 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 0x2cad 12447 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 12448 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 0x2cae 12449 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 12450 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 0x2caf 12451 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 12452 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 0x2cb0 12453 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 12454 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 0x2cb1 12455 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 12456 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 0x2cb2 12457 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 12458 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 0x2cb3 12459 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 12460 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 0x2cb4 12461 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 12462 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 0x2cb5 12463 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 12464 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 0x2cb6 12465 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 12466 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 0x2cb7 12467 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 12468 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 0x2cb8 12469 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 12470 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 0x2cb9 12471 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 12472 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 0x2cba 12473 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 12474 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 0x2cbb 12475 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 12476 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 0x2cbc 12477 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 12478 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 0x2cbd 12479 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 12480 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 0x2cbe 12481 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 12482 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 0x2cbf 12483 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 12484 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 0x2cc0 12485 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 12486 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 0x2cc1 12487 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 12488 12489 12490 // addressBlock: dce_dc_pwrseq0_dispdec_pwrseq_dispdec 12491 // base address: 0x0 12492 #define regPWRSEQ0_DC_GPIO_PWRSEQ_EN 0x2f10 12493 #define regPWRSEQ0_DC_GPIO_PWRSEQ_EN_BASE_IDX 2 12494 #define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL 0x2f11 12495 #define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL_BASE_IDX 2 12496 #define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK 0x2f12 12497 #define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK_BASE_IDX 2 12498 #define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y 0x2f13 12499 #define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y_BASE_IDX 2 12500 #define regPWRSEQ0_PANEL_PWRSEQ_CNTL 0x2f14 12501 #define regPWRSEQ0_PANEL_PWRSEQ_CNTL_BASE_IDX 2 12502 #define regPWRSEQ0_PANEL_PWRSEQ_STATE 0x2f15 12503 #define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX 2 12504 #define regPWRSEQ0_PANEL_PWRSEQ_DELAY1 0x2f16 12505 #define regPWRSEQ0_PANEL_PWRSEQ_DELAY1_BASE_IDX 2 12506 #define regPWRSEQ0_PANEL_PWRSEQ_DELAY2 0x2f17 12507 #define regPWRSEQ0_PANEL_PWRSEQ_DELAY2_BASE_IDX 2 12508 #define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1 0x2f18 12509 #define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1_BASE_IDX 2 12510 #define regPWRSEQ0_BL_PWM_CNTL 0x2f19 12511 #define regPWRSEQ0_BL_PWM_CNTL_BASE_IDX 2 12512 #define regPWRSEQ0_BL_PWM_CNTL2 0x2f1a 12513 #define regPWRSEQ0_BL_PWM_CNTL2_BASE_IDX 2 12514 #define regPWRSEQ0_BL_PWM_PERIOD_CNTL 0x2f1b 12515 #define regPWRSEQ0_BL_PWM_PERIOD_CNTL_BASE_IDX 2 12516 #define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK 0x2f1c 12517 #define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK_BASE_IDX 2 12518 #define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2 0x2f1d 12519 #define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2_BASE_IDX 2 12520 #define regPWRSEQ0_PWRSEQ_SPARE 0x2f21 12521 #define regPWRSEQ0_PWRSEQ_SPARE_BASE_IDX 2 12522 12523 12524 // addressBlock: dce_dc_pwrseq1_dispdec_pwrseq_dispdec 12525 // base address: 0x1b0 12526 #define regPWRSEQ1_DC_GPIO_PWRSEQ_EN 0x2f7c 12527 #define regPWRSEQ1_DC_GPIO_PWRSEQ_EN_BASE_IDX 2 12528 #define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL 0x2f7d 12529 #define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL_BASE_IDX 2 12530 #define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK 0x2f7e 12531 #define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK_BASE_IDX 2 12532 #define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y 0x2f7f 12533 #define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y_BASE_IDX 2 12534 #define regPWRSEQ1_PANEL_PWRSEQ_CNTL 0x2f80 12535 #define regPWRSEQ1_PANEL_PWRSEQ_CNTL_BASE_IDX 2 12536 #define regPWRSEQ1_PANEL_PWRSEQ_STATE 0x2f81 12537 #define regPWRSEQ1_PANEL_PWRSEQ_STATE_BASE_IDX 2 12538 #define regPWRSEQ1_PANEL_PWRSEQ_DELAY1 0x2f82 12539 #define regPWRSEQ1_PANEL_PWRSEQ_DELAY1_BASE_IDX 2 12540 #define regPWRSEQ1_PANEL_PWRSEQ_DELAY2 0x2f83 12541 #define regPWRSEQ1_PANEL_PWRSEQ_DELAY2_BASE_IDX 2 12542 #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1 0x2f84 12543 #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1_BASE_IDX 2 12544 #define regPWRSEQ1_BL_PWM_CNTL 0x2f85 12545 #define regPWRSEQ1_BL_PWM_CNTL_BASE_IDX 2 12546 #define regPWRSEQ1_BL_PWM_CNTL2 0x2f86 12547 #define regPWRSEQ1_BL_PWM_CNTL2_BASE_IDX 2 12548 #define regPWRSEQ1_BL_PWM_PERIOD_CNTL 0x2f87 12549 #define regPWRSEQ1_BL_PWM_PERIOD_CNTL_BASE_IDX 2 12550 #define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK 0x2f88 12551 #define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX 2 12552 #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2 0x2f89 12553 #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2_BASE_IDX 2 12554 #define regPWRSEQ1_PWRSEQ_SPARE 0x2f8d 12555 #define regPWRSEQ1_PWRSEQ_SPARE_BASE_IDX 2 12556 12557 12558 // addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec 12559 // base address: 0x0 12560 #define regDSCC0_DSCC_CONFIG0 0x300a 12561 #define regDSCC0_DSCC_CONFIG0_BASE_IDX 2 12562 #define regDSCC0_DSCC_CONFIG1 0x300b 12563 #define regDSCC0_DSCC_CONFIG1_BASE_IDX 2 12564 #define regDSCC0_DSCC_STATUS 0x300c 12565 #define regDSCC0_DSCC_STATUS_BASE_IDX 2 12566 #define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS 0x300d 12567 #define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 12568 #define regDSCC0_DSCC_PPS_CONFIG0 0x300e 12569 #define regDSCC0_DSCC_PPS_CONFIG0_BASE_IDX 2 12570 #define regDSCC0_DSCC_PPS_CONFIG1 0x300f 12571 #define regDSCC0_DSCC_PPS_CONFIG1_BASE_IDX 2 12572 #define regDSCC0_DSCC_PPS_CONFIG2 0x3010 12573 #define regDSCC0_DSCC_PPS_CONFIG2_BASE_IDX 2 12574 #define regDSCC0_DSCC_PPS_CONFIG3 0x3011 12575 #define regDSCC0_DSCC_PPS_CONFIG3_BASE_IDX 2 12576 #define regDSCC0_DSCC_PPS_CONFIG4 0x3012 12577 #define regDSCC0_DSCC_PPS_CONFIG4_BASE_IDX 2 12578 #define regDSCC0_DSCC_PPS_CONFIG5 0x3013 12579 #define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX 2 12580 #define regDSCC0_DSCC_PPS_CONFIG6 0x3014 12581 #define regDSCC0_DSCC_PPS_CONFIG6_BASE_IDX 2 12582 #define regDSCC0_DSCC_PPS_CONFIG7 0x3015 12583 #define regDSCC0_DSCC_PPS_CONFIG7_BASE_IDX 2 12584 #define regDSCC0_DSCC_PPS_CONFIG8 0x3016 12585 #define regDSCC0_DSCC_PPS_CONFIG8_BASE_IDX 2 12586 #define regDSCC0_DSCC_PPS_CONFIG9 0x3017 12587 #define regDSCC0_DSCC_PPS_CONFIG9_BASE_IDX 2 12588 #define regDSCC0_DSCC_PPS_CONFIG10 0x3018 12589 #define regDSCC0_DSCC_PPS_CONFIG10_BASE_IDX 2 12590 #define regDSCC0_DSCC_PPS_CONFIG11 0x3019 12591 #define regDSCC0_DSCC_PPS_CONFIG11_BASE_IDX 2 12592 #define regDSCC0_DSCC_PPS_CONFIG12 0x301a 12593 #define regDSCC0_DSCC_PPS_CONFIG12_BASE_IDX 2 12594 #define regDSCC0_DSCC_PPS_CONFIG13 0x301b 12595 #define regDSCC0_DSCC_PPS_CONFIG13_BASE_IDX 2 12596 #define regDSCC0_DSCC_PPS_CONFIG14 0x301c 12597 #define regDSCC0_DSCC_PPS_CONFIG14_BASE_IDX 2 12598 #define regDSCC0_DSCC_PPS_CONFIG15 0x301d 12599 #define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX 2 12600 #define regDSCC0_DSCC_PPS_CONFIG16 0x301e 12601 #define regDSCC0_DSCC_PPS_CONFIG16_BASE_IDX 2 12602 #define regDSCC0_DSCC_PPS_CONFIG17 0x301f 12603 #define regDSCC0_DSCC_PPS_CONFIG17_BASE_IDX 2 12604 #define regDSCC0_DSCC_PPS_CONFIG18 0x3020 12605 #define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX 2 12606 #define regDSCC0_DSCC_PPS_CONFIG19 0x3021 12607 #define regDSCC0_DSCC_PPS_CONFIG19_BASE_IDX 2 12608 #define regDSCC0_DSCC_PPS_CONFIG20 0x3022 12609 #define regDSCC0_DSCC_PPS_CONFIG20_BASE_IDX 2 12610 #define regDSCC0_DSCC_PPS_CONFIG21 0x3023 12611 #define regDSCC0_DSCC_PPS_CONFIG21_BASE_IDX 2 12612 #define regDSCC0_DSCC_PPS_CONFIG22 0x3024 12613 #define regDSCC0_DSCC_PPS_CONFIG22_BASE_IDX 2 12614 #define regDSCC0_DSCC_MEM_POWER_CONTROL 0x3025 12615 #define regDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 12616 #define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3026 12617 #define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 12618 #define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3027 12619 #define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 12620 #define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3028 12621 #define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 12622 #define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3029 12623 #define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 12624 #define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER 0x302a 12625 #define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 12626 #define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER 0x302b 12627 #define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 12628 #define regDSCC0_DSCC_MAX_ABS_ERROR0 0x302c 12629 #define regDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 12630 #define regDSCC0_DSCC_MAX_ABS_ERROR1 0x302d 12631 #define regDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 12632 #define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x302e 12633 #define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12634 #define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x302f 12635 #define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12636 #define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3030 12637 #define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12638 #define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3031 12639 #define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12640 #define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3032 12641 #define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12642 #define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3033 12643 #define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12644 #define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3034 12645 #define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12646 #define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3035 12647 #define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12648 #define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE 0x303a 12649 #define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 12650 12651 // addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec 12652 // base address: 0x0 12653 #define regDSCCIF0_DSCCIF_CONFIG0 0x3005 12654 #define regDSCCIF0_DSCCIF_CONFIG0_BASE_IDX 2 12655 #define regDSCCIF0_DSCCIF_CONFIG1 0x3006 12656 #define regDSCCIF0_DSCCIF_CONFIG1_BASE_IDX 2 12657 12658 12659 // addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec 12660 // base address: 0x0 12661 #define regDSC_TOP0_DSC_TOP_CONTROL 0x3000 12662 #define regDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX 2 12663 #define regDSC_TOP0_DSC_DEBUG_CONTROL 0x3001 12664 #define regDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX 2 12665 12666 12667 // addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 12668 // base address: 0xc140 12669 #define regDC_PERFMON19_PERFCOUNTER_CNTL 0x3050 12670 #define regDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX 2 12671 #define regDC_PERFMON19_PERFCOUNTER_CNTL2 0x3051 12672 #define regDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX 2 12673 #define regDC_PERFMON19_PERFCOUNTER_STATE 0x3052 12674 #define regDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX 2 12675 #define regDC_PERFMON19_PERFMON_CNTL 0x3053 12676 #define regDC_PERFMON19_PERFMON_CNTL_BASE_IDX 2 12677 #define regDC_PERFMON19_PERFMON_CNTL2 0x3054 12678 #define regDC_PERFMON19_PERFMON_CNTL2_BASE_IDX 2 12679 #define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC 0x3055 12680 #define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 12681 #define regDC_PERFMON19_PERFMON_CVALUE_LOW 0x3056 12682 #define regDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX 2 12683 #define regDC_PERFMON19_PERFMON_HI 0x3057 12684 #define regDC_PERFMON19_PERFMON_HI_BASE_IDX 2 12685 #define regDC_PERFMON19_PERFMON_LOW 0x3058 12686 #define regDC_PERFMON19_PERFMON_LOW_BASE_IDX 2 12687 12688 12689 // addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec 12690 // base address: 0x170 12691 #define regDSCC1_DSCC_CONFIG0 0x3066 12692 #define regDSCC1_DSCC_CONFIG0_BASE_IDX 2 12693 #define regDSCC1_DSCC_CONFIG1 0x3067 12694 #define regDSCC1_DSCC_CONFIG1_BASE_IDX 2 12695 #define regDSCC1_DSCC_STATUS 0x3068 12696 #define regDSCC1_DSCC_STATUS_BASE_IDX 2 12697 #define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS 0x3069 12698 #define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 12699 #define regDSCC1_DSCC_PPS_CONFIG0 0x306a 12700 #define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX 2 12701 #define regDSCC1_DSCC_PPS_CONFIG1 0x306b 12702 #define regDSCC1_DSCC_PPS_CONFIG1_BASE_IDX 2 12703 #define regDSCC1_DSCC_PPS_CONFIG2 0x306c 12704 #define regDSCC1_DSCC_PPS_CONFIG2_BASE_IDX 2 12705 #define regDSCC1_DSCC_PPS_CONFIG3 0x306d 12706 #define regDSCC1_DSCC_PPS_CONFIG3_BASE_IDX 2 12707 #define regDSCC1_DSCC_PPS_CONFIG4 0x306e 12708 #define regDSCC1_DSCC_PPS_CONFIG4_BASE_IDX 2 12709 #define regDSCC1_DSCC_PPS_CONFIG5 0x306f 12710 #define regDSCC1_DSCC_PPS_CONFIG5_BASE_IDX 2 12711 #define regDSCC1_DSCC_PPS_CONFIG6 0x3070 12712 #define regDSCC1_DSCC_PPS_CONFIG6_BASE_IDX 2 12713 #define regDSCC1_DSCC_PPS_CONFIG7 0x3071 12714 #define regDSCC1_DSCC_PPS_CONFIG7_BASE_IDX 2 12715 #define regDSCC1_DSCC_PPS_CONFIG8 0x3072 12716 #define regDSCC1_DSCC_PPS_CONFIG8_BASE_IDX 2 12717 #define regDSCC1_DSCC_PPS_CONFIG9 0x3073 12718 #define regDSCC1_DSCC_PPS_CONFIG9_BASE_IDX 2 12719 #define regDSCC1_DSCC_PPS_CONFIG10 0x3074 12720 #define regDSCC1_DSCC_PPS_CONFIG10_BASE_IDX 2 12721 #define regDSCC1_DSCC_PPS_CONFIG11 0x3075 12722 #define regDSCC1_DSCC_PPS_CONFIG11_BASE_IDX 2 12723 #define regDSCC1_DSCC_PPS_CONFIG12 0x3076 12724 #define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX 2 12725 #define regDSCC1_DSCC_PPS_CONFIG13 0x3077 12726 #define regDSCC1_DSCC_PPS_CONFIG13_BASE_IDX 2 12727 #define regDSCC1_DSCC_PPS_CONFIG14 0x3078 12728 #define regDSCC1_DSCC_PPS_CONFIG14_BASE_IDX 2 12729 #define regDSCC1_DSCC_PPS_CONFIG15 0x3079 12730 #define regDSCC1_DSCC_PPS_CONFIG15_BASE_IDX 2 12731 #define regDSCC1_DSCC_PPS_CONFIG16 0x307a 12732 #define regDSCC1_DSCC_PPS_CONFIG16_BASE_IDX 2 12733 #define regDSCC1_DSCC_PPS_CONFIG17 0x307b 12734 #define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX 2 12735 #define regDSCC1_DSCC_PPS_CONFIG18 0x307c 12736 #define regDSCC1_DSCC_PPS_CONFIG18_BASE_IDX 2 12737 #define regDSCC1_DSCC_PPS_CONFIG19 0x307d 12738 #define regDSCC1_DSCC_PPS_CONFIG19_BASE_IDX 2 12739 #define regDSCC1_DSCC_PPS_CONFIG20 0x307e 12740 #define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX 2 12741 #define regDSCC1_DSCC_PPS_CONFIG21 0x307f 12742 #define regDSCC1_DSCC_PPS_CONFIG21_BASE_IDX 2 12743 #define regDSCC1_DSCC_PPS_CONFIG22 0x3080 12744 #define regDSCC1_DSCC_PPS_CONFIG22_BASE_IDX 2 12745 #define regDSCC1_DSCC_MEM_POWER_CONTROL 0x3081 12746 #define regDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 12747 #define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3082 12748 #define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 12749 #define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3083 12750 #define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 12751 #define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3084 12752 #define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 12753 #define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3085 12754 #define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 12755 #define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER 0x3086 12756 #define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 12757 #define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3087 12758 #define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 12759 #define regDSCC1_DSCC_MAX_ABS_ERROR0 0x3088 12760 #define regDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 12761 #define regDSCC1_DSCC_MAX_ABS_ERROR1 0x3089 12762 #define regDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 12763 #define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x308a 12764 #define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12765 #define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x308b 12766 #define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12767 #define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x308c 12768 #define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12769 #define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x308d 12770 #define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12771 #define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x308e 12772 #define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12773 #define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x308f 12774 #define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12775 #define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3090 12776 #define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12777 #define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3091 12778 #define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12779 #define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE 0x3096 12780 #define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 12781 12782 12783 // addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec 12784 // base address: 0x170 12785 #define regDSCCIF1_DSCCIF_CONFIG0 0x3061 12786 #define regDSCCIF1_DSCCIF_CONFIG0_BASE_IDX 2 12787 #define regDSCCIF1_DSCCIF_CONFIG1 0x3062 12788 #define regDSCCIF1_DSCCIF_CONFIG1_BASE_IDX 2 12789 12790 12791 // addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec 12792 // base address: 0x170 12793 #define regDSC_TOP1_DSC_TOP_CONTROL 0x305c 12794 #define regDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX 2 12795 #define regDSC_TOP1_DSC_DEBUG_CONTROL 0x305d 12796 #define regDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX 2 12797 12798 12799 // addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 12800 // base address: 0xc2b0 12801 #define regDC_PERFMON20_PERFCOUNTER_CNTL 0x30ac 12802 #define regDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX 2 12803 #define regDC_PERFMON20_PERFCOUNTER_CNTL2 0x30ad 12804 #define regDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX 2 12805 #define regDC_PERFMON20_PERFCOUNTER_STATE 0x30ae 12806 #define regDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX 2 12807 #define regDC_PERFMON20_PERFMON_CNTL 0x30af 12808 #define regDC_PERFMON20_PERFMON_CNTL_BASE_IDX 2 12809 #define regDC_PERFMON20_PERFMON_CNTL2 0x30b0 12810 #define regDC_PERFMON20_PERFMON_CNTL2_BASE_IDX 2 12811 #define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC 0x30b1 12812 #define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 12813 #define regDC_PERFMON20_PERFMON_CVALUE_LOW 0x30b2 12814 #define regDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX 2 12815 #define regDC_PERFMON20_PERFMON_HI 0x30b3 12816 #define regDC_PERFMON20_PERFMON_HI_BASE_IDX 2 12817 #define regDC_PERFMON20_PERFMON_LOW 0x30b4 12818 #define regDC_PERFMON20_PERFMON_LOW_BASE_IDX 2 12819 12820 12821 // addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec 12822 // base address: 0x2e0 12823 #define regDSCC2_DSCC_CONFIG0 0x30c2 12824 #define regDSCC2_DSCC_CONFIG0_BASE_IDX 2 12825 #define regDSCC2_DSCC_CONFIG1 0x30c3 12826 #define regDSCC2_DSCC_CONFIG1_BASE_IDX 2 12827 #define regDSCC2_DSCC_STATUS 0x30c4 12828 #define regDSCC2_DSCC_STATUS_BASE_IDX 2 12829 #define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS 0x30c5 12830 #define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 12831 #define regDSCC2_DSCC_PPS_CONFIG0 0x30c6 12832 #define regDSCC2_DSCC_PPS_CONFIG0_BASE_IDX 2 12833 #define regDSCC2_DSCC_PPS_CONFIG1 0x30c7 12834 #define regDSCC2_DSCC_PPS_CONFIG1_BASE_IDX 2 12835 #define regDSCC2_DSCC_PPS_CONFIG2 0x30c8 12836 #define regDSCC2_DSCC_PPS_CONFIG2_BASE_IDX 2 12837 #define regDSCC2_DSCC_PPS_CONFIG3 0x30c9 12838 #define regDSCC2_DSCC_PPS_CONFIG3_BASE_IDX 2 12839 #define regDSCC2_DSCC_PPS_CONFIG4 0x30ca 12840 #define regDSCC2_DSCC_PPS_CONFIG4_BASE_IDX 2 12841 #define regDSCC2_DSCC_PPS_CONFIG5 0x30cb 12842 #define regDSCC2_DSCC_PPS_CONFIG5_BASE_IDX 2 12843 #define regDSCC2_DSCC_PPS_CONFIG6 0x30cc 12844 #define regDSCC2_DSCC_PPS_CONFIG6_BASE_IDX 2 12845 #define regDSCC2_DSCC_PPS_CONFIG7 0x30cd 12846 #define regDSCC2_DSCC_PPS_CONFIG7_BASE_IDX 2 12847 #define regDSCC2_DSCC_PPS_CONFIG8 0x30ce 12848 #define regDSCC2_DSCC_PPS_CONFIG8_BASE_IDX 2 12849 #define regDSCC2_DSCC_PPS_CONFIG9 0x30cf 12850 #define regDSCC2_DSCC_PPS_CONFIG9_BASE_IDX 2 12851 #define regDSCC2_DSCC_PPS_CONFIG10 0x30d0 12852 #define regDSCC2_DSCC_PPS_CONFIG10_BASE_IDX 2 12853 #define regDSCC2_DSCC_PPS_CONFIG11 0x30d1 12854 #define regDSCC2_DSCC_PPS_CONFIG11_BASE_IDX 2 12855 #define regDSCC2_DSCC_PPS_CONFIG12 0x30d2 12856 #define regDSCC2_DSCC_PPS_CONFIG12_BASE_IDX 2 12857 #define regDSCC2_DSCC_PPS_CONFIG13 0x30d3 12858 #define regDSCC2_DSCC_PPS_CONFIG13_BASE_IDX 2 12859 #define regDSCC2_DSCC_PPS_CONFIG14 0x30d4 12860 #define regDSCC2_DSCC_PPS_CONFIG14_BASE_IDX 2 12861 #define regDSCC2_DSCC_PPS_CONFIG15 0x30d5 12862 #define regDSCC2_DSCC_PPS_CONFIG15_BASE_IDX 2 12863 #define regDSCC2_DSCC_PPS_CONFIG16 0x30d6 12864 #define regDSCC2_DSCC_PPS_CONFIG16_BASE_IDX 2 12865 #define regDSCC2_DSCC_PPS_CONFIG17 0x30d7 12866 #define regDSCC2_DSCC_PPS_CONFIG17_BASE_IDX 2 12867 #define regDSCC2_DSCC_PPS_CONFIG18 0x30d8 12868 #define regDSCC2_DSCC_PPS_CONFIG18_BASE_IDX 2 12869 #define regDSCC2_DSCC_PPS_CONFIG19 0x30d9 12870 #define regDSCC2_DSCC_PPS_CONFIG19_BASE_IDX 2 12871 #define regDSCC2_DSCC_PPS_CONFIG20 0x30da 12872 #define regDSCC2_DSCC_PPS_CONFIG20_BASE_IDX 2 12873 #define regDSCC2_DSCC_PPS_CONFIG21 0x30db 12874 #define regDSCC2_DSCC_PPS_CONFIG21_BASE_IDX 2 12875 #define regDSCC2_DSCC_PPS_CONFIG22 0x30dc 12876 #define regDSCC2_DSCC_PPS_CONFIG22_BASE_IDX 2 12877 #define regDSCC2_DSCC_MEM_POWER_CONTROL 0x30dd 12878 #define regDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 12879 #define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER 0x30de 12880 #define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 12881 #define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER 0x30df 12882 #define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 12883 #define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER 0x30e0 12884 #define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 12885 #define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER 0x30e1 12886 #define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 12887 #define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER 0x30e2 12888 #define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 12889 #define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER 0x30e3 12890 #define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 12891 #define regDSCC2_DSCC_MAX_ABS_ERROR0 0x30e4 12892 #define regDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 12893 #define regDSCC2_DSCC_MAX_ABS_ERROR1 0x30e5 12894 #define regDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 12895 #define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x30e6 12896 #define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12897 #define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x30e7 12898 #define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12899 #define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x30e8 12900 #define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12901 #define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x30e9 12902 #define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12903 #define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x30ea 12904 #define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12905 #define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x30eb 12906 #define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12907 #define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x30ec 12908 #define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12909 #define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x30ed 12910 #define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12911 #define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE 0x30f2 12912 #define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 12913 12914 12915 // addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec 12916 // base address: 0x2e0 12917 #define regDSCCIF2_DSCCIF_CONFIG0 0x30bd 12918 #define regDSCCIF2_DSCCIF_CONFIG0_BASE_IDX 2 12919 #define regDSCCIF2_DSCCIF_CONFIG1 0x30be 12920 #define regDSCCIF2_DSCCIF_CONFIG1_BASE_IDX 2 12921 12922 12923 // addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec 12924 // base address: 0x2e0 12925 #define regDSC_TOP2_DSC_TOP_CONTROL 0x30b8 12926 #define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX 2 12927 #define regDSC_TOP2_DSC_DEBUG_CONTROL 0x30b9 12928 #define regDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX 2 12929 12930 12931 // addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 12932 // base address: 0xc420 12933 #define regDC_PERFMON21_PERFCOUNTER_CNTL 0x3108 12934 #define regDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX 2 12935 #define regDC_PERFMON21_PERFCOUNTER_CNTL2 0x3109 12936 #define regDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX 2 12937 #define regDC_PERFMON21_PERFCOUNTER_STATE 0x310a 12938 #define regDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX 2 12939 #define regDC_PERFMON21_PERFMON_CNTL 0x310b 12940 #define regDC_PERFMON21_PERFMON_CNTL_BASE_IDX 2 12941 #define regDC_PERFMON21_PERFMON_CNTL2 0x310c 12942 #define regDC_PERFMON21_PERFMON_CNTL2_BASE_IDX 2 12943 #define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC 0x310d 12944 #define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 12945 #define regDC_PERFMON21_PERFMON_CVALUE_LOW 0x310e 12946 #define regDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX 2 12947 #define regDC_PERFMON21_PERFMON_HI 0x310f 12948 #define regDC_PERFMON21_PERFMON_HI_BASE_IDX 2 12949 #define regDC_PERFMON21_PERFMON_LOW 0x3110 12950 #define regDC_PERFMON21_PERFMON_LOW_BASE_IDX 2 12951 12952 12953 // addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec 12954 // base address: 0x450 12955 #define regDSCC3_DSCC_CONFIG0 0x311e 12956 #define regDSCC3_DSCC_CONFIG0_BASE_IDX 2 12957 #define regDSCC3_DSCC_CONFIG1 0x311f 12958 #define regDSCC3_DSCC_CONFIG1_BASE_IDX 2 12959 #define regDSCC3_DSCC_STATUS 0x3120 12960 #define regDSCC3_DSCC_STATUS_BASE_IDX 2 12961 #define regDSCC3_DSCC_INTERRUPT_CONTROL_STATUS 0x3121 12962 #define regDSCC3_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 12963 #define regDSCC3_DSCC_PPS_CONFIG0 0x3122 12964 #define regDSCC3_DSCC_PPS_CONFIG0_BASE_IDX 2 12965 #define regDSCC3_DSCC_PPS_CONFIG1 0x3123 12966 #define regDSCC3_DSCC_PPS_CONFIG1_BASE_IDX 2 12967 #define regDSCC3_DSCC_PPS_CONFIG2 0x3124 12968 #define regDSCC3_DSCC_PPS_CONFIG2_BASE_IDX 2 12969 #define regDSCC3_DSCC_PPS_CONFIG3 0x3125 12970 #define regDSCC3_DSCC_PPS_CONFIG3_BASE_IDX 2 12971 #define regDSCC3_DSCC_PPS_CONFIG4 0x3126 12972 #define regDSCC3_DSCC_PPS_CONFIG4_BASE_IDX 2 12973 #define regDSCC3_DSCC_PPS_CONFIG5 0x3127 12974 #define regDSCC3_DSCC_PPS_CONFIG5_BASE_IDX 2 12975 #define regDSCC3_DSCC_PPS_CONFIG6 0x3128 12976 #define regDSCC3_DSCC_PPS_CONFIG6_BASE_IDX 2 12977 #define regDSCC3_DSCC_PPS_CONFIG7 0x3129 12978 #define regDSCC3_DSCC_PPS_CONFIG7_BASE_IDX 2 12979 #define regDSCC3_DSCC_PPS_CONFIG8 0x312a 12980 #define regDSCC3_DSCC_PPS_CONFIG8_BASE_IDX 2 12981 #define regDSCC3_DSCC_PPS_CONFIG9 0x312b 12982 #define regDSCC3_DSCC_PPS_CONFIG9_BASE_IDX 2 12983 #define regDSCC3_DSCC_PPS_CONFIG10 0x312c 12984 #define regDSCC3_DSCC_PPS_CONFIG10_BASE_IDX 2 12985 #define regDSCC3_DSCC_PPS_CONFIG11 0x312d 12986 #define regDSCC3_DSCC_PPS_CONFIG11_BASE_IDX 2 12987 #define regDSCC3_DSCC_PPS_CONFIG12 0x312e 12988 #define regDSCC3_DSCC_PPS_CONFIG12_BASE_IDX 2 12989 #define regDSCC3_DSCC_PPS_CONFIG13 0x312f 12990 #define regDSCC3_DSCC_PPS_CONFIG13_BASE_IDX 2 12991 #define regDSCC3_DSCC_PPS_CONFIG14 0x3130 12992 #define regDSCC3_DSCC_PPS_CONFIG14_BASE_IDX 2 12993 #define regDSCC3_DSCC_PPS_CONFIG15 0x3131 12994 #define regDSCC3_DSCC_PPS_CONFIG15_BASE_IDX 2 12995 #define regDSCC3_DSCC_PPS_CONFIG16 0x3132 12996 #define regDSCC3_DSCC_PPS_CONFIG16_BASE_IDX 2 12997 #define regDSCC3_DSCC_PPS_CONFIG17 0x3133 12998 #define regDSCC3_DSCC_PPS_CONFIG17_BASE_IDX 2 12999 #define regDSCC3_DSCC_PPS_CONFIG18 0x3134 13000 #define regDSCC3_DSCC_PPS_CONFIG18_BASE_IDX 2 13001 #define regDSCC3_DSCC_PPS_CONFIG19 0x3135 13002 #define regDSCC3_DSCC_PPS_CONFIG19_BASE_IDX 2 13003 #define regDSCC3_DSCC_PPS_CONFIG20 0x3136 13004 #define regDSCC3_DSCC_PPS_CONFIG20_BASE_IDX 2 13005 #define regDSCC3_DSCC_PPS_CONFIG21 0x3137 13006 #define regDSCC3_DSCC_PPS_CONFIG21_BASE_IDX 2 13007 #define regDSCC3_DSCC_PPS_CONFIG22 0x3138 13008 #define regDSCC3_DSCC_PPS_CONFIG22_BASE_IDX 2 13009 #define regDSCC3_DSCC_MEM_POWER_CONTROL 0x3139 13010 #define regDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 13011 #define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER 0x313a 13012 #define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 13013 #define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER 0x313b 13014 #define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 13015 #define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER 0x313c 13016 #define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 13017 #define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER 0x313d 13018 #define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 13019 #define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER 0x313e 13020 #define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 13021 #define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER 0x313f 13022 #define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 13023 #define regDSCC3_DSCC_MAX_ABS_ERROR0 0x3140 13024 #define regDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 13025 #define regDSCC3_DSCC_MAX_ABS_ERROR1 0x3141 13026 #define regDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 13027 #define regDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x3142 13028 #define regDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 13029 #define regDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x3143 13030 #define regDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 13031 #define regDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3144 13032 #define regDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 13033 #define regDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3145 13034 #define regDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 13035 #define regDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3146 13036 #define regDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 13037 #define regDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3147 13038 #define regDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 13039 #define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3148 13040 #define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 13041 #define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3149 13042 #define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 13043 #define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE 0x314e 13044 #define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 13045 13046 13047 // addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec 13048 // base address: 0x450 13049 #define regDSCCIF3_DSCCIF_CONFIG0 0x3119 13050 #define regDSCCIF3_DSCCIF_CONFIG0_BASE_IDX 2 13051 #define regDSCCIF3_DSCCIF_CONFIG1 0x311a 13052 #define regDSCCIF3_DSCCIF_CONFIG1_BASE_IDX 2 13053 13054 13055 // addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec 13056 // base address: 0x450 13057 #define regDSC_TOP3_DSC_TOP_CONTROL 0x3114 13058 #define regDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX 2 13059 #define regDSC_TOP3_DSC_DEBUG_CONTROL 0x3115 13060 #define regDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX 2 13061 13062 13063 // addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 13064 // base address: 0xc590 13065 #define regDC_PERFMON22_PERFCOUNTER_CNTL 0x3164 13066 #define regDC_PERFMON22_PERFCOUNTER_CNTL_BASE_IDX 2 13067 #define regDC_PERFMON22_PERFCOUNTER_CNTL2 0x3165 13068 #define regDC_PERFMON22_PERFCOUNTER_CNTL2_BASE_IDX 2 13069 #define regDC_PERFMON22_PERFCOUNTER_STATE 0x3166 13070 #define regDC_PERFMON22_PERFCOUNTER_STATE_BASE_IDX 2 13071 #define regDC_PERFMON22_PERFMON_CNTL 0x3167 13072 #define regDC_PERFMON22_PERFMON_CNTL_BASE_IDX 2 13073 #define regDC_PERFMON22_PERFMON_CNTL2 0x3168 13074 #define regDC_PERFMON22_PERFMON_CNTL2_BASE_IDX 2 13075 #define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC 0x3169 13076 #define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 13077 #define regDC_PERFMON22_PERFMON_CVALUE_LOW 0x316a 13078 #define regDC_PERFMON22_PERFMON_CVALUE_LOW_BASE_IDX 2 13079 #define regDC_PERFMON22_PERFMON_HI 0x316b 13080 #define regDC_PERFMON22_PERFMON_HI_BASE_IDX 2 13081 #define regDC_PERFMON22_PERFMON_LOW 0x316c 13082 #define regDC_PERFMON22_PERFMON_LOW_BASE_IDX 2 13083 13084 13085 // addressBlock: dce_dc_hpo_hpo_top_dispdec 13086 // base address: 0x2790c 13087 #define regHPO_TOP_CLOCK_CONTROL 0x0e43 13088 #define regHPO_TOP_CLOCK_CONTROL_BASE_IDX 3 13089 #define regHPO_TOP_HW_CONTROL 0x0e4a 13090 #define regHPO_TOP_HW_CONTROL_BASE_IDX 3 13091 13092 13093 // addressBlock: dce_dc_hpo_dp_stream_mapper_dispdec 13094 // base address: 0x27958 13095 #define regDP_STREAM_MAPPER_CONTROL0 0x0e56 13096 #define regDP_STREAM_MAPPER_CONTROL0_BASE_IDX 3 13097 #define regDP_STREAM_MAPPER_CONTROL1 0x0e57 13098 #define regDP_STREAM_MAPPER_CONTROL1_BASE_IDX 3 13099 #define regDP_STREAM_MAPPER_CONTROL2 0x0e58 13100 #define regDP_STREAM_MAPPER_CONTROL2_BASE_IDX 3 13101 #define regDP_STREAM_MAPPER_CONTROL3 0x0e59 13102 #define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX 3 13103 13104 13105 // addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec 13106 // base address: 0x1a698 13107 #define regDC_PERFMON23_PERFCOUNTER_CNTL 0x0e66 13108 #define regDC_PERFMON23_PERFCOUNTER_CNTL_BASE_IDX 3 13109 #define regDC_PERFMON23_PERFCOUNTER_CNTL2 0x0e67 13110 #define regDC_PERFMON23_PERFCOUNTER_CNTL2_BASE_IDX 3 13111 #define regDC_PERFMON23_PERFCOUNTER_STATE 0x0e68 13112 #define regDC_PERFMON23_PERFCOUNTER_STATE_BASE_IDX 3 13113 #define regDC_PERFMON23_PERFMON_CNTL 0x0e69 13114 #define regDC_PERFMON23_PERFMON_CNTL_BASE_IDX 3 13115 #define regDC_PERFMON23_PERFMON_CNTL2 0x0e6a 13116 #define regDC_PERFMON23_PERFMON_CNTL2_BASE_IDX 3 13117 #define regDC_PERFMON23_PERFMON_CVALUE_INT_MISC 0x0e6b 13118 #define regDC_PERFMON23_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 13119 #define regDC_PERFMON23_PERFMON_CVALUE_LOW 0x0e6c 13120 #define regDC_PERFMON23_PERFMON_CVALUE_LOW_BASE_IDX 3 13121 #define regDC_PERFMON23_PERFMON_HI 0x0e6d 13122 #define regDC_PERFMON23_PERFMON_HI_BASE_IDX 3 13123 #define regDC_PERFMON23_PERFMON_LOW 0x0e6e 13124 #define regDC_PERFMON23_PERFMON_LOW_BASE_IDX 3 13125 13126 13127 // addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec 13128 // base address: 0x2656c 13129 #define regHDMI_LINK_ENC_CONTROL 0x095b 13130 #define regHDMI_LINK_ENC_CONTROL_BASE_IDX 3 13131 #define regHDMI_LINK_ENC_CLK_CTRL 0x095c 13132 #define regHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3 13133 13134 13135 // addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec 13136 // base address: 0x26594 13137 #define regHDMI_FRL_ENC_CONFIG 0x0965 13138 #define regHDMI_FRL_ENC_CONFIG_BASE_IDX 3 13139 #define regHDMI_FRL_ENC_CONFIG2 0x0966 13140 #define regHDMI_FRL_ENC_CONFIG2_BASE_IDX 3 13141 #define regHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967 13142 #define regHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3 13143 #define regHDMI_FRL_ENC_MEM_CTRL 0x0968 13144 #define regHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3 13145 13146 13147 // addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec 13148 // base address: 0x2634c 13149 #define regHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 13150 #define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 13151 #define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 13152 #define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 13153 #define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 13154 #define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 13155 #define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 13156 #define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 13157 #define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 13158 #define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 13159 13160 13161 // addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec 13162 // base address: 0x2646c 13163 #define regAFMT5_AFMT_ACP 0x091b 13164 #define regAFMT5_AFMT_ACP_BASE_IDX 3 13165 #define regAFMT5_AFMT_VBI_PACKET_CONTROL 0x091c 13166 #define regAFMT5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 3 13167 #define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2 0x091d 13168 #define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 3 13169 #define regAFMT5_AFMT_AUDIO_INFO0 0x091e 13170 #define regAFMT5_AFMT_AUDIO_INFO0_BASE_IDX 3 13171 #define regAFMT5_AFMT_AUDIO_INFO1 0x091f 13172 #define regAFMT5_AFMT_AUDIO_INFO1_BASE_IDX 3 13173 #define regAFMT5_AFMT_60958_0 0x0920 13174 #define regAFMT5_AFMT_60958_0_BASE_IDX 3 13175 #define regAFMT5_AFMT_60958_1 0x0921 13176 #define regAFMT5_AFMT_60958_1_BASE_IDX 3 13177 #define regAFMT5_AFMT_AUDIO_CRC_CONTROL 0x0922 13178 #define regAFMT5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 3 13179 #define regAFMT5_AFMT_RAMP_CONTROL0 0x0923 13180 #define regAFMT5_AFMT_RAMP_CONTROL0_BASE_IDX 3 13181 #define regAFMT5_AFMT_RAMP_CONTROL1 0x0924 13182 #define regAFMT5_AFMT_RAMP_CONTROL1_BASE_IDX 3 13183 #define regAFMT5_AFMT_RAMP_CONTROL2 0x0925 13184 #define regAFMT5_AFMT_RAMP_CONTROL2_BASE_IDX 3 13185 #define regAFMT5_AFMT_RAMP_CONTROL3 0x0926 13186 #define regAFMT5_AFMT_RAMP_CONTROL3_BASE_IDX 3 13187 #define regAFMT5_AFMT_60958_2 0x0927 13188 #define regAFMT5_AFMT_60958_2_BASE_IDX 3 13189 #define regAFMT5_AFMT_AUDIO_CRC_RESULT 0x0928 13190 #define regAFMT5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 3 13191 #define regAFMT5_AFMT_STATUS 0x0929 13192 #define regAFMT5_AFMT_STATUS_BASE_IDX 3 13193 #define regAFMT5_AFMT_AUDIO_PACKET_CONTROL 0x092a 13194 #define regAFMT5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 3 13195 #define regAFMT5_AFMT_INFOFRAME_CONTROL0 0x092b 13196 #define regAFMT5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 3 13197 #define regAFMT5_AFMT_INTERRUPT_STATUS 0x092c 13198 #define regAFMT5_AFMT_INTERRUPT_STATUS_BASE_IDX 3 13199 #define regAFMT5_AFMT_AUDIO_SRC_CONTROL 0x092d 13200 #define regAFMT5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 3 13201 #define regAFMT5_AFMT_MEM_PWR 0x092f 13202 #define regAFMT5_AFMT_MEM_PWR_BASE_IDX 3 13203 13204 13205 // addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec 13206 // base address: 0x264f0 13207 #define regDME5_DME_CONTROL 0x093c 13208 #define regDME5_DME_CONTROL_BASE_IDX 3 13209 #define regDME5_DME_MEMORY_CONTROL 0x093d 13210 #define regDME5_DME_MEMORY_CONTROL_BASE_IDX 3 13211 13212 13213 // addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec 13214 // base address: 0x264c4 13215 #define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL 0x0931 13216 #define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 3 13217 #define regVPG5_VPG_GENERIC_PACKET_DATA 0x0932 13218 #define regVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX 3 13219 #define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL 0x0933 13220 #define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 3 13221 #define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x0934 13222 #define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 3 13223 #define regVPG5_VPG_GENERIC_STATUS 0x0935 13224 #define regVPG5_VPG_GENERIC_STATUS_BASE_IDX 3 13225 #define regVPG5_VPG_MEM_PWR 0x0936 13226 #define regVPG5_VPG_MEM_PWR_BASE_IDX 3 13227 #define regVPG5_VPG_ISRC1_2_ACCESS_CTRL 0x0937 13228 #define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 3 13229 #define regVPG5_VPG_ISRC1_2_DATA 0x0938 13230 #define regVPG5_VPG_ISRC1_2_DATA_BASE_IDX 3 13231 #define regVPG5_VPG_MPEG_INFO0 0x0939 13232 #define regVPG5_VPG_MPEG_INFO0_BASE_IDX 3 13233 #define regVPG5_VPG_MPEG_INFO1 0x093a 13234 #define regVPG5_VPG_MPEG_INFO1_BASE_IDX 3 13235 13236 13237 // addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec 13238 // base address: 0x2637c 13239 #define regHDMI_TB_ENC_CONTROL 0x08df 13240 #define regHDMI_TB_ENC_CONTROL_BASE_IDX 3 13241 #define regHDMI_TB_ENC_PIXEL_FORMAT 0x08e0 13242 #define regHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3 13243 #define regHDMI_TB_ENC_PACKET_CONTROL 0x08e1 13244 #define regHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3 13245 #define regHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2 13246 #define regHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3 13247 #define regHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3 13248 #define regHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3 13249 #define regHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4 13250 #define regHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3 13251 #define regHDMI_TB_ENC_GC_CONTROL 0x08e5 13252 #define regHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3 13253 #define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6 13254 #define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3 13255 #define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7 13256 #define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3 13257 #define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8 13258 #define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3 13259 #define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9 13260 #define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3 13261 #define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea 13262 #define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3 13263 #define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb 13264 #define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3 13265 #define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec 13266 #define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3 13267 #define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed 13268 #define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3 13269 #define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee 13270 #define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3 13271 #define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef 13272 #define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3 13273 #define regHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0 13274 #define regHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3 13275 #define regHDMI_TB_ENC_DB_CONTROL 0x08f1 13276 #define regHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3 13277 #define regHDMI_TB_ENC_ACR_32_0 0x08f2 13278 #define regHDMI_TB_ENC_ACR_32_0_BASE_IDX 3 13279 #define regHDMI_TB_ENC_ACR_32_1 0x08f3 13280 #define regHDMI_TB_ENC_ACR_32_1_BASE_IDX 3 13281 #define regHDMI_TB_ENC_ACR_44_0 0x08f4 13282 #define regHDMI_TB_ENC_ACR_44_0_BASE_IDX 3 13283 #define regHDMI_TB_ENC_ACR_44_1 0x08f5 13284 #define regHDMI_TB_ENC_ACR_44_1_BASE_IDX 3 13285 #define regHDMI_TB_ENC_ACR_48_0 0x08f6 13286 #define regHDMI_TB_ENC_ACR_48_0_BASE_IDX 3 13287 #define regHDMI_TB_ENC_ACR_48_1 0x08f7 13288 #define regHDMI_TB_ENC_ACR_48_1_BASE_IDX 3 13289 #define regHDMI_TB_ENC_ACR_STATUS_0 0x08f8 13290 #define regHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3 13291 #define regHDMI_TB_ENC_ACR_STATUS_1 0x08f9 13292 #define regHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3 13293 #define regHDMI_TB_ENC_BUFFER_CONTROL 0x08fb 13294 #define regHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3 13295 #define regHDMI_TB_ENC_MEM_CTRL 0x08fe 13296 #define regHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3 13297 #define regHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff 13298 #define regHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3 13299 #define regHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900 13300 #define regHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3 13301 #define regHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901 13302 #define regHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3 13303 #define regHDMI_TB_ENC_CRC_CNTL 0x0903 13304 #define regHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3 13305 #define regHDMI_TB_ENC_CRC_RESULT_0 0x0904 13306 #define regHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3 13307 #define regHDMI_TB_ENC_ENCRYPTION_CONTROL 0x0907 13308 #define regHDMI_TB_ENC_ENCRYPTION_CONTROL_BASE_IDX 3 13309 #define regHDMI_TB_ENC_MODE 0x0908 13310 #define regHDMI_TB_ENC_MODE_BASE_IDX 3 13311 #define regHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909 13312 #define regHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3 13313 #define regHDMI_TB_ENC_CRC_RESULT_1 0x090a 13314 #define regHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3 13315 13316 13317 // addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec 13318 // base address: 0x1ab8c 13319 #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL 0x3623 13320 #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 13321 #define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x3624 13322 #define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 13323 #define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL 0x3625 13324 #define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 13325 #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x3626 13326 #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 13327 #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x3627 13328 #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 13329 #define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE 0x3628 13330 #define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE_BASE_IDX 2 13331 13332 13333 // addressBlock: dce_dc_hpo_dp_stream_enc0_apg_apg_dispdec 13334 // base address: 0x1abc0 13335 #define regAPG0_APG_CONTROL 0x3630 13336 #define regAPG0_APG_CONTROL_BASE_IDX 2 13337 #define regAPG0_APG_CONTROL2 0x3631 13338 #define regAPG0_APG_CONTROL2_BASE_IDX 2 13339 #define regAPG0_APG_DBG_GEN_CONTROL 0x3632 13340 #define regAPG0_APG_DBG_GEN_CONTROL_BASE_IDX 2 13341 #define regAPG0_APG_PACKET_CONTROL 0x3633 13342 #define regAPG0_APG_PACKET_CONTROL_BASE_IDX 2 13343 #define regAPG0_APG_AUDIO_CRC_CONTROL 0x363a 13344 #define regAPG0_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 13345 #define regAPG0_APG_AUDIO_CRC_CONTROL2 0x363b 13346 #define regAPG0_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 13347 #define regAPG0_APG_AUDIO_CRC_RESULT 0x363c 13348 #define regAPG0_APG_AUDIO_CRC_RESULT_BASE_IDX 2 13349 #define regAPG0_APG_STATUS 0x3641 13350 #define regAPG0_APG_STATUS_BASE_IDX 2 13351 #define regAPG0_APG_STATUS2 0x3642 13352 #define regAPG0_APG_STATUS2_BASE_IDX 2 13353 #define regAPG0_APG_MEM_PWR 0x3644 13354 #define regAPG0_APG_MEM_PWR_BASE_IDX 2 13355 #define regAPG0_APG_SPARE 0x3646 13356 #define regAPG0_APG_SPARE_BASE_IDX 2 13357 13358 13359 // addressBlock: dce_dc_hpo_dp_stream_enc0_dme_dme_dispdec 13360 // base address: 0x1ac38 13361 #define regDME6_DME_CONTROL 0x364e 13362 #define regDME6_DME_CONTROL_BASE_IDX 2 13363 #define regDME6_DME_MEMORY_CONTROL 0x364f 13364 #define regDME6_DME_MEMORY_CONTROL_BASE_IDX 2 13365 13366 13367 // addressBlock: dce_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec 13368 // base address: 0x1ac44 13369 #define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3651 13370 #define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 13371 #define regVPG6_VPG_GENERIC_PACKET_DATA 0x3652 13372 #define regVPG6_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 13373 #define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL 0x3653 13374 #define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 13375 #define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3654 13376 #define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 13377 #define regVPG6_VPG_GENERIC_STATUS 0x3655 13378 #define regVPG6_VPG_GENERIC_STATUS_BASE_IDX 2 13379 #define regVPG6_VPG_MEM_PWR 0x3656 13380 #define regVPG6_VPG_MEM_PWR_BASE_IDX 2 13381 #define regVPG6_VPG_ISRC1_2_ACCESS_CTRL 0x3657 13382 #define regVPG6_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 13383 #define regVPG6_VPG_ISRC1_2_DATA 0x3658 13384 #define regVPG6_VPG_ISRC1_2_DATA_BASE_IDX 2 13385 #define regVPG6_VPG_MPEG_INFO0 0x3659 13386 #define regVPG6_VPG_MPEG_INFO0_BASE_IDX 2 13387 #define regVPG6_VPG_MPEG_INFO1 0x365a 13388 #define regVPG6_VPG_MPEG_INFO1_BASE_IDX 2 13389 13390 13391 // addressBlock: dce_dc_hpo_dp_sym32_enc0_dispdec 13392 // base address: 0x1ac74 13393 #define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL 0x365d 13394 #define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX 2 13395 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL 0x365e 13396 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 13397 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x365f 13398 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13399 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3660 13400 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13401 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3661 13402 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 13403 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0 0x3662 13404 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 13405 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1 0x3663 13406 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 13407 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2 0x3664 13408 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 13409 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3 0x3665 13410 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 13411 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4 0x3666 13412 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 13413 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5 0x3667 13414 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 13415 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6 0x3668 13416 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 13417 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7 0x3669 13418 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 13419 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8 0x366a 13420 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 13421 #define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL 0x366b 13422 #define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 13423 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x366c 13424 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 13425 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x366d 13426 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 13427 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x366e 13428 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 13429 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x366f 13430 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 13431 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3670 13432 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 13433 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3671 13434 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 13435 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3672 13436 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 13437 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3673 13438 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 13439 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3674 13440 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 13441 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3675 13442 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 13443 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x3676 13444 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 13445 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x3677 13446 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 13447 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3678 13448 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 13449 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3679 13450 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 13451 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x367a 13452 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 13453 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL 0x367b 13454 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 13455 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x367c 13456 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 13457 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x367d 13458 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 13459 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x367e 13460 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 13461 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL 0x3683 13462 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 13463 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL 0x3684 13464 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 13465 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3685 13466 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 13467 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3686 13468 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 13469 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL 0x3687 13470 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 13471 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0 0x3688 13472 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 13473 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1 0x3689 13474 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 13475 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS 0x368a 13476 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 13477 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS 0x368b 13478 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX 2 13479 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL 0x368c 13480 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX 2 13481 #define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL 0x368d 13482 #define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 13483 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE 0x368e 13484 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE_BASE_IDX 2 13485 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT2 0x3693 13486 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT2_BASE_IDX 2 13487 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT3 0x3694 13488 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT3_BASE_IDX 2 13489 13490 13491 // addressBlock: dce_dc_hpo_dp_stream_enc1_dispdec 13492 // base address: 0x1aedc 13493 #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL 0x36f7 13494 #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 13495 #define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x36f8 13496 #define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 13497 #define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL 0x36f9 13498 #define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 13499 #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x36fa 13500 #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 13501 #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x36fb 13502 #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 13503 #define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE 0x36fc 13504 #define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE_BASE_IDX 2 13505 13506 13507 // addressBlock: dce_dc_hpo_dp_stream_enc1_apg_apg_dispdec 13508 // base address: 0x1af10 13509 #define regAPG1_APG_CONTROL 0x3704 13510 #define regAPG1_APG_CONTROL_BASE_IDX 2 13511 #define regAPG1_APG_CONTROL2 0x3705 13512 #define regAPG1_APG_CONTROL2_BASE_IDX 2 13513 #define regAPG1_APG_DBG_GEN_CONTROL 0x3706 13514 #define regAPG1_APG_DBG_GEN_CONTROL_BASE_IDX 2 13515 #define regAPG1_APG_PACKET_CONTROL 0x3707 13516 #define regAPG1_APG_PACKET_CONTROL_BASE_IDX 2 13517 #define regAPG1_APG_AUDIO_CRC_CONTROL 0x370e 13518 #define regAPG1_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 13519 #define regAPG1_APG_AUDIO_CRC_CONTROL2 0x370f 13520 #define regAPG1_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 13521 #define regAPG1_APG_AUDIO_CRC_RESULT 0x3710 13522 #define regAPG1_APG_AUDIO_CRC_RESULT_BASE_IDX 2 13523 #define regAPG1_APG_STATUS 0x3715 13524 #define regAPG1_APG_STATUS_BASE_IDX 2 13525 #define regAPG1_APG_STATUS2 0x3716 13526 #define regAPG1_APG_STATUS2_BASE_IDX 2 13527 #define regAPG1_APG_MEM_PWR 0x3718 13528 #define regAPG1_APG_MEM_PWR_BASE_IDX 2 13529 #define regAPG1_APG_SPARE 0x371a 13530 #define regAPG1_APG_SPARE_BASE_IDX 2 13531 13532 13533 // addressBlock: dce_dc_hpo_dp_stream_enc1_dme_dme_dispdec 13534 // base address: 0x1af88 13535 #define regDME7_DME_CONTROL 0x3722 13536 #define regDME7_DME_CONTROL_BASE_IDX 2 13537 #define regDME7_DME_MEMORY_CONTROL 0x3723 13538 #define regDME7_DME_MEMORY_CONTROL_BASE_IDX 2 13539 13540 13541 // addressBlock: dce_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec 13542 // base address: 0x1af94 13543 #define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3725 13544 #define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 13545 #define regVPG7_VPG_GENERIC_PACKET_DATA 0x3726 13546 #define regVPG7_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 13547 #define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL 0x3727 13548 #define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 13549 #define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3728 13550 #define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 13551 #define regVPG7_VPG_GENERIC_STATUS 0x3729 13552 #define regVPG7_VPG_GENERIC_STATUS_BASE_IDX 2 13553 #define regVPG7_VPG_MEM_PWR 0x372a 13554 #define regVPG7_VPG_MEM_PWR_BASE_IDX 2 13555 #define regVPG7_VPG_ISRC1_2_ACCESS_CTRL 0x372b 13556 #define regVPG7_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 13557 #define regVPG7_VPG_ISRC1_2_DATA 0x372c 13558 #define regVPG7_VPG_ISRC1_2_DATA_BASE_IDX 2 13559 #define regVPG7_VPG_MPEG_INFO0 0x372d 13560 #define regVPG7_VPG_MPEG_INFO0_BASE_IDX 2 13561 #define regVPG7_VPG_MPEG_INFO1 0x372e 13562 #define regVPG7_VPG_MPEG_INFO1_BASE_IDX 2 13563 13564 13565 // addressBlock: dce_dc_hpo_dp_sym32_enc1_dispdec 13566 // base address: 0x1afc4 13567 #define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL 0x3731 13568 #define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL_BASE_IDX 2 13569 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3732 13570 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 13571 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3733 13572 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13573 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3734 13574 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13575 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3735 13576 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 13577 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0 0x3736 13578 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 13579 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1 0x3737 13580 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 13581 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2 0x3738 13582 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 13583 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3 0x3739 13584 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 13585 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4 0x373a 13586 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 13587 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5 0x373b 13588 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 13589 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6 0x373c 13590 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 13591 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7 0x373d 13592 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 13593 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8 0x373e 13594 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 13595 #define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL 0x373f 13596 #define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 13597 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3740 13598 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 13599 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3741 13600 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 13601 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3742 13602 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 13603 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3743 13604 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 13605 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3744 13606 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 13607 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3745 13608 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 13609 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3746 13610 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 13611 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3747 13612 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 13613 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3748 13614 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 13615 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3749 13616 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 13617 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x374a 13618 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 13619 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x374b 13620 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 13621 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x374c 13622 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 13623 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x374d 13624 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 13625 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x374e 13626 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 13627 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL 0x374f 13628 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 13629 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3750 13630 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 13631 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3751 13632 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 13633 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3752 13634 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 13635 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL 0x3757 13636 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 13637 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL 0x3758 13638 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 13639 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3759 13640 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 13641 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x375a 13642 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 13643 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL 0x375b 13644 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 13645 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0 0x375c 13646 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 13647 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1 0x375d 13648 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 13649 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS 0x375e 13650 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 13651 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS 0x375f 13652 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX 2 13653 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL 0x3760 13654 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX 2 13655 #define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3761 13656 #define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 13657 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE 0x3762 13658 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE_BASE_IDX 2 13659 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT2 0x3767 13660 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT2_BASE_IDX 2 13661 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT3 0x3768 13662 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT3_BASE_IDX 2 13663 13664 13665 // addressBlock: dce_dc_hpo_dp_stream_enc2_dispdec 13666 // base address: 0x1b22c 13667 #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL 0x37cb 13668 #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 13669 #define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x37cc 13670 #define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 13671 #define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL 0x37cd 13672 #define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 13673 #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x37ce 13674 #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 13675 #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x37cf 13676 #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 13677 #define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE 0x37d0 13678 #define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE_BASE_IDX 2 13679 13680 13681 // addressBlock: dce_dc_hpo_dp_stream_enc2_apg_apg_dispdec 13682 // base address: 0x1b260 13683 #define regAPG2_APG_CONTROL 0x37d8 13684 #define regAPG2_APG_CONTROL_BASE_IDX 2 13685 #define regAPG2_APG_CONTROL2 0x37d9 13686 #define regAPG2_APG_CONTROL2_BASE_IDX 2 13687 #define regAPG2_APG_DBG_GEN_CONTROL 0x37da 13688 #define regAPG2_APG_DBG_GEN_CONTROL_BASE_IDX 2 13689 #define regAPG2_APG_PACKET_CONTROL 0x37db 13690 #define regAPG2_APG_PACKET_CONTROL_BASE_IDX 2 13691 #define regAPG2_APG_AUDIO_CRC_CONTROL 0x37e2 13692 #define regAPG2_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 13693 #define regAPG2_APG_AUDIO_CRC_CONTROL2 0x37e3 13694 #define regAPG2_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 13695 #define regAPG2_APG_AUDIO_CRC_RESULT 0x37e4 13696 #define regAPG2_APG_AUDIO_CRC_RESULT_BASE_IDX 2 13697 #define regAPG2_APG_STATUS 0x37e9 13698 #define regAPG2_APG_STATUS_BASE_IDX 2 13699 #define regAPG2_APG_STATUS2 0x37ea 13700 #define regAPG2_APG_STATUS2_BASE_IDX 2 13701 #define regAPG2_APG_MEM_PWR 0x37ec 13702 #define regAPG2_APG_MEM_PWR_BASE_IDX 2 13703 #define regAPG2_APG_SPARE 0x37ee 13704 #define regAPG2_APG_SPARE_BASE_IDX 2 13705 13706 13707 // addressBlock: dce_dc_hpo_dp_stream_enc2_dme_dme_dispdec 13708 // base address: 0x1b2d8 13709 #define regDME8_DME_CONTROL 0x37f6 13710 #define regDME8_DME_CONTROL_BASE_IDX 2 13711 #define regDME8_DME_MEMORY_CONTROL 0x37f7 13712 #define regDME8_DME_MEMORY_CONTROL_BASE_IDX 2 13713 13714 13715 // addressBlock: dce_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec 13716 // base address: 0x1b2e4 13717 #define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL 0x37f9 13718 #define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 13719 #define regVPG8_VPG_GENERIC_PACKET_DATA 0x37fa 13720 #define regVPG8_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 13721 #define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL 0x37fb 13722 #define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 13723 #define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x37fc 13724 #define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 13725 #define regVPG8_VPG_GENERIC_STATUS 0x37fd 13726 #define regVPG8_VPG_GENERIC_STATUS_BASE_IDX 2 13727 #define regVPG8_VPG_MEM_PWR 0x37fe 13728 #define regVPG8_VPG_MEM_PWR_BASE_IDX 2 13729 #define regVPG8_VPG_ISRC1_2_ACCESS_CTRL 0x37ff 13730 #define regVPG8_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 13731 #define regVPG8_VPG_ISRC1_2_DATA 0x3800 13732 #define regVPG8_VPG_ISRC1_2_DATA_BASE_IDX 2 13733 #define regVPG8_VPG_MPEG_INFO0 0x3801 13734 #define regVPG8_VPG_MPEG_INFO0_BASE_IDX 2 13735 #define regVPG8_VPG_MPEG_INFO1 0x3802 13736 #define regVPG8_VPG_MPEG_INFO1_BASE_IDX 2 13737 13738 13739 // addressBlock: dce_dc_hpo_dp_sym32_enc2_dispdec 13740 // base address: 0x1b314 13741 #define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL 0x3805 13742 #define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL_BASE_IDX 2 13743 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3806 13744 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 13745 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3807 13746 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13747 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3808 13748 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13749 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3809 13750 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 13751 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0 0x380a 13752 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 13753 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1 0x380b 13754 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 13755 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2 0x380c 13756 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 13757 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3 0x380d 13758 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 13759 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4 0x380e 13760 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 13761 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5 0x380f 13762 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 13763 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6 0x3810 13764 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 13765 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7 0x3811 13766 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 13767 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8 0x3812 13768 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 13769 #define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL 0x3813 13770 #define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 13771 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3814 13772 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 13773 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3815 13774 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 13775 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3816 13776 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 13777 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3817 13778 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 13779 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3818 13780 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 13781 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3819 13782 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 13783 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x381a 13784 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 13785 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x381b 13786 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 13787 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x381c 13788 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 13789 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x381d 13790 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 13791 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x381e 13792 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 13793 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x381f 13794 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 13795 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3820 13796 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 13797 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3821 13798 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 13799 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x3822 13800 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 13801 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL 0x3823 13802 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 13803 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3824 13804 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 13805 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3825 13806 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 13807 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3826 13808 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 13809 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL 0x382b 13810 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 13811 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL 0x382c 13812 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 13813 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL 0x382d 13814 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 13815 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x382e 13816 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 13817 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL 0x382f 13818 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 13819 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0 0x3830 13820 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 13821 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1 0x3831 13822 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 13823 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS 0x3832 13824 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 13825 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS 0x3833 13826 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX 2 13827 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL 0x3834 13828 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX 2 13829 #define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3835 13830 #define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 13831 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE 0x3836 13832 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE_BASE_IDX 2 13833 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT2 0x383b 13834 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT2_BASE_IDX 2 13835 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT3 0x383c 13836 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT3_BASE_IDX 2 13837 13838 13839 // addressBlock: dce_dc_hpo_dp_stream_enc3_dispdec 13840 // base address: 0x1b57c 13841 #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL 0x389f 13842 #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 13843 #define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x38a0 13844 #define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 13845 #define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL 0x38a1 13846 #define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 13847 #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x38a2 13848 #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 13849 #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x38a3 13850 #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 13851 #define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE 0x38a4 13852 #define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE_BASE_IDX 2 13853 13854 13855 // addressBlock: dce_dc_hpo_dp_stream_enc3_apg_apg_dispdec 13856 // base address: 0x1b5b0 13857 #define regAPG3_APG_CONTROL 0x38ac 13858 #define regAPG3_APG_CONTROL_BASE_IDX 2 13859 #define regAPG3_APG_CONTROL2 0x38ad 13860 #define regAPG3_APG_CONTROL2_BASE_IDX 2 13861 #define regAPG3_APG_DBG_GEN_CONTROL 0x38ae 13862 #define regAPG3_APG_DBG_GEN_CONTROL_BASE_IDX 2 13863 #define regAPG3_APG_PACKET_CONTROL 0x38af 13864 #define regAPG3_APG_PACKET_CONTROL_BASE_IDX 2 13865 #define regAPG3_APG_AUDIO_CRC_CONTROL 0x38b6 13866 #define regAPG3_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 13867 #define regAPG3_APG_AUDIO_CRC_CONTROL2 0x38b7 13868 #define regAPG3_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 13869 #define regAPG3_APG_AUDIO_CRC_RESULT 0x38b8 13870 #define regAPG3_APG_AUDIO_CRC_RESULT_BASE_IDX 2 13871 #define regAPG3_APG_STATUS 0x38bd 13872 #define regAPG3_APG_STATUS_BASE_IDX 2 13873 #define regAPG3_APG_STATUS2 0x38be 13874 #define regAPG3_APG_STATUS2_BASE_IDX 2 13875 #define regAPG3_APG_MEM_PWR 0x38c0 13876 #define regAPG3_APG_MEM_PWR_BASE_IDX 2 13877 #define regAPG3_APG_SPARE 0x38c2 13878 #define regAPG3_APG_SPARE_BASE_IDX 2 13879 13880 13881 // addressBlock: dce_dc_hpo_dp_stream_enc3_dme_dme_dispdec 13882 // base address: 0x1b628 13883 #define regDME9_DME_CONTROL 0x38ca 13884 #define regDME9_DME_CONTROL_BASE_IDX 2 13885 #define regDME9_DME_MEMORY_CONTROL 0x38cb 13886 #define regDME9_DME_MEMORY_CONTROL_BASE_IDX 2 13887 13888 13889 // addressBlock: dce_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec 13890 // base address: 0x1b634 13891 #define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL 0x38cd 13892 #define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 13893 #define regVPG9_VPG_GENERIC_PACKET_DATA 0x38ce 13894 #define regVPG9_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 13895 #define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL 0x38cf 13896 #define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 13897 #define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x38d0 13898 #define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 13899 #define regVPG9_VPG_GENERIC_STATUS 0x38d1 13900 #define regVPG9_VPG_GENERIC_STATUS_BASE_IDX 2 13901 #define regVPG9_VPG_MEM_PWR 0x38d2 13902 #define regVPG9_VPG_MEM_PWR_BASE_IDX 2 13903 #define regVPG9_VPG_ISRC1_2_ACCESS_CTRL 0x38d3 13904 #define regVPG9_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 13905 #define regVPG9_VPG_ISRC1_2_DATA 0x38d4 13906 #define regVPG9_VPG_ISRC1_2_DATA_BASE_IDX 2 13907 #define regVPG9_VPG_MPEG_INFO0 0x38d5 13908 #define regVPG9_VPG_MPEG_INFO0_BASE_IDX 2 13909 #define regVPG9_VPG_MPEG_INFO1 0x38d6 13910 #define regVPG9_VPG_MPEG_INFO1_BASE_IDX 2 13911 13912 13913 // addressBlock: dce_dc_hpo_dp_sym32_enc3_dispdec 13914 // base address: 0x1b664 13915 #define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL 0x38d9 13916 #define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL_BASE_IDX 2 13917 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL 0x38da 13918 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 13919 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x38db 13920 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13921 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x38dc 13922 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13923 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x38dd 13924 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 13925 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0 0x38de 13926 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 13927 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1 0x38df 13928 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 13929 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2 0x38e0 13930 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 13931 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3 0x38e1 13932 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 13933 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4 0x38e2 13934 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 13935 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5 0x38e3 13936 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 13937 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6 0x38e4 13938 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 13939 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7 0x38e5 13940 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 13941 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8 0x38e6 13942 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 13943 #define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL 0x38e7 13944 #define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 13945 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x38e8 13946 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 13947 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x38e9 13948 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 13949 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x38ea 13950 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 13951 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x38eb 13952 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 13953 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x38ec 13954 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 13955 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x38ed 13956 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 13957 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x38ee 13958 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 13959 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x38ef 13960 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 13961 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x38f0 13962 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 13963 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x38f1 13964 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 13965 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x38f2 13966 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 13967 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x38f3 13968 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 13969 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x38f4 13970 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 13971 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x38f5 13972 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 13973 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x38f6 13974 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 13975 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL 0x38f7 13976 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 13977 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x38f8 13978 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 13979 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x38f9 13980 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 13981 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x38fa 13982 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 13983 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL 0x38ff 13984 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 13985 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL 0x3900 13986 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 13987 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3901 13988 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 13989 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3902 13990 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 13991 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL 0x3903 13992 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 13993 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0 0x3904 13994 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 13995 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1 0x3905 13996 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 13997 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS 0x3906 13998 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 13999 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS 0x3907 14000 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX 2 14001 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL 0x3908 14002 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX 2 14003 #define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3909 14004 #define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 14005 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE 0x390a 14006 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE_BASE_IDX 2 14007 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT2 0x390f 14008 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT2_BASE_IDX 2 14009 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT3 0x3910 14010 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT3_BASE_IDX 2 14011 14012 14013 // addressBlock: dce_dc_hpo_dp_link_enc0_dispdec 14014 // base address: 0x1ad5c 14015 #define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL 0x3697 14016 #define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 14017 #define regDP_LINK_ENC0_DP_LINK_ENC_SPARE 0x3698 14018 #define regDP_LINK_ENC0_DP_LINK_ENC_SPARE_BASE_IDX 2 14019 14020 14021 // addressBlock: dce_dc_hpo_dp_dphy_sym320_dispdec 14022 // base address: 0x1ae00 14023 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL 0x36c0 14024 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 14025 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS 0x36c1 14026 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS_BASE_IDX 2 14027 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE 0x36c4 14028 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 14029 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0 0x36c5 14030 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 14031 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1 0x36c6 14032 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 14033 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2 0x36c7 14034 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 14035 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3 0x36c8 14036 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 14037 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0 0x36cb 14038 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 14039 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1 0x36cc 14040 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 14041 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2 0x36cd 14042 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 14043 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3 0x36ce 14044 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 14045 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0 0x36d1 14046 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 14047 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1 0x36d2 14048 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 14049 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2 0x36d3 14050 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 14051 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3 0x36d4 14052 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 14053 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG 0x36d7 14054 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 14055 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0 0x36d8 14056 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 14057 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1 0x36d9 14058 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 14059 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2 0x36da 14060 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 14061 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3 0x36db 14062 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 14063 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE 0x36dc 14064 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 14065 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0 0x36dd 14066 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 14067 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1 0x36de 14068 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 14069 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2 0x36df 14070 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 14071 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3 0x36e0 14072 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 14073 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4 0x36e1 14074 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 14075 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5 0x36e2 14076 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 14077 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6 0x36e3 14078 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 14079 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7 0x36e4 14080 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 14081 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8 0x36e5 14082 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 14083 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9 0x36e6 14084 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 14085 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10 0x36e7 14086 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 14087 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS 0x36e8 14088 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 14089 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE 0x36ea 14090 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX 2 14091 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 0x36eb 14092 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX 2 14093 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 0x36ec 14094 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX 2 14095 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL 0x36ed 14096 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX 2 14097 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0 0x36ee 14098 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX 2 14099 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1 0x36ef 14100 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX 2 14101 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS 0x36f0 14102 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX 2 14103 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT 0x36f1 14104 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX 2 14105 14106 14107 // addressBlock: dce_dc_hpo_dp_link_enc1_dispdec 14108 // base address: 0x1b0ac 14109 #define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL 0x376b 14110 #define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 14111 #define regDP_LINK_ENC1_DP_LINK_ENC_SPARE 0x376c 14112 #define regDP_LINK_ENC1_DP_LINK_ENC_SPARE_BASE_IDX 2 14113 14114 14115 // addressBlock: dce_dc_hpo_dp_dphy_sym321_dispdec 14116 // base address: 0x1b150 14117 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL 0x3794 14118 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 14119 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS 0x3795 14120 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS_BASE_IDX 2 14121 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE 0x3798 14122 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 14123 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0 0x3799 14124 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 14125 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1 0x379a 14126 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 14127 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2 0x379b 14128 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 14129 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3 0x379c 14130 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 14131 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0 0x379f 14132 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 14133 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1 0x37a0 14134 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 14135 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2 0x37a1 14136 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 14137 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3 0x37a2 14138 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 14139 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0 0x37a5 14140 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 14141 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1 0x37a6 14142 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 14143 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2 0x37a7 14144 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 14145 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3 0x37a8 14146 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 14147 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG 0x37ab 14148 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 14149 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0 0x37ac 14150 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 14151 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1 0x37ad 14152 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 14153 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2 0x37ae 14154 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 14155 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3 0x37af 14156 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 14157 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE 0x37b0 14158 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 14159 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0 0x37b1 14160 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 14161 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1 0x37b2 14162 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 14163 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2 0x37b3 14164 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 14165 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3 0x37b4 14166 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 14167 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4 0x37b5 14168 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 14169 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5 0x37b6 14170 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 14171 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6 0x37b7 14172 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 14173 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7 0x37b8 14174 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 14175 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8 0x37b9 14176 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 14177 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9 0x37ba 14178 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 14179 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10 0x37bb 14180 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 14181 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS 0x37bc 14182 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 14183 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE 0x37be 14184 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX 2 14185 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 0x37bf 14186 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX 2 14187 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 0x37c0 14188 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX 2 14189 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL 0x37c1 14190 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX 2 14191 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0 0x37c2 14192 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX 2 14193 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1 0x37c3 14194 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX 2 14195 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS 0x37c4 14196 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX 2 14197 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT 0x37c5 14198 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX 2 14199 14200 14201 // addressBlock: dce_dc_dchvm_hvm_dispdec 14202 // base address: 0x0 14203 #define regDCHVM_CTRL0 0x3603 14204 #define regDCHVM_CTRL0_BASE_IDX 2 14205 #define regDCHVM_CTRL1 0x3604 14206 #define regDCHVM_CTRL1_BASE_IDX 2 14207 #define regDCHVM_CLK_CTRL 0x3605 14208 #define regDCHVM_CLK_CTRL_BASE_IDX 2 14209 #define regDCHVM_MEM_CTRL 0x3606 14210 #define regDCHVM_MEM_CTRL_BASE_IDX 2 14211 #define regDCHVM_RIOMMU_CTRL0 0x3607 14212 #define regDCHVM_RIOMMU_CTRL0_BASE_IDX 2 14213 #define regDCHVM_RIOMMU_STAT0 0x3608 14214 #define regDCHVM_RIOMMU_STAT0_BASE_IDX 2 14215 14216 14217 // addressBlock: dce_dc_dlpc_dlpc_dispdec 14218 // base address: 0x0 14219 #define regDLPC_ENABLE 0x2fe8 14220 #define regDLPC_ENABLE_BASE_IDX 2 14221 #define regDLPC_CURRENT_COUNT 0x2fe9 14222 #define regDLPC_CURRENT_COUNT_BASE_IDX 2 14223 #define regDLPC_OPTC_SNAPSHOT 0x2fea 14224 #define regDLPC_OPTC_SNAPSHOT_BASE_IDX 2 14225 #define regDLPC_PWRUP 0x2feb 14226 #define regDLPC_PWRUP_BASE_IDX 2 14227 #define regDLPC_OTG_RESYNC 0x2fec 14228 #define regDLPC_OTG_RESYNC_BASE_IDX 2 14229 #define regDLPC_DCN_ZSC_LONO_PWRUP 0x2fed 14230 #define regDLPC_DCN_ZSC_LONO_PWRUP_BASE_IDX 2 14231 #define regDLPC_SPARE 0x2fee 14232 #define regDLPC_SPARE_BASE_IDX 2 14233 #define regDLPC_COUNTER_INIT_VALUE 0x2fef 14234 #define regDLPC_COUNTER_INIT_VALUE_BASE_IDX 2 14235 14236 14237 // addressBlock: dce_dpia_dpia_mu0_dpiadec 14238 // base address: 0x72000 14239 #define regDPIA_MU_CLOCK_CTRL 0x13800 14240 #define regDPIA_MU_CLOCK_CTRL_BASE_IDX 3 14241 #define regDPIA_MU_CLOCK_CTRL_DPIA_PORT0 0x13801 14242 #define regDPIA_MU_CLOCK_CTRL_DPIA_PORT0_BASE_IDX 3 14243 #define regDPIA_MU_RESET_CTRL_DPIA_PORT0 0x13802 14244 #define regDPIA_MU_RESET_CTRL_DPIA_PORT0_BASE_IDX 3 14245 #define regDPIA_MU_CLOCK_CTRL_DPIA_PORT1 0x13803 14246 #define regDPIA_MU_CLOCK_CTRL_DPIA_PORT1_BASE_IDX 3 14247 #define regDPIA_MU_RESET_CTRL_DPIA_PORT1 0x13804 14248 #define regDPIA_MU_RESET_CTRL_DPIA_PORT1_BASE_IDX 3 14249 #define regDPIA_MU_CLOCK_CTRL_DPIA_PORT2 0x13805 14250 #define regDPIA_MU_CLOCK_CTRL_DPIA_PORT2_BASE_IDX 3 14251 #define regDPIA_MU_RESET_CTRL_DPIA_PORT2 0x13806 14252 #define regDPIA_MU_RESET_CTRL_DPIA_PORT2_BASE_IDX 3 14253 #define regDPIA_MU_CLOCK_CTRL_DPIA_PORT3 0x13807 14254 #define regDPIA_MU_CLOCK_CTRL_DPIA_PORT3_BASE_IDX 3 14255 #define regDPIA_MU_RESET_CTRL_DPIA_PORT3 0x13808 14256 #define regDPIA_MU_RESET_CTRL_DPIA_PORT3_BASE_IDX 3 14257 #define regDPIA_MU_TPI_STATUS_DPIA_PORT0 0x13811 14258 #define regDPIA_MU_TPI_STATUS_DPIA_PORT0_BASE_IDX 3 14259 #define regDPIA_MU_TPI_STATUS_DPIA_PORT1 0x13812 14260 #define regDPIA_MU_TPI_STATUS_DPIA_PORT1_BASE_IDX 3 14261 #define regDPIA_MU_TPI_STATUS_DPIA_PORT2 0x13813 14262 #define regDPIA_MU_TPI_STATUS_DPIA_PORT2_BASE_IDX 3 14263 #define regDPIA_MU_TPI_STATUS_DPIA_PORT3 0x13814 14264 #define regDPIA_MU_TPI_STATUS_DPIA_PORT3_BASE_IDX 3 14265 #define regDPIA_MU_TPI_MAX_CREDIT_COUNT 0x13819 14266 #define regDPIA_MU_TPI_MAX_CREDIT_COUNT_BASE_IDX 3 14267 #define regDPIA_MU_INTERRUPT_STATUS 0x1381a 14268 #define regDPIA_MU_INTERRUPT_STATUS_BASE_IDX 3 14269 #define regDPIA_MU_INTERRUPT_CTRL 0x1381b 14270 #define regDPIA_MU_INTERRUPT_CTRL_BASE_IDX 3 14271 #define regDPIA_MU_LOCAL_INTERRUPT_CTRL 0x1381c 14272 #define regDPIA_MU_LOCAL_INTERRUPT_CTRL_BASE_IDX 3 14273 #define regDPIA_MU_LOCAL_INTERRUPT_ACK 0x1381d 14274 #define regDPIA_MU_LOCAL_INTERRUPT_ACK_BASE_IDX 3 14275 #define regDPIA_MU_RBBMIF_TIMEOUT_CTRL 0x1381e 14276 #define regDPIA_MU_RBBMIF_TIMEOUT_CTRL_BASE_IDX 3 14277 #define regDPIA_MU_RBBMIF_TIMEOUT_CTRL2 0x1381f 14278 #define regDPIA_MU_RBBMIF_TIMEOUT_CTRL2_BASE_IDX 3 14279 #define regDPIA_MU_RBBMIF_STATUS 0x13820 14280 #define regDPIA_MU_RBBMIF_STATUS_BASE_IDX 3 14281 #define regDPIA_MU_MICROSECOND_REF_CTRL 0x13821 14282 #define regDPIA_MU_MICROSECOND_REF_CTRL_BASE_IDX 3 14283 #define regDPIA_MU_PORT_ADP_STATUS 0x13822 14284 #define regDPIA_MU_PORT_ADP_STATUS_BASE_IDX 3 14285 #define regDPIA_GLUE_CTRL 0x13823 14286 #define regDPIA_GLUE_CTRL_BASE_IDX 3 14287 #define regDPIA_PERF_COUNT_CONTROL0 0x13825 14288 #define regDPIA_PERF_COUNT_CONTROL0_BASE_IDX 3 14289 #define regDPIA_PERF_COUNT_CONTROL1 0x13826 14290 #define regDPIA_PERF_COUNT_CONTROL1_BASE_IDX 3 14291 #define regDPIA_PERF_COUNT_CONTROL2 0x13827 14292 #define regDPIA_PERF_COUNT_CONTROL2_BASE_IDX 3 14293 #define regDPIA_PERF_COUNT_CONTROL3 0x13828 14294 #define regDPIA_PERF_COUNT_CONTROL3_BASE_IDX 3 14295 #define regDPIA_PERF_COUNT_CONTROL4 0x13829 14296 #define regDPIA_PERF_COUNT_CONTROL4_BASE_IDX 3 14297 #define regDPIA_PERF_COUNT_CONTROL5 0x1382a 14298 #define regDPIA_PERF_COUNT_CONTROL5_BASE_IDX 3 14299 #define regDPIA_PERF_COUNT_INDEX 0x1382b 14300 #define regDPIA_PERF_COUNT_INDEX_BASE_IDX 3 14301 #define regDPIA_PERF_COUNT_DATA_LO 0x1382c 14302 #define regDPIA_PERF_COUNT_DATA_LO_BASE_IDX 3 14303 #define regDPIA_MU_SPARE 0x1382d 14304 #define regDPIA_MU_SPARE_BASE_IDX 3 14305 14306 14307 // addressBlock: azendpoint_f2codecind 14308 // base address: 0x0 14309 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 14310 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 14311 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d 14312 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e 14313 #define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 14314 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e 14315 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 14316 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 14317 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 14318 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a 14319 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b 14320 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 14321 #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 14322 #define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 14323 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 14324 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c 14325 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d 14326 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e 14327 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f 14328 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 14329 #define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 14330 #define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 14331 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 14332 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 14333 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 14334 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 14335 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 14336 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a 14337 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b 14338 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c 14339 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 14340 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 14341 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 14342 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 14343 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 14344 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 14345 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 14346 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a 14347 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b 14348 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c 14349 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d 14350 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e 14351 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f 14352 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 14353 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 14354 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 14355 #define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 14356 #define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 14357 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 14358 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 14359 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a 14360 #define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b 14361 #define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c 14362 #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d 14363 #define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e 14364 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 14365 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c 14366 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e 14367 14368 14369 // addressBlock: azendpoint_descriptorind 14370 // base address: 0x0 14371 #define ixAUDIO_DESCRIPTOR0 0x0001 14372 #define ixAUDIO_DESCRIPTOR1 0x0002 14373 #define ixAUDIO_DESCRIPTOR2 0x0003 14374 #define ixAUDIO_DESCRIPTOR3 0x0004 14375 #define ixAUDIO_DESCRIPTOR4 0x0005 14376 #define ixAUDIO_DESCRIPTOR5 0x0006 14377 #define ixAUDIO_DESCRIPTOR6 0x0007 14378 #define ixAUDIO_DESCRIPTOR7 0x0008 14379 #define ixAUDIO_DESCRIPTOR8 0x0009 14380 #define ixAUDIO_DESCRIPTOR9 0x000a 14381 #define ixAUDIO_DESCRIPTOR10 0x000b 14382 #define ixAUDIO_DESCRIPTOR11 0x000c 14383 #define ixAUDIO_DESCRIPTOR12 0x000d 14384 #define ixAUDIO_DESCRIPTOR13 0x000e 14385 14386 14387 // addressBlock: azendpoint_sinkinfoind 14388 // base address: 0x0 14389 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000 14390 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001 14391 #define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002 14392 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003 14393 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004 14394 #define ixSINK_DESCRIPTION0 0x0005 14395 #define ixSINK_DESCRIPTION1 0x0006 14396 #define ixSINK_DESCRIPTION2 0x0007 14397 #define ixSINK_DESCRIPTION3 0x0008 14398 #define ixSINK_DESCRIPTION4 0x0009 14399 #define ixSINK_DESCRIPTION5 0x000a 14400 #define ixSINK_DESCRIPTION6 0x000b 14401 #define ixSINK_DESCRIPTION7 0x000c 14402 #define ixSINK_DESCRIPTION8 0x000d 14403 #define ixSINK_DESCRIPTION9 0x000e 14404 #define ixSINK_DESCRIPTION10 0x000f 14405 #define ixSINK_DESCRIPTION11 0x0010 14406 #define ixSINK_DESCRIPTION12 0x0011 14407 #define ixSINK_DESCRIPTION13 0x0012 14408 #define ixSINK_DESCRIPTION14 0x0013 14409 #define ixSINK_DESCRIPTION15 0x0014 14410 #define ixSINK_DESCRIPTION16 0x0015 14411 #define ixSINK_DESCRIPTION17 0x0016 14412 14413 14414 // addressBlock: azf0controller_azinputcrc0resultind 14415 // base address: 0x0 14416 #define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000 14417 #define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001 14418 #define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002 14419 #define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003 14420 #define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004 14421 #define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005 14422 #define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006 14423 #define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007 14424 14425 14426 // addressBlock: azf0controller_azinputcrc1resultind 14427 // base address: 0x0 14428 #define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000 14429 #define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001 14430 #define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002 14431 #define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003 14432 #define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004 14433 #define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005 14434 #define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006 14435 #define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007 14436 14437 14438 // addressBlock: azf0controller_azcrc0resultind 14439 // base address: 0x0 14440 #define ixAZALIA_CRC0_CHANNEL0 0x0000 14441 #define ixAZALIA_CRC0_CHANNEL1 0x0001 14442 #define ixAZALIA_CRC0_CHANNEL2 0x0002 14443 #define ixAZALIA_CRC0_CHANNEL3 0x0003 14444 #define ixAZALIA_CRC0_CHANNEL4 0x0004 14445 #define ixAZALIA_CRC0_CHANNEL5 0x0005 14446 #define ixAZALIA_CRC0_CHANNEL6 0x0006 14447 #define ixAZALIA_CRC0_CHANNEL7 0x0007 14448 14449 14450 // addressBlock: azf0controller_azcrc1resultind 14451 // base address: 0x0 14452 #define ixAZALIA_CRC1_CHANNEL0 0x0000 14453 #define ixAZALIA_CRC1_CHANNEL1 0x0001 14454 #define ixAZALIA_CRC1_CHANNEL2 0x0002 14455 #define ixAZALIA_CRC1_CHANNEL3 0x0003 14456 #define ixAZALIA_CRC1_CHANNEL4 0x0004 14457 #define ixAZALIA_CRC1_CHANNEL5 0x0005 14458 #define ixAZALIA_CRC1_CHANNEL6 0x0006 14459 #define ixAZALIA_CRC1_CHANNEL7 0x0007 14460 14461 14462 // addressBlock: azinputendpoint_f2codecind 14463 // base address: 0x0 14464 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 14465 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 14466 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d 14467 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 14468 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a 14469 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b 14470 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 14471 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 14472 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 14473 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c 14474 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d 14475 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e 14476 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f 14477 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 14478 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 14479 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 14480 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 14481 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a 14482 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c 14483 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 14484 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 14485 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 14486 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 14487 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 14488 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 14489 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a 14490 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b 14491 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c 14492 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d 14493 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e 14494 #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 14495 #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c 14496 14497 14498 // addressBlock: azroot_f2codecind 14499 // base address: 0x0 14500 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00 14501 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02 14502 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04 14503 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 14504 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 14505 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 14506 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 14507 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 14508 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 14509 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff 14510 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 14511 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 14512 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a 14513 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b 14514 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f 14515 14516 14517 // addressBlock: azf0stream0_streamind 14518 // base address: 0x0 14519 #define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000 14520 #define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14521 #define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14522 #define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14523 #define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14524 14525 14526 // addressBlock: azf0stream1_streamind 14527 // base address: 0x0 14528 #define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000 14529 #define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14530 #define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14531 #define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14532 #define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14533 14534 14535 // addressBlock: azf0stream2_streamind 14536 // base address: 0x0 14537 #define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000 14538 #define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14539 #define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14540 #define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14541 #define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14542 14543 14544 // addressBlock: azf0stream3_streamind 14545 // base address: 0x0 14546 #define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000 14547 #define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14548 #define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14549 #define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14550 #define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14551 14552 14553 // addressBlock: azf0stream4_streamind 14554 // base address: 0x0 14555 #define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000 14556 #define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14557 #define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14558 #define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14559 #define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14560 14561 14562 // addressBlock: azf0stream5_streamind 14563 // base address: 0x0 14564 #define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000 14565 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14566 #define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14567 #define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14568 #define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14569 14570 14571 // addressBlock: azf0stream6_streamind 14572 // base address: 0x0 14573 #define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000 14574 #define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14575 #define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14576 #define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14577 #define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14578 14579 14580 // addressBlock: azf0stream7_streamind 14581 // base address: 0x0 14582 #define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000 14583 #define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14584 #define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14585 #define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14586 #define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14587 14588 14589 // addressBlock: azf0stream8_streamind 14590 // base address: 0x0 14591 #define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000 14592 #define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14593 #define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14594 #define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14595 #define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14596 14597 14598 // addressBlock: azf0stream9_streamind 14599 // base address: 0x0 14600 #define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000 14601 #define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14602 #define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14603 #define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14604 #define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14605 14606 14607 // addressBlock: azf0stream10_streamind 14608 // base address: 0x0 14609 #define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000 14610 #define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14611 #define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14612 #define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14613 #define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14614 14615 14616 // addressBlock: azf0stream11_streamind 14617 // base address: 0x0 14618 #define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000 14619 #define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14620 #define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14621 #define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14622 #define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14623 14624 14625 // addressBlock: azf0stream12_streamind 14626 // base address: 0x0 14627 #define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000 14628 #define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14629 #define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14630 #define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14631 #define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14632 14633 14634 // addressBlock: azf0stream13_streamind 14635 // base address: 0x0 14636 #define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000 14637 #define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14638 #define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14639 #define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14640 #define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14641 14642 14643 // addressBlock: azf0stream14_streamind 14644 // base address: 0x0 14645 #define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000 14646 #define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14647 #define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14648 #define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14649 #define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14650 14651 14652 // addressBlock: azf0stream15_streamind 14653 // base address: 0x0 14654 #define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000 14655 #define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14656 #define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14657 #define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14658 #define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14659 14660 14661 // addressBlock: azf0endpoint0_endpointind 14662 // base address: 0x0 14663 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14664 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14665 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14666 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14667 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14668 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14669 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14670 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14671 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14672 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14673 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14674 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14675 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14676 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14677 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14678 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14679 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14680 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14681 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14682 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14683 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14684 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14685 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14686 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14687 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14688 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14689 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14690 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14691 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14692 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14693 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14694 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14695 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14696 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14697 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14698 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14699 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14700 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14701 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14702 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14703 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14704 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14705 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14706 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14707 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14708 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14709 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14710 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14711 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14712 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14713 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14714 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14715 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14716 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14717 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14718 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14719 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14720 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14721 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14722 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14723 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14724 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14725 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14726 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14727 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14728 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14729 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14730 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14731 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14732 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14733 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14734 #define ixAZF0ENDPOINT0_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 14735 14736 14737 // addressBlock: azf0endpoint1_endpointind 14738 // base address: 0x0 14739 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14740 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14741 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14742 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14743 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14744 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14745 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14746 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14747 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14748 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14749 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14750 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14751 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14752 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14753 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14754 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14755 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14756 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14757 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14758 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14759 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14760 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14761 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14762 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14763 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14764 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14765 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14766 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14767 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14768 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14769 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14770 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14771 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14772 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14773 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14774 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14775 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14776 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14777 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14778 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14779 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14780 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14781 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14782 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14783 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14784 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14785 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14786 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14787 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14788 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14789 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14790 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14791 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14792 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14793 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14794 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14795 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14796 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14797 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14798 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14799 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14800 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14801 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14802 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14803 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14804 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14805 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14806 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14807 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14808 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14809 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14810 #define ixAZF0ENDPOINT1_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 14811 14812 14813 // addressBlock: azf0endpoint2_endpointind 14814 // base address: 0x0 14815 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14816 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14817 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14818 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14819 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14820 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14821 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14822 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14823 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14824 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14825 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14826 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14827 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14828 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14829 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14830 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14831 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14832 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14833 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14834 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14835 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14836 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14837 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14838 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14839 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14840 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14841 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14842 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14843 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14844 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14845 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14846 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14847 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14848 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14849 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14850 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14851 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14852 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14853 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14854 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14855 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14856 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14857 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14858 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14859 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14860 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14861 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14862 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14863 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14864 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14865 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14866 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14867 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14868 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14869 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14870 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14871 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14872 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14873 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14874 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14875 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14876 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14877 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14878 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14879 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14880 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14881 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14882 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14883 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14884 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14885 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14886 #define ixAZF0ENDPOINT2_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 14887 14888 14889 // addressBlock: azf0endpoint3_endpointind 14890 // base address: 0x0 14891 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14892 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14893 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14894 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14895 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14896 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14897 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14898 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14899 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14900 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14901 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14902 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14903 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14904 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14905 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14906 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14907 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14908 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14909 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14910 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14911 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14912 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14913 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14914 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14915 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14916 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14917 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14918 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14919 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14920 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14921 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14922 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14923 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14924 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14925 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14926 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14927 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14928 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14929 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14930 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14931 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14932 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14933 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14934 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14935 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14936 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14937 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14938 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14939 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14940 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14941 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14942 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14943 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14944 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14945 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14946 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14947 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14948 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14949 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14950 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14951 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14952 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14953 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14954 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14955 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14956 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14957 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14958 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14959 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14960 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14961 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14962 #define ixAZF0ENDPOINT3_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 14963 14964 14965 // addressBlock: azf0endpoint4_endpointind 14966 // base address: 0x0 14967 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14968 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14969 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14970 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14971 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14972 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14973 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14974 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14975 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14976 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14977 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14978 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14979 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14980 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14981 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14982 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14983 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14984 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14985 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14986 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14987 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14988 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14989 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14990 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14991 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14992 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14993 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14994 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14995 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14996 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14997 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14998 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14999 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15000 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 15001 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 15002 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 15003 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 15004 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 15005 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 15006 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 15007 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 15008 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 15009 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 15010 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 15011 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15012 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15013 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15014 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 15015 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 15016 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 15017 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 15018 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 15019 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 15020 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 15021 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 15022 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 15023 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 15024 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 15025 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 15026 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 15027 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15028 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 15029 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15030 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 15031 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 15032 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 15033 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 15034 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 15035 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 15036 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 15037 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 15038 #define ixAZF0ENDPOINT4_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 15039 15040 15041 // addressBlock: azf0endpoint5_endpointind 15042 // base address: 0x0 15043 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15044 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15045 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15046 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15047 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15048 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15049 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 15050 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 15051 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 15052 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 15053 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 15054 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 15055 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15056 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 15057 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15058 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 15059 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 15060 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 15061 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 15062 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 15063 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 15064 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 15065 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 15066 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 15067 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 15068 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 15069 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 15070 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 15071 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 15072 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 15073 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 15074 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 15075 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15076 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 15077 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 15078 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 15079 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 15080 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 15081 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 15082 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 15083 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 15084 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 15085 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 15086 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 15087 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15088 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15089 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15090 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 15091 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 15092 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 15093 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 15094 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 15095 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 15096 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 15097 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 15098 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 15099 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 15100 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 15101 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 15102 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 15103 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15104 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 15105 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15106 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 15107 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 15108 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 15109 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 15110 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 15111 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 15112 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 15113 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 15114 #define ixAZF0ENDPOINT5_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 15115 15116 15117 // addressBlock: azf0endpoint6_endpointind 15118 // base address: 0x0 15119 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15120 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15121 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15122 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15123 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15124 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15125 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 15126 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 15127 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 15128 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 15129 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 15130 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 15131 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15132 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 15133 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15134 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 15135 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 15136 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 15137 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 15138 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 15139 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 15140 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 15141 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 15142 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 15143 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 15144 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 15145 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 15146 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 15147 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 15148 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 15149 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 15150 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 15151 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15152 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 15153 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 15154 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 15155 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 15156 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 15157 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 15158 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 15159 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 15160 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 15161 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 15162 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 15163 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15164 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15165 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15166 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 15167 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 15168 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 15169 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 15170 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 15171 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 15172 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 15173 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 15174 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 15175 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 15176 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 15177 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 15178 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 15179 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15180 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 15181 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15182 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 15183 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 15184 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 15185 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 15186 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 15187 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 15188 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 15189 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 15190 #define ixAZF0ENDPOINT6_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 15191 15192 15193 // addressBlock: azf0endpoint7_endpointind 15194 // base address: 0x0 15195 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15196 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15197 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15198 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15199 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15200 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15201 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 15202 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 15203 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 15204 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 15205 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 15206 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 15207 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15208 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 15209 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15210 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 15211 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 15212 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 15213 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 15214 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 15215 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 15216 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 15217 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 15218 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 15219 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 15220 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 15221 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 15222 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 15223 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 15224 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 15225 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 15226 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 15227 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15228 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 15229 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 15230 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 15231 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 15232 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 15233 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 15234 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 15235 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 15236 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 15237 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 15238 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 15239 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15240 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15241 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15242 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 15243 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 15244 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 15245 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 15246 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 15247 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 15248 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 15249 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 15250 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 15251 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 15252 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 15253 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 15254 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 15255 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15256 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 15257 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15258 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 15259 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 15260 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 15261 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 15262 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 15263 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 15264 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 15265 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 15266 #define ixAZF0ENDPOINT7_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 15267 15268 15269 // addressBlock: azf0inputendpoint0_inputendpointind 15270 // base address: 0x0 15271 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15272 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15273 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15274 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15275 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15276 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15277 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15278 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 15279 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15280 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 15281 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 15282 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15283 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 15284 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 15285 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 15286 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15287 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15288 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15289 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15290 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 15291 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15292 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 15293 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15294 15295 15296 // addressBlock: azf0inputendpoint1_inputendpointind 15297 // base address: 0x0 15298 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15299 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15300 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15301 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15302 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15303 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15304 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15305 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 15306 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15307 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 15308 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 15309 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15310 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 15311 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 15312 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 15313 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15314 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15315 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15316 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15317 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 15318 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15319 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 15320 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15321 15322 15323 // addressBlock: azf0inputendpoint2_inputendpointind 15324 // base address: 0x0 15325 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15326 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15327 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15328 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15329 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15330 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15331 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15332 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 15333 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15334 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 15335 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 15336 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15337 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 15338 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 15339 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 15340 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15341 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15342 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15343 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15344 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 15345 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15346 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 15347 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15348 15349 15350 // addressBlock: azf0inputendpoint3_inputendpointind 15351 // base address: 0x0 15352 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15353 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15354 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15355 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15356 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15357 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15358 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15359 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 15360 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15361 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 15362 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 15363 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15364 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 15365 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 15366 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 15367 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15368 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15369 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15370 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15371 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 15372 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15373 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 15374 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15375 15376 15377 // addressBlock: azf0inputendpoint4_inputendpointind 15378 // base address: 0x0 15379 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15380 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15381 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15382 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15383 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15384 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15385 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15386 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 15387 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15388 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 15389 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 15390 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15391 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 15392 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 15393 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 15394 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15395 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15396 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15397 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15398 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 15399 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15400 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 15401 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15402 15403 15404 // addressBlock: azf0inputendpoint5_inputendpointind 15405 // base address: 0x0 15406 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15407 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15408 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15409 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15410 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15411 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15412 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15413 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 15414 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15415 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 15416 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 15417 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15418 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 15419 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 15420 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 15421 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15422 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15423 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15424 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15425 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 15426 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15427 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 15428 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15429 15430 15431 // addressBlock: azf0inputendpoint6_inputendpointind 15432 // base address: 0x0 15433 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15434 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15435 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15436 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15437 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15438 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15439 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15440 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 15441 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15442 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 15443 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 15444 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15445 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 15446 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 15447 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 15448 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15449 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15450 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15451 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15452 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 15453 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15454 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 15455 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15456 15457 15458 // addressBlock: azf0inputendpoint7_inputendpointind 15459 // base address: 0x0 15460 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15461 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15462 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15463 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15464 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15465 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15466 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15467 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 15468 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15469 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 15470 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 15471 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15472 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 15473 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 15474 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 15475 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15476 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15477 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15478 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15479 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 15480 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15481 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 15482 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15483 15484 15485 #endif 15486