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Searched refs:regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h5994 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G … macro
H A Ddcn_3_5_0_offset.h12842 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G … macro
H A Ddcn_3_5_1_offset.h12821 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G … macro
H A Ddcn_3_2_1_offset.h5542 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G … macro
H A Ddcn_3_1_4_offset.h13908 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G … macro
H A Ddcn_3_1_2_offset.h7241 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G … macro
H A Ddcn_3_2_0_offset.h5543 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G … macro
H A Ddcn_3_1_5_offset.h7000 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G … macro
H A Ddcn_4_1_0_offset.h6082 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G … macro
H A Ddcn_3_1_6_offset.h7461 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G … macro