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Searched refs:regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h6429 #define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h14242 #define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h14221 #define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h5977 #define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h5978 #define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h6573 #define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX … macro