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Searched refs:regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G (Results 1 – 6 of 6) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h6320 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G … macro
H A Ddcn_3_5_0_offset.h14133 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G … macro
H A Ddcn_3_5_1_offset.h14112 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G … macro
H A Ddcn_3_2_1_offset.h5868 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G … macro
H A Ddcn_3_2_0_offset.h5869 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G … macro
H A Ddcn_4_1_0_offset.h6408 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G … macro