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Searched refs:regMPCC3_MPCC_BG_G_Y_BASE_IDX (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h5325 #define regMPCC3_MPCC_BG_G_Y_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h12268 #define regMPCC3_MPCC_BG_G_Y_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h12247 #define regMPCC3_MPCC_BG_G_Y_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h4899 #define regMPCC3_MPCC_BG_G_Y_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h13335 #define regMPCC3_MPCC_BG_G_Y_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h6574 #define regMPCC3_MPCC_BG_G_Y_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h4900 #define regMPCC3_MPCC_BG_G_Y_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h6333 #define regMPCC3_MPCC_BG_G_Y_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h5423 #define regMPCC3_MPCC_BG_G_Y_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h6794 #define regMPCC3_MPCC_BG_G_Y_BASE_IDX … macro