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Searched refs:regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h1209 #define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h2094 #define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h2073 #define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h1055 #define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h2333 #define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h1418 #define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h1055 #define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h1181 #define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h1066 #define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h1634 #define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX … macro