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Searched refs:regJPEG_CGC_CTRL (Results 1 – 9 of 9) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Djpeg_v5_0_0.c246 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); in jpeg_v5_0_0_disable_clock_gating()
249 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data); in jpeg_v5_0_0_disable_clock_gating()
256 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); in jpeg_v5_0_0_enable_clock_gating()
259 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data); in jpeg_v5_0_0_enable_clock_gating()
H A Djpeg_v4_0.c277 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); in jpeg_v4_0_disable_clock_gating()
287 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data); in jpeg_v4_0_disable_clock_gating()
301 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); in jpeg_v4_0_enable_clock_gating()
311 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data); in jpeg_v4_0_enable_clock_gating()
H A Djpeg_v4_0_5.c310 data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL); in jpeg_v4_0_5_disable_clock_gating()
320 WREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL, data); in jpeg_v4_0_5_disable_clock_gating()
334 data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL); in jpeg_v4_0_5_enable_clock_gating()
344 WREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL, data); in jpeg_v4_0_5_enable_clock_gating()
H A Djpeg_v4_0_3.c486 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL); in jpeg_v4_0_3_disable_clock_gating()
496 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL, data); in jpeg_v4_0_3_disable_clock_gating()
511 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL); in jpeg_v4_0_3_enable_clock_gating()
521 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL, data); in jpeg_v4_0_3_enable_clock_gating()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h846 #define regJPEG_CGC_CTRL … macro
H A Dvcn_5_0_0_offset.h916 #define regJPEG_CGC_CTRL … macro
H A Dvcn_4_0_5_offset.h1085 #define regJPEG_CGC_CTRL … macro
H A Dvcn_4_0_0_offset.h1116 #define regJPEG_CGC_CTRL … macro
H A Dvcn_4_0_3_offset.h1041 #define regJPEG_CGC_CTRL … macro