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Searched refs:regIH_RB_CNTL_RING1 (Results 1 – 7 of 7) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Dosssys_4_4_2_offset.h130 #define regIH_RB_CNTL_RING1 … macro
H A Dosssys_6_0_0_offset.h130 #define regIH_RB_CNTL_RING1 … macro
H A Dosssys_6_1_0_offset.h130 #define regIH_RB_CNTL_RING1 … macro
H A Dosssys_7_0_0_offset.h130 #define regIH_RB_CNTL_RING1 … macro
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dih_v6_0.c69 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL_RING1); in ih_v6_0_init_register_offset()
99 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1); in force_update_wptr_for_self_int()
112 WREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1, ih_rb_cntl); in force_update_wptr_for_self_int()
H A Dih_v6_1.c69 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL_RING1); in ih_v6_1_init_register_offset()
99 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1); in force_update_wptr_for_self_int()
112 WREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1, ih_rb_cntl); in force_update_wptr_for_self_int()
H A Dih_v7_0.c69 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL_RING1); in ih_v7_0_init_register_offset()
99 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1); in force_update_wptr_for_self_int()
112 WREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1, ih_rb_cntl); in force_update_wptr_for_self_int()