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Searched refs:regGRBM_GFX_INDEX (Results 1 – 15 of 15) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dimu_v12_0.c207 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0xe0000000, 0x1c0000),
211 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000000, 0x1c0000),
213 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000001, 0x1c0000),
215 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000100, 0x1c0000),
217 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000101, 0x1c0000),
219 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0xe0000000, 0x1c0000),
351 if (reg == SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX)) { in program_imu_rlc_ram()
H A Damdgpu_amdkfd_gfx_v12.c171 WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), gfx_index_val); in wave_control_execute_v12()
181 WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), data); in wave_control_execute_v12()
H A Damdgpu_amdkfd_gfx_v11.c582 WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), gfx_index_val); in wave_control_execute_v11()
592 WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), data); in wave_control_execute_v11()
H A Dgfx_v9_4_3.c708 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); in gfx_v9_4_3_xcc_select_se_sh()
1400 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1644 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)},
H A Dmes_v11_0.c384 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, in mes_v11_0_reset_queue_mmio()
H A Dmes_v12_0.c403 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, in mes_v12_0_reset_queue_mmio()
H A Dgfx_v9_4_2.c871 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, 0, regGRBM_GFX_INDEX, data); in gfx_v9_4_2_select_se_sh()
H A Dgfx_v12_0.c722 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); in gfx_v12_0_init_rlcg_reg_access_ctrl()
1610 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); in gfx_v12_0_select_se_sh()
H A Dgfx_v11_0.c904 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); in gfx_v11_0_init_rlcg_reg_access_ctrl()
1889 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); in gfx_v11_0_select_se_sh()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h3076 #define regGRBM_GFX_INDEX … macro
H A Dgc_9_4_3_offset.h5308 #define regGRBM_GFX_INDEX … macro
H A Dgc_11_5_0_offset.h5943 #define regGRBM_GFX_INDEX … macro
H A Dgc_12_0_0_offset.h4566 #define regGRBM_GFX_INDEX … macro
H A Dgc_11_0_0_offset.h7170 #define regGRBM_GFX_INDEX … macro
H A Dgc_11_0_3_offset.h7476 #define regGRBM_GFX_INDEX … macro