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Searched refs:regGDS_VMID0_BASE (Results 1 – 7 of 7) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c1240 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0); in gfx_v9_4_3_xcc_init_compute_vmid()
1258 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0); in gfx_v9_4_3_xcc_init_gds_vmid()
2448 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid, in gfx_v9_4_3_ring_emit_gds_switch()
H A Dgfx_v11_0.c2000 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0); in gfx_v11_0_init_compute_vmid()
2018 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0); in gfx_v11_0_init_gds_vmid()
5039 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid, in gfx_v11_0_ring_emit_gds_switch()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h1278 #define regGDS_VMID0_BASE … macro
H A Dgc_9_4_3_offset.h3458 #define regGDS_VMID0_BASE … macro
H A Dgc_11_5_0_offset.h3737 #define regGDS_VMID0_BASE … macro
H A Dgc_11_0_0_offset.h4764 #define regGDS_VMID0_BASE … macro
H A Dgc_11_0_3_offset.h4988 #define regGDS_VMID0_BASE … macro