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Searched refs:regGB_ADDR_CONFIG (Results 1 – 16 of 16) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dimu_v11_0_3.c91 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x00000444, 0xe0000000),
94 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x00000244, 0xe0000000),
H A Dimu_v11_0.c230 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x00000545, 0xe0000000),
235 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x00000345, 0xe0000000),
284 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x00000243, 0xe0000000),
H A Dsoc24.c132 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)},
161 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && in soc24_get_register_value()
H A Dsoc21.c269 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)},
296 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config) in soc21_get_register_value()
H A Dimu_v12_0.c220 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x08200545, 0x1c0000),
H A Dgfx_v9_4_2.c82 SOC15_REG_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042),
H A Dgfx_v9_4_3.c350 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG, in gfx_v9_4_3_init_golden_registers()
H A Dgfx_v12_0.c3446 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); in get_gb_addr_config()
H A Dgfx_v11_0.c4580 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); in get_gb_addr_config()
/linux-6.15/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_plane.c646 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); in amdgpu_dm_plane_add_gfx11_modifiers()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h4760 #define regGB_ADDR_CONFIG … macro
H A Dgc_9_4_3_offset.h1048 #define regGB_ADDR_CONFIG … macro
H A Dgc_11_5_0_offset.h1491 #define regGB_ADDR_CONFIG … macro
H A Dgc_12_0_0_offset.h7589 #define regGB_ADDR_CONFIG … macro
H A Dgc_11_0_0_offset.h2390 #define regGB_ADDR_CONFIG … macro
H A Dgc_11_0_3_offset.h2498 #define regGB_ADDR_CONFIG … macro