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Searched refs:regDSCL1_OTG_V_BLANK_BASE_IDX (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h4077 #define regDSCL1_OTG_V_BLANK_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h4976 #define regDSCL1_OTG_V_BLANK_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h4955 #define regDSCL1_OTG_V_BLANK_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h3729 #define regDSCL1_OTG_V_BLANK_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h5415 #define regDSCL1_OTG_V_BLANK_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h4506 #define regDSCL1_OTG_V_BLANK_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h3730 #define regDSCL1_OTG_V_BLANK_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h4265 #define regDSCL1_OTG_V_BLANK_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h3922 #define regDSCL1_OTG_V_BLANK_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h4726 #define regDSCL1_OTG_V_BLANK_BASE_IDX … macro