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Searched refs:regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h4097 #define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h4996 #define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h4975 #define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h3749 #define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h5435 #define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h4526 #define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h3750 #define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h4285 #define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h3942 #define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h4746 #define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX … macro