Home
last modified time | relevance | path

Searched refs:regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h4093 #define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h4992 #define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h4971 #define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h3745 #define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h5431 #define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h4522 #define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h3746 #define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h4281 #define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h3938 #define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h4742 #define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX … macro