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Searched refs:regDSCL0_OTG_H_BLANK_BASE_IDX (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h3659 #define regDSCL0_OTG_H_BLANK_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h4562 #define regDSCL0_OTG_H_BLANK_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h4541 #define regDSCL0_OTG_H_BLANK_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h3337 #define regDSCL0_OTG_H_BLANK_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h4721 #define regDSCL0_OTG_H_BLANK_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h3812 #define regDSCL0_OTG_H_BLANK_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h3338 #define regDSCL0_OTG_H_BLANK_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h3571 #define regDSCL0_OTG_H_BLANK_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h3411 #define regDSCL0_OTG_H_BLANK_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h4032 #define regDSCL0_OTG_H_BLANK_BASE_IDX … macro