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Searched refs:regDSCC3_DSCC_PPS_CONFIG1_BASE_IDX (Results 1 – 7 of 7) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h12966 #define regDSCC3_DSCC_PPS_CONFIG1_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h10905 #define regDSCC3_DSCC_PPS_CONFIG1_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h10884 #define regDSCC3_DSCC_PPS_CONFIG1_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h12070 #define regDSCC3_DSCC_PPS_CONFIG1_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h12007 #define regDSCC3_DSCC_PPS_CONFIG1_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h12080 #define regDSCC3_DSCC_PPS_CONFIG1_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h12332 #define regDSCC3_DSCC_PPS_CONFIG1_BASE_IDX … macro