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Searched refs:regDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h13010 #define regDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h10949 #define regDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h10928 #define regDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h12114 #define regDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h12051 #define regDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h12124 #define regDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX … macro