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Searched refs:regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h12896 #define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h10835 #define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h10814 #define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h12021 #define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h11937 #define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h12812 #define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h12024 #define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h12677 #define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h13408 #define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX … macro