Home
last modified time | relevance | path

Searched refs:regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h12830 #define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h10769 #define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h10748 #define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h11955 #define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h11871 #define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h12746 #define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h11958 #define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h12611 #define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h13342 #define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro