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Searched refs:regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS (Results 1 – 9 of 9) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h12829 #define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS … macro
H A Ddcn_3_5_0_offset.h10768 #define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS … macro
H A Ddcn_3_5_1_offset.h10747 #define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS … macro
H A Ddcn_3_2_1_offset.h11954 #define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS … macro
H A Ddcn_3_1_4_offset.h11870 #define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS … macro
H A Ddcn_3_1_2_offset.h12745 #define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS … macro
H A Ddcn_3_2_0_offset.h11957 #define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS … macro
H A Ddcn_3_1_5_offset.h12610 #define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS … macro
H A Ddcn_3_1_6_offset.h13341 #define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS … macro