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Searched refs:regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h12740 #define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h10679 #define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h10658 #define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h11885 #define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h11781 #define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h12656 #define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h11882 #define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h12521 #define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h12082 #define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h13252 #define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX … macro