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Searched refs:regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h12734 #define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX macro
H A Ddcn_3_5_0_offset.h10673 #define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX macro
H A Ddcn_3_5_1_offset.h10652 #define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX macro
H A Ddcn_3_2_1_offset.h11879 #define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX macro
H A Ddcn_3_1_4_offset.h11775 #define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX macro
H A Ddcn_3_1_2_offset.h12650 #define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX macro
H A Ddcn_3_2_0_offset.h11876 #define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX macro
H A Ddcn_3_1_5_offset.h12515 #define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX macro
H A Ddcn_4_1_0_offset.h12076 #define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX macro
H A Ddcn_3_1_6_offset.h13246 #define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX macro