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Searched refs:regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h12698 #define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h10637 #define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h10616 #define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h11843 #define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h11739 #define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h12614 #define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h11840 #define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h12479 #define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h13210 #define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro