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Searched refs:regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h12605 #define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h10544 #define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h10523 #define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h11769 #define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h11645 #define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h12520 #define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h11760 #define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h12385 #define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h11934 #define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h13116 #define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX … macro