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Searched refs:regDSCC0_DSCC_MEM_POWER_CONTROL (Results 1 – 9 of 9) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h12614 #define regDSCC0_DSCC_MEM_POWER_CONTROL … macro
H A Ddcn_3_5_0_offset.h10553 #define regDSCC0_DSCC_MEM_POWER_CONTROL … macro
H A Ddcn_3_5_1_offset.h10532 #define regDSCC0_DSCC_MEM_POWER_CONTROL … macro
H A Ddcn_3_2_1_offset.h11778 #define regDSCC0_DSCC_MEM_POWER_CONTROL … macro
H A Ddcn_3_1_4_offset.h11654 #define regDSCC0_DSCC_MEM_POWER_CONTROL … macro
H A Ddcn_3_1_2_offset.h12529 #define regDSCC0_DSCC_MEM_POWER_CONTROL … macro
H A Ddcn_3_2_0_offset.h11769 #define regDSCC0_DSCC_MEM_POWER_CONTROL … macro
H A Ddcn_3_1_5_offset.h12394 #define regDSCC0_DSCC_MEM_POWER_CONTROL … macro
H A Ddcn_3_1_6_offset.h13125 #define regDSCC0_DSCC_MEM_POWER_CONTROL … macro