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Searched refs:regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h13495 #define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL … macro
H A Ddcn_3_5_0_offset.h11540 #define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL … macro
H A Ddcn_3_5_1_offset.h11519 #define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL … macro
H A Ddcn_3_2_1_offset.h12433 #define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL … macro
H A Ddcn_3_1_4_offset.h12634 #define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL … macro
H A Ddcn_3_1_2_offset.h13155 #define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL … macro
H A Ddcn_3_2_0_offset.h12449 #define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL … macro
H A Ddcn_3_1_5_offset.h13018 #define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL … macro
H A Ddcn_4_1_0_offset.h13132 #define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL … macro
H A Ddcn_3_1_6_offset.h13751 #define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL … macro