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Searched refs:regDC_PINSTRAPS_BASE_IDX (Results 1 – 24 of 24) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn316/
H A Ddcn316_resource.c1145 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), in read_dce_straps()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn314/
H A Ddcn314_resource.c1209 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), in read_dce_straps()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.c1158 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), in read_dce_straps()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn315/
H A Ddcn315_resource.c1151 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), in read_dce_straps()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c1153 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), in read_dce_straps()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c1080 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, in read_dce_straps()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn36/
H A Ddcn36_resource.c1139 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), in read_dce_straps()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn351/
H A Ddcn351_resource.c1138 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), in read_dce_straps()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.c1073 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, in read_dce_straps()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c1097 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, in read_dce_straps()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_1_4_offset.h6257 #define regDC_PINSTRAPS_BASE_IDX … macro
H A Ddpcs_4_2_0_offset.h597 #define regDC_PINSTRAPS_BASE_IDX … macro
H A Ddpcs_4_2_2_offset.h594 #define regDC_PINSTRAPS_BASE_IDX … macro
H A Ddpcs_4_2_3_offset.h630 #define regDC_PINSTRAPS_BASE_IDX … macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h11879 #define regDC_PINSTRAPS_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h9798 #define regDC_PINSTRAPS_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h9777 #define regDC_PINSTRAPS_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h10959 #define regDC_PINSTRAPS_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h10909 #define regDC_PINSTRAPS_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h11806 #define regDC_PINSTRAPS_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h10950 #define regDC_PINSTRAPS_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h11551 #define regDC_PINSTRAPS_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h11210 #define regDC_PINSTRAPS_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h12042 #define regDC_PINSTRAPS_BASE_IDX … macro