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Searched refs:regCP_RB_WPTR_POLL_ADDR_HI (Results 1 – 8 of 8) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c257 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI),
3669 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, in gfx_v11_0_cp_gfx_resume()
3706 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, in gfx_v11_0_cp_gfx_resume()
H A Dgfx_v12_0.c213 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI),
2672 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, in gfx_v12_0_cp_gfx_resume()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h357 #define regCP_RB_WPTR_POLL_ADDR_HI macro
H A Dgc_9_4_3_offset.h2808 #define regCP_RB_WPTR_POLL_ADDR_HI macro
H A Dgc_11_5_0_offset.h3397 #define regCP_RB_WPTR_POLL_ADDR_HI macro
H A Dgc_12_0_0_offset.h3704 #define regCP_RB_WPTR_POLL_ADDR_HI macro
H A Dgc_11_0_0_offset.h4424 #define regCP_RB_WPTR_POLL_ADDR_HI macro
H A Dgc_11_0_3_offset.h4648 #define regCP_RB_WPTR_POLL_ADDR_HI macro