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Searched refs:regCP_MQD_CONTROL (Results 1 – 11 of 11) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dmes_v11_0.c1209 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); in mes_v11_0_queue_init_register()
1211 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); in mes_v11_0_queue_init_register()
H A Dmes_v12_0.c1300 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); in mes_v12_0_queue_init_register()
1302 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); in mes_v12_0_queue_init_register()
H A Dgfx_v9_4_3.c1844 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); in gfx_v9_4_3_xcc_mqd_init()
1956 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, in gfx_v9_4_3_xcc_kiq_init_register()
H A Dgfx_v12_0.c3200 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, in gfx_v12_0_kiq_init_register()
H A Dgfx_v11_0.c4314 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, in gfx_v11_0_kiq_init_register()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h765 #define regCP_MQD_CONTROL … macro
H A Dgc_9_4_3_offset.h3354 #define regCP_MQD_CONTROL … macro
H A Dgc_11_5_0_offset.h3645 #define regCP_MQD_CONTROL … macro
H A Dgc_12_0_0_offset.h3912 #define regCP_MQD_CONTROL … macro
H A Dgc_11_0_0_offset.h4672 #define regCP_MQD_CONTROL … macro
H A Dgc_11_0_3_offset.h4896 #define regCP_MQD_CONTROL … macro