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Searched refs:regCP_ME_CNTL (Results 1 – 8 of 8) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c2614 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2623 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2737 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2746 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2891 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_gfx_rs64()
2894 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2899 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2916 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2921 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
3038 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_cp_gfx_enable()
[all …]
H A Dgfx_v12_0.c2054 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v12_0_config_gfx_rs64()
2057 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_config_gfx_rs64()
2062 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_config_gfx_rs64()
2076 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v12_0_config_gfx_rs64()
2079 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_config_gfx_rs64()
2084 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_config_gfx_rs64()
2140 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_set_pfp_ucode_start_addr()
2149 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_set_pfp_ucode_start_addr()
2182 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_set_me_ucode_start_addr()
2191 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_set_me_ucode_start_addr()
[all …]
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h239 #define regCP_ME_CNTL … macro
H A Dgc_9_4_3_offset.h196 #define regCP_ME_CNTL … macro
H A Dgc_11_5_0_offset.h5013 #define regCP_ME_CNTL … macro
H A Dgc_12_0_0_offset.h4058 #define regCP_ME_CNTL … macro
H A Dgc_11_0_0_offset.h6198 #define regCP_ME_CNTL … macro
H A Dgc_11_0_3_offset.h6478 #define regCP_ME_CNTL … macro