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Searched refs:regCP_MEC_RS64_CNTL (Results 1 – 6 of 6) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v12_0.c2098 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v12_0_config_gfx_rs64()
2103 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v12_0_config_gfx_rs64()
2110 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v12_0_config_gfx_rs64()
2701 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v12_0_cp_compute_enable()
2722 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); in gfx_v12_0_cp_compute_enable()
H A Dgfx_v11_0.c2935 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v11_0_config_gfx_rs64()
2940 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2947 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
3736 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v11_0_cp_compute_enable()
3757 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); in gfx_v11_0_cp_compute_enable()
4943 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0); in gfx_v11_0_soft_reset()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_5_0_offset.h6535 #define regCP_MEC_RS64_CNTL … macro
H A Dgc_12_0_0_offset.h4952 #define regCP_MEC_RS64_CNTL … macro
H A Dgc_11_0_0_offset.h7762 #define regCP_MEC_RS64_CNTL … macro
H A Dgc_11_0_3_offset.h8066 #define regCP_MEC_RS64_CNTL … macro