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Searched refs:regCP_MEC_DC_BASE_CNTL (Results 1 – 6 of 6) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c2798 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2801 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); in gfx_v11_0_config_mec_cache_rs64()
3892 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3895 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); in gfx_v11_0_cp_compute_load_microcode_rs64()
H A Dgfx_v12_0.c2794 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); in gfx_v12_0_cp_compute_load_microcode_rs64()
2797 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); in gfx_v12_0_cp_compute_load_microcode_rs64()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_5_0_offset.h6549 #define regCP_MEC_DC_BASE_CNTL … macro
H A Dgc_12_0_0_offset.h4966 #define regCP_MEC_DC_BASE_CNTL … macro
H A Dgc_11_0_0_offset.h7776 #define regCP_MEC_DC_BASE_CNTL … macro
H A Dgc_11_0_3_offset.h8080 #define regCP_MEC_DC_BASE_CNTL … macro