Home
last modified time | relevance | path

Searched refs:regCP_HQD_PQ_WPTR_LO (Results 1 – 13 of 13) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gc_9_4_3.c338 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_LO, in kgd_gfx_v9_4_3_hqd_load()
H A Damdgpu_amdkfd_gfx_v11.c234 WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_LO), in hqd_load_v11()
H A Dgfx_v9_4_3.c154 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO),
1943 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, in gfx_v9_4_3_xcc_kiq_init_register()
2001 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, in gfx_v9_4_3_xcc_kiq_init_register()
2057 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); in gfx_v9_4_3_xcc_q_fini_register()
H A Dmes_v11_0.c1510 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); in mes_v11_0_kiq_dequeue()
H A Dgfx_v12_0.c184 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO),
3187 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, in gfx_v12_0_kiq_init_register()
3237 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, in gfx_v12_0_kiq_init_register()
H A Dmes_v12_0.c1614 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); in mes_v12_0_kiq_dequeue_sched()
H A Dgfx_v11_0.c228 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO),
4301 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, in gfx_v11_0_kiq_init_register()
4351 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, in gfx_v11_0_kiq_init_register()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h805 #define regCP_HQD_PQ_WPTR_LO … macro
H A Dgc_9_4_3_offset.h3394 #define regCP_HQD_PQ_WPTR_LO … macro
H A Dgc_11_5_0_offset.h3685 #define regCP_HQD_PQ_WPTR_LO … macro
H A Dgc_12_0_0_offset.h3952 #define regCP_HQD_PQ_WPTR_LO … macro
H A Dgc_11_0_0_offset.h4712 #define regCP_HQD_PQ_WPTR_LO … macro
H A Dgc_11_0_3_offset.h4936 #define regCP_HQD_PQ_WPTR_LO … macro