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Searched refs:regCP_HQD_PQ_RPTR (Results 1 – 11 of 11) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c128 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR),
1881 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR); in gfx_v9_4_3_xcc_mqd_init()
1941 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, in gfx_v9_4_3_xcc_kiq_init_register()
2055 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); in gfx_v9_4_3_xcc_q_fini_register()
H A Dmes_v11_0.c1512 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); in mes_v11_0_kiq_dequeue()
H A Dmes_v12_0.c1616 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); in mes_v12_0_kiq_dequeue_sched()
H A Dgfx_v12_0.c158 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR),
3185 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, in gfx_v12_0_kiq_init_register()
H A Dgfx_v11_0.c202 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR),
4299 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, in gfx_v11_0_kiq_init_register()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h713 #define regCP_HQD_PQ_RPTR … macro
H A Dgc_9_4_3_offset.h3302 #define regCP_HQD_PQ_RPTR … macro
H A Dgc_11_5_0_offset.h3593 #define regCP_HQD_PQ_RPTR … macro
H A Dgc_12_0_0_offset.h3862 #define regCP_HQD_PQ_RPTR … macro
H A Dgc_11_0_0_offset.h4620 #define regCP_HQD_PQ_RPTR … macro
H A Dgc_11_0_3_offset.h4844 #define regCP_HQD_PQ_RPTR … macro