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Searched refs:regCP_HQD_PQ_DOORBELL_CONTROL (Results 1 – 13 of 13) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dmes_v11_0.c1199 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); in mes_v11_0_queue_init_register()
1202 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); in mes_v11_0_queue_init_register()
1233 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, in mes_v11_0_queue_init_register()
1501 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); in mes_v11_0_kiq_dequeue()
1506 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); in mes_v11_0_kiq_dequeue()
1508 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); in mes_v11_0_kiq_dequeue()
H A Dmes_v12_0.c1290 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); in mes_v12_0_queue_init_register()
1293 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); in mes_v12_0_queue_init_register()
1324 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, in mes_v12_0_queue_init_register()
1605 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); in mes_v12_0_kiq_dequeue_sched()
1610 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); in mes_v12_0_kiq_dequeue_sched()
1612 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); in mes_v12_0_kiq_dequeue_sched()
H A Damdgpu_amdkfd_gc_9_4_3.c309 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_DOORBELL_CONTROL, data); in kgd_gfx_v9_4_3_hqd_load()
H A Dgfx_v9_4_3.c131 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),
1811 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v9_4_3_xcc_mqd_init()
1928 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v9_4_3_xcc_kiq_init_register()
1997 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v9_4_3_xcc_kiq_init_register()
2053 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); in gfx_v9_4_3_xcc_q_fini_register()
2054 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); in gfx_v9_4_3_xcc_q_fini_register()
H A Damdgpu_amdkfd_gfx_v11.c205 WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), data); in hqd_load_v11()
H A Dgfx_v12_0.c161 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),
3172 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v12_0_kiq_init_register()
3233 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v12_0_kiq_init_register()
H A Dgfx_v11_0.c205 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),
4286 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v11_0_kiq_init_register()
4347 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v11_0_kiq_init_register()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h723 #define regCP_HQD_PQ_DOORBELL_CONTROL … macro
H A Dgc_9_4_3_offset.h3312 #define regCP_HQD_PQ_DOORBELL_CONTROL … macro
H A Dgc_11_5_0_offset.h3603 #define regCP_HQD_PQ_DOORBELL_CONTROL … macro
H A Dgc_12_0_0_offset.h3872 #define regCP_HQD_PQ_DOORBELL_CONTROL … macro
H A Dgc_11_0_0_offset.h4630 #define regCP_HQD_PQ_DOORBELL_CONTROL … macro
H A Dgc_11_0_3_offset.h4854 #define regCP_HQD_PQ_DOORBELL_CONTROL … macro