Searched refs:regCP_HQD_EOP_CONTROL (Results 1 – 9 of 9) sorted by relevance
| /linux-6.15/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v9_4_3.c | 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL),
1804 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL); in gfx_v9_4_3_xcc_mqd_init()
1924 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, in gfx_v9_4_3_xcc_kiq_init_register()
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| H A D | gfx_v12_0.c | 170 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL),
3168 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, in gfx_v12_0_kiq_init_register()
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| H A D | gfx_v11_0.c | 214 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL),
4282 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, in gfx_v11_0_kiq_init_register()
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| /linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_4_2_offset.h | 775 #define regCP_HQD_EOP_CONTROL … macro
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| H A D | gc_9_4_3_offset.h | 3364 #define regCP_HQD_EOP_CONTROL … macro
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| H A D | gc_11_5_0_offset.h | 3655 #define regCP_HQD_EOP_CONTROL … macro
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| H A D | gc_12_0_0_offset.h | 3922 #define regCP_HQD_EOP_CONTROL … macro
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| H A D | gc_11_0_0_offset.h | 4682 #define regCP_HQD_EOP_CONTROL … macro
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| H A D | gc_11_0_3_offset.h | 4906 #define regCP_HQD_EOP_CONTROL … macro
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