Home
last modified time | relevance | path

Searched refs:regCP_HQD_EOP_BASE_ADDR_HI (Results 1 – 9 of 9) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c139 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI),
1920 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, in gfx_v9_4_3_xcc_kiq_init_register()
H A Dgfx_v12_0.c169 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI),
3164 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, in gfx_v12_0_kiq_init_register()
H A Dgfx_v11_0.c213 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI),
4278 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, in gfx_v11_0_kiq_init_register()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h773 #define regCP_HQD_EOP_BASE_ADDR_HI macro
H A Dgc_9_4_3_offset.h3362 #define regCP_HQD_EOP_BASE_ADDR_HI macro
H A Dgc_11_5_0_offset.h3653 #define regCP_HQD_EOP_BASE_ADDR_HI macro
H A Dgc_12_0_0_offset.h3920 #define regCP_HQD_EOP_BASE_ADDR_HI macro
H A Dgc_11_0_0_offset.h4680 #define regCP_HQD_EOP_BASE_ADDR_HI macro
H A Dgc_11_0_3_offset.h4904 #define regCP_HQD_EOP_BASE_ADDR_HI macro