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Searched refs:regCP_HQD_DEQUEUE_REQUEST (Results 1 – 12 of 12) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c137 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST),
299 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 0x2); in gfx_v9_4_3_kiq_reset_hw_queue()
1933 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v9_4_3_xcc_kiq_init_register()
1939 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, in gfx_v9_4_3_xcc_kiq_init_register()
2031 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v9_4_3_xcc_q_fini_register()
2046 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, in gfx_v9_4_3_xcc_q_fini_register()
H A Damdgpu_amdkfd_gfx_v11.c515 WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_DEQUEUE_REQUEST), type); in hqd_destroy_v11()
H A Dmes_v11_0.c415 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); in mes_v11_0_reset_queue_mmio()
1494 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); in mes_v11_0_kiq_dequeue()
H A Dmes_v12_0.c434 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); in mes_v12_0_reset_queue_mmio()
1598 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); in mes_v12_0_kiq_dequeue_sched()
H A Dgfx_v11_0.c211 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST),
4291 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v11_0_kiq_init_register()
4297 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, in gfx_v11_0_kiq_init_register()
4858 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); in gfx_v11_0_soft_reset()
H A Dgfx_v12_0.c167 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST),
3177 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v12_0_kiq_init_register()
3183 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, in gfx_v12_0_kiq_init_register()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h739 #define regCP_HQD_DEQUEUE_REQUEST … macro
H A Dgc_9_4_3_offset.h3328 #define regCP_HQD_DEQUEUE_REQUEST … macro
H A Dgc_11_5_0_offset.h3619 #define regCP_HQD_DEQUEUE_REQUEST … macro
H A Dgc_12_0_0_offset.h3888 #define regCP_HQD_DEQUEUE_REQUEST … macro
H A Dgc_11_0_0_offset.h4646 #define regCP_HQD_DEQUEUE_REQUEST … macro
H A Dgc_11_0_3_offset.h4870 #define regCP_HQD_DEQUEUE_REQUEST … macro