Home
last modified time | relevance | path

Searched refs:regCP_HQD_ACTIVE (Results 1 – 13 of 13) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v11.c254 WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_ACTIVE), data); in hqd_load_v11()
457 act = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_ACTIVE)); in hqd_is_occupied_v11()
519 temp = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_ACTIVE)); in hqd_destroy_v11()
H A Dmes_v11_0.c420 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in mes_v11_0_reset_queue_mmio()
1240 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); in mes_v11_0_queue_init_register()
1493 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { in mes_v11_0_kiq_dequeue()
1496 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in mes_v11_0_kiq_dequeue()
H A Dmes_v12_0.c439 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in mes_v12_0_reset_queue_mmio()
1331 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); in mes_v12_0_queue_init_register()
1597 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { in mes_v12_0_kiq_dequeue_sched()
1600 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in mes_v12_0_kiq_dequeue_sched()
H A Dgfx_v9_4_3.c121 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ACTIVE),
303 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) in gfx_v9_4_3_kiq_reset_hw_queue()
1932 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { in gfx_v9_4_3_xcc_kiq_init_register()
1935 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) in gfx_v9_4_3_xcc_kiq_init_register()
2013 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, in gfx_v9_4_3_xcc_kiq_init_register()
2029 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { in gfx_v9_4_3_xcc_q_fini_register()
2034 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) in gfx_v9_4_3_xcc_q_fini_register()
2043 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); in gfx_v9_4_3_xcc_q_fini_register()
3432 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) in gfx_v9_4_3_unmap_done()
H A Damdgpu_amdkfd_gc_9_4_3.c355 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_ACTIVE, data); in kgd_gfx_v9_4_3_hqd_load()
H A Dgfx_v12_0.c3156 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); in gfx_v12_0_kiq_init_register()
3176 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { in gfx_v12_0_kiq_init_register()
3179 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in gfx_v12_0_kiq_init_register()
3249 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, in gfx_v12_0_kiq_init_register()
H A Dgfx_v11_0.c4270 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); in gfx_v11_0_kiq_init_register()
4290 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { in gfx_v11_0_kiq_init_register()
4293 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in gfx_v11_0_kiq_init_register()
4363 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, in gfx_v11_0_kiq_init_register()
4901 if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) && in gfx_v11_0_soft_reset()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h697 #define regCP_HQD_ACTIVE … macro
H A Dgc_9_4_3_offset.h3286 #define regCP_HQD_ACTIVE … macro
H A Dgc_11_5_0_offset.h3577 #define regCP_HQD_ACTIVE … macro
H A Dgc_12_0_0_offset.h3846 #define regCP_HQD_ACTIVE … macro
H A Dgc_11_0_0_offset.h4604 #define regCP_HQD_ACTIVE … macro
H A Dgc_11_0_3_offset.h4828 #define regCP_HQD_ACTIVE … macro