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Searched refs:regCP_GFX_RS64_DC_OP_CNTL (Results 1 – 6 of 6) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c2639 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2641 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2644 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2762 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2764 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2767 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
3250 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3252 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3255 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3469 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
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H A Dgfx_v12_0.c2394 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2396 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2399 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2539 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
2541 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
2544 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_5_0_offset.h6769 #define regCP_GFX_RS64_DC_OP_CNTL … macro
H A Dgc_12_0_0_offset.h5186 #define regCP_GFX_RS64_DC_OP_CNTL … macro
H A Dgc_11_0_0_offset.h7996 #define regCP_GFX_RS64_DC_OP_CNTL … macro
H A Dgc_11_0_3_offset.h8300 #define regCP_GFX_RS64_DC_OP_CNTL … macro