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Searched refs:regCP_GFX_RS64_DC_BASE_CNTL (Results 1 – 6 of 6) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c2633 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2636 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2756 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v11_0_config_me_cache_rs64()
2759 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
3244 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3247 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3463 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3466 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
H A Dgfx_v12_0.c2388 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2391 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2533 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
2536 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_5_0_offset.h6767 #define regCP_GFX_RS64_DC_BASE_CNTL … macro
H A Dgc_12_0_0_offset.h5184 #define regCP_GFX_RS64_DC_BASE_CNTL … macro
H A Dgc_11_0_0_offset.h7994 #define regCP_GFX_RS64_DC_BASE_CNTL … macro
H A Dgc_11_0_3_offset.h8298 #define regCP_GFX_RS64_DC_BASE_CNTL … macro