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Searched refs:regCP_GFX_HQD_HQ_CONTROL0 (Results 1 – 6 of 6) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_5_0_offset.h3421 #define regCP_GFX_HQD_HQ_CONTROL0 … macro
H A Dgc_12_0_0_offset.h3728 #define regCP_GFX_HQD_HQ_CONTROL0 … macro
H A Dgc_11_0_0_offset.h4448 #define regCP_GFX_HQD_HQ_CONTROL0 … macro
H A Dgc_11_0_3_offset.h4672 #define regCP_GFX_HQD_HQ_CONTROL0 … macro
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v12_0.c208 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0),
H A Dgfx_v11_0.c252 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0),