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Searched refs:regCPG_PSP_DEBUG (Results 1 – 9 of 9) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dimu_v11_0.c247 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPG_PSP_DEBUG, CPG_PSP_DEBUG__GPA_OVERRIDE_MASK, 0)
316 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPG_PSP_DEBUG, CPG_PSP_DEBUG__GPA_OVERRIDE_MASK, 0)
H A Dimu_v11_0_3.c104 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPG_PSP_DEBUG, CPG_PSP_DEBUG__GPA_OVERRIDE_MASK, 0xe0000000),
H A Dgfx_v12_0.c3486 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); in gfx_v12_0_disable_gpa_mode()
3488 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); in gfx_v12_0_disable_gpa_mode()
H A Dgfx_v11_0.c4620 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); in gfx_v11_0_disable_gpa_mode()
4622 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); in gfx_v11_0_disable_gpa_mode()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h7378 #define regCPG_PSP_DEBUG … macro
H A Dgc_11_5_0_offset.h9331 #define regCPG_PSP_DEBUG … macro
H A Dgc_12_0_0_offset.h7099 #define regCPG_PSP_DEBUG … macro
H A Dgc_11_0_0_offset.h10938 #define regCPG_PSP_DEBUG … macro
H A Dgc_11_0_3_offset.h11338 #define regCPG_PSP_DEBUG … macro