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Searched refs:regCM3_CM_POST_CSC_CONTROL_BASE_IDX (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h4937 #define regCM3_CM_POST_CSC_CONTROL_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h5828 #define regCM3_CM_POST_CSC_CONTROL_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h5807 #define regCM3_CM_POST_CSC_CONTROL_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h4537 #define regCM3_CM_POST_CSC_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h6827 #define regCM3_CM_POST_CSC_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h5918 #define regCM3_CM_POST_CSC_CONTROL_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h4538 #define regCM3_CM_POST_CSC_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h5677 #define regCM3_CM_POST_CSC_CONTROL_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h5087 #define regCM3_CM_POST_CSC_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h6138 #define regCM3_CM_POST_CSC_CONTROL_BASE_IDX … macro