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Searched refs:regCM1_CM_POST_CSC_CONTROL_BASE_IDX (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h4105 #define regCM1_CM_POST_CSC_CONTROL_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h5004 #define regCM1_CM_POST_CSC_CONTROL_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h4983 #define regCM1_CM_POST_CSC_CONTROL_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h3757 #define regCM1_CM_POST_CSC_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h5443 #define regCM1_CM_POST_CSC_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h4534 #define regCM1_CM_POST_CSC_CONTROL_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h3758 #define regCM1_CM_POST_CSC_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h4293 #define regCM1_CM_POST_CSC_CONTROL_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h4068 #define regCM1_CM_POST_CSC_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h4754 #define regCM1_CM_POST_CSC_CONTROL_BASE_IDX … macro